DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/1/26 has been entered.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4, and 6 – 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2 and 6 – 11 rejected for their dependency on claim 1.
Claim 1 recites the limitation "the mux" in line 9, claim 1 recites a limitation that it has a mux or a de-mux, where in the de-mux interpretation there is no antecedent basis for a mux. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the mux" in line 1, claim 4 depends on claim 1 which recites a limitation that it has a mux or a de-mux, where in the de-mux interpretation there is no antecedent basis for a mux. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 2, 4, 6, 9, 10, and 16 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Grobelny et al. (US Publication Number 2018/0293197, hereinafter “Grobelny”) in view of Dunstan et al. (US Publication Number 2017/0293335, hereinafter “Dunstan”) further in view of Lambert et al. (US Publication Number 2020/0341929, hereinafter “Lambert”).
6. As per claim 1, Grobelny teaches a data storage device, comprising: a plurality of memory devices (104/106, figure 1); and a controller (140, figure 1/334, figure 3), wherein the controller comprises: a first plurality of control signal input pins (334 to 332, figure 3 via pins, paragraph 42); a second plurality of control signal output pins (334 to 352, figure 3, pins paragraph 46); and a third plurality of sideband signal input pins (paragraphs 47 - 49), wherein the third plurality is less than the second plurality (associated pins for the first, second, and third control signals wherein the sideband are utilized in a manner less than the overall plurality of pins, paragraph 53).
Grobelny does not appear to explicitly disclose a controller coupled to each memory device.
However, Dunstan discloses a controller coupled to each memory device (paragraphs 50 and 51).
Grobelny and Dunstan are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny and Dunstan before him or her, to modify the controller of Grobelny to include the structure of Dunstan because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 2). Therefore, it would have been obvious to combine Dunstan with Grobelny to obtain the invention as specified in the instant claims.
Grobelny/Dunstan does not appear to explicitly disclose a controller comprises a multiplexer (mux) or a de-multiplexer (de-mux), and wherein the mux or de-mux comprises control signal input, control signal output and sideband signal input.
However, Matula discloses (figure 2) a controller comprises a multiplexer (mux) or a de-multiplexer (de-mux) (215, figure 2), and wherein the mux or de-mux comprises control signal input, control signal output and sideband signal input (input signals 270 and 280a…e, output signals 280, sideband signals 275, figure 2, paragraphs 28 and 30).
Grobelny/Dunstan and Matula are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan and Matula before him or her, to modify the controller of Grobelny/Dunstan to include the structure of Matula because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance network handling (paragraph 2). Therefore, it would have been obvious to combine Matula with Grobelny/Dunstan to obtain the invention as specified in the instant claims.
Grobelny/Dunstan/ Matula does not appear to explicitly disclose, wherein the mux is configured to receive a number of sideband signals through the third plurality of sideband signal input pins and reuse the number of received sideband signals by multiplexing the number of received sideband signals to respective ports corresponding to the plurality of memory devices.
However, Lambert discloses wherein the mux is configured to receive a number of sideband signals through the third plurality of sideband signal input pins (third plurality of sideband input pins PERST_N and PWRBRAKE_N connections od adapter sideband connection set 218 at MCU 222, paragraphs 23 and 25, figures 4a and 5a, and MCU 222 receives reset signal 400, a PERST_N signal, and throttling signal 500, a PWRBRAKE_N signal, from CPLD 210 over set 218, paragraph 33, first set is PRSNT_N and WAKE_N of set 228a/b, figure 6a, paragraphs 26 and 25, second plurality of control output pins, outbound from 22, paragraphs 26, 37, and 40) and reuse the number of received sideband signals by multiplexing the number of received sideband signals to respective ports (adapter sideband connection sets 228a/b, figure 2, paragraph 26) corresponding to the plurality of memory devices (under a stored policy MCU 222 sends a received signal to a single endpoint, reset 400 to 224a over set 228a, or sends the same received signal to every endpoint, throttle 500 over each of sets 228a/b and can reach more than two but fewer than all, the reference presents it as an answer to the single set of sideband links a PCIe connector provides, paragraphs 27, 31, 37, 39, 40, figures 4b and 5b, additionally examiner notes the claims have been interpreted in light of the actual function rather the explicit verbiage of “mux” as the number of signals output when multiplexing should be less than the number of signals input and demultiplexing takes in fewer input signals than it outputs contrary to the structure of the claim).
Grobelny/Dunstan/Matula and Lambert are analogous art because they are from the same field of endeavor of signal handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan/Matula and Lambert before him or her, to modify the signal processing of Grobelny/Dunstan/Matula to include the routing mechanism of Lambert because it would enhance the signal processing and routing according to the communication policy.
One of ordinary skill would be motivated to make such modification in order to enhance sideband communication (paragraphs 2 - 4). Therefore, it would have been obvious to combine Lambert with Grobelny/Dunstan/Matula to obtain the invention as specified in the instant claims.
Examiner note: Applicant is entitled to be his own lexicographer with respect to the use of the words mux and de-mux and Examiner has recited a prior art in light of the actual function of the claims as recited where the claims contradict the typical flow of signals represented by the phrases mux and de-mux.
7. As per claim 16, Grobelny teaches a data storage device, comprising: means to store data; and a controller, wherein the controller comprises: a multiplexer (mux) (320/342/344, figure 3) having “n” number of sideband pins (paragraphs 52 and 58), wherein “n” is an integer, and wherein the mux (mux functionality, paragraphs 44 – 46) is configured to switch between 2n contexts (switching paragraph 45) for control signals for data storage device operation (associated pins for the first, second, and third control signals wherein the sideband are utilized in a manner less than the overall plurality of pins, paragraph 53).
Grobelny does not appear to explicitly disclose a controller coupled to the means to store data and a time division multiplexer.
However, Dunstan discloses a controller coupled to the means to store data (paragraphs 50 and 51) and a time division multiplexer (paragraph 104).
Grobelny and Dunstan are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny and Dunstan before him or her, to modify the controller of Grobelny to include the structure of Dunstan because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 2). Therefore, it would have been obvious to combine Dunstan with Grobelny to obtain the invention as specified in the instant claims.
Grobelny/Dunstan does not appear to explicitly disclose wherein the mux comprises a plurality of control signal output pins, and wherein “n” is less than the plurality of control signal output pins.
However, Matula discloses (figure 2) wherein the mux (215, figure 2)comprises a plurality of control signal output pins, and wherein “n” is less than the plurality of control signal output pins (output signals 280, sideband signals 275, figure 2, paragraphs 28 and 30).
Grobelny/Dunstan and Matula are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan and Matula before him or her, to modify the controller of Grobelny/Dunstan to include the structure of Matula because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance network handling (paragraph 2). Therefore, it would have been obvious to combine Matula with Grobelny/Dunstan to obtain the invention as specified in the instant claims.
Grobelny/Dunstan/ Matula does not appear to explicitly disclose, wherein the mux is configured to receive sideband signals through an “n” number of sideband signal input pins and reuse the received sideband signals by multiplexing the received sideband signals to respective ports corresponding to the plurality of memory devices.
However, Lambert discloses wherein the mux is configured to receive sideband signals through an “n” number of sideband signal input pins (third plurality of sideband input pins PERST_N and PWRBRAKE_N connections od adapter sideband connection set 218 at MCU 222, paragraphs 23 and 25, figures 4a and 5a, and MCU 222 receives reset signal 400, a PERST_N signal, and throttling signal 500, a PWRBRAKE_N signal, from CPLD 210 over set 218, paragraph 33, first set is PRSNT_N and WAKE_N of set 228a/b, figure 6a, paragraphs 26 and 25, second plurality of control output pins, outbound from 22, paragraphs 26, 37, and 40) and reuse the received sideband signals by multiplexing the number of received sideband signals to respective ports (adapter sideband connection sets 228a/b, figure 2, paragraph 26) corresponding to the plurality of memory devices (under a stored policy MCU 222 sends a received signal to a single endpoint, reset 400 to 224a over set 228a, or sends the same received signal to every endpoint, throttle 500 over each of sets 228a/b and can reach more than two but fewer than all, the reference presents it as an answer to the single set of sideband links a PCIe connector provides, paragraphs 27, 31, 37, 39, 40, figures 4b and 5b, additionally examiner notes the claims have been interpreted in light of the actual function rather the explicit verbiage of “mux” as the number of signals output when multiplexing should be less than the number of signals input and demultiplexing takes in fewer input signals than it outputs contrary to the structure of the claim).
Grobelny/Dunstan/Matula and Lambert are analogous art because they are from the same field of endeavor of signal handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan/Matula and Lambert before him or her, to modify the signal processing of Grobelny/Dunstan/Matula to include the routing mechanism of Lambert because it would enhance the signal processing and routing according to the communication policy.
One of ordinary skill would be motivated to make such modification in order to enhance sideband communication (paragraphs 2 - 4). Therefore, it would have been obvious to combine Lambert with Grobelny/Dunstan/Matula to obtain the invention as specified in the instant claims.
Examiner note: Applicant is entitled to be his own lexicographer with respect to the use of the words mux and de-mux and Examiner has recited a prior art in light of the actual function of the claims as recited where the claims contradict the typical flow of signals represented by the phrases mux and de-mux.
8. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 1 above, as per claim 2, Grobelny teaches a device, wherein the second plurality is greater than the first plurality (associated pins for the first, second, and third control signals wherein the sideband are utilized in a manner less than the overall plurality of pins including for the second vs first, paragraph 53).
9. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 1 above, as per claim 4, Dunstan teaches a device, wherein the mux is a time division mux (TDM, paragraph 104).
10. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 1 above, as per claim 6, Grobelny teaches a device, wherein at least one sideband signal input pin of the third plurality of sideband signal input pins is a vendor specific sideband signal input pin (PCIe standard specific, paragraph 43).
11. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 1 above, as per claim 9, Grobelny teaches a device, wherein the controller is configured to deliver sideband signals from the third plurality of sideband signal input pins to each of the memory devices (via 108, figure 1).
12. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 1 above, as per claim 10, Grobelny teaches a device, wherein each memory device is coupled to the controller by a fourth plurality of signal lines that are each coupled to the second plurality of control signal output pins (additional signal lines seen interfaced to controller 334, figure 3).
13. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 1 above, as per claim 11, Grobelny teaches a device, wherein the fourth plurality is equal to the first plurality (PCIe configuration, figure 3).
14. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 16 above, as per claim 17, Grobelny teaches a device, wherein the mux has a plurality of ports (figure 3, plurality of ports, paragraph 42).
15. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 16 above, as per claim 18, Grobelny teaches a device, wherein the means to store data is coupled to the controller through the plurality of ports (plurality of ports, paragraph 17).
16. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 16 above, as per claim 19, Grobelny teaches a device, wherein the controller is configured to send sideband signals to the means to store data through a system management bus (SMBus) controller (SMBus, paragraphs 46 and 47).
17. Grobelny modified by the teachings of Dunstan/Matula/Lambert as seen in claim 16 above, as per claim 20, Grobelny teaches a device, wherein “n” is greater than 1 (more than 1 connectivity, figure 3).
18. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Grobelny in view of Dunstan in view of Matula in view of Lambert further in view of Panian et al. (US Publication Number 2024/0094792, hereinafter “Panian”)
19. As per claim 7, Grobelny/Dunstan/Matula/Lambert does not appear to explicitly disclose at least one sideband signal input pin of the third plurality of sideband signal input pins is a power loss acknowledge (PLA) input pin.
However, Panian discloses at least one sideband signal input pin of the third plurality of sideband signal input pins is a power loss acknowledge (PLA) input pin (paragraph 55).
Grobelny/Dunstan/Matula/Lambert and Panian are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan/Matula/Lambert and Panian before him or her, to modify the controller of Grobelny/Dunstan/Matula/Lambert to include the structure of Panian because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 7). Therefore, it would have been obvious to combine Panian with Grobelny/Dunstan/Matula/Lambert to obtain the invention as specified in the instant claims.
20. As per claim 8, Grobelny/Dunstan/Matula/Lambert does not appear to explicitly at least one sideband signal input pin of the third plurality of sideband signal input pins is a wake pin.
However, Panian discloses at least one sideband signal input pin of the third plurality of sideband signal input pins is a wake pin (paragraph 55).
Grobelny/Dunstan/Matula/Lambert and Panian are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan/Matula/Lambert and Panian before him or her, to modify the controller of Grobelny/Dunstan/Matula/Lambert to include the structure of Panian because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 7). Therefore, it would have been obvious to combine Panian with Grobelny/Dunstan/Matula/Lambert to obtain the invention as specified in the instant claims.
Response to Arguments
21. Applicant’s arguments with respect to claims 1, 2, 4, 6 – 11, and 16 - 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument in view of Lambert.
Conclusion
22. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Frick and Rathiniasabapathi have teachings of mux interfacing with sideband/input/output signals.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AURANGZEB HASSAN whose telephone number is (571)272-8625. The examiner can normally be reached 7 AM to 3 PM.
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AH
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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