DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
2. The disclosure is objected to because of the following informalities: paragraph 44 recites “power loss prevention (PLP) which Examiner believes should be corrected to “power loss protection (PLP)”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 2, 4, 6, 9, 10, and 16 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Grobelny et al. (US Publication Number 2018/0293197, hereinafter “Grobelny”) in view of Dunstan et al. (US Publication Number 2017/0293335, hereinafter “Dunstan”).
5. As per claim 1, Grobelny teaches a data storage device, comprising: a plurality of memory devices (104/106, figure 1); and a controller (140, figure 1/334, figure 3), wherein the controller comprises: a first plurality of control signal input pins (334 to 332, figure 3 via pins, paragraph 42); a second plurality of control signal output pins (334 to 352, figure 3, pins paragraph 46); and a third plurality of sideband signal input pins (paragraphs 47 - 49), wherein the third plurality is less than the second plurality (associated pins for the first, second, and third control signals wherein the sideband are utilized in a manner less than the overall plurality of pins, paragraph 53).
Grobelny does not appear to explicitly disclose a controller coupled to each memory device.
However, Dunstan discloses a controller coupled to each memory device (paragraphs 50 and 51).
Grobelny and Dunstan are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny and Dunstan before him or her, to modify the controller of Grobelny to include the structure of Dunstan because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 2). Therefore, it would have been obvious to combine Dunstan with Grobelny to obtain the invention as specified in the instant claims.
Grobelny/Dunstan does not appear to explicitly disclose a controller comprises a multiplexer (mux) or a de-multiplexer (de-mux), and wherein the mux or de-mux comprises control signal input, control signal output and sideband signal input.
However, Matula discloses (figure 2) a controller comprises a multiplexer (mux) or a de-multiplexer (de-mux) (215, figure 2), and wherein the mux or de-mux comprises control signal input, control signal output and sideband signal input (input signals 270 and 280a…e, output signals 280, sideband signals 275, figure 2, paragraphs 28 and 30).
Grobelny/Dunstan and Matula are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan and Matula before him or her, to modify the controller of Grobelny/Dunstan to include the structure of Matula because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance network handling (paragraph 2). Therefore, it would have been obvious to combine Matula with Grobelny/Dunstan to obtain the invention as specified in the instant claims.
6. As per claim 16, Grobelny teaches a data storage device, comprising: means to store data; and a controller, wherein the controller comprises: a multiplexer (mux) (320/342/344, figure 3) having “n” number of sideband pins (paragraphs 52 and 58), wherein “n” is an integer, and wherein the mux (mux functionality, paragraphs 44 – 46) is configured to switch between 2n contexts (switching paragraph 45) for control signals for data storage device operation (associated pins for the first, second, and third control signals wherein the sideband are utilized in a manner less than the overall plurality of pins, paragraph 53).
Grobelny does not appear to explicitly disclose a controller coupled to the means to store data and a time division multiplexer.
However, Dunstan discloses a controller coupled to the means to store data (paragraphs 50 and 51) and a time division multiplexer (paragraph 104).
Grobelny and Dunstan are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny and Dunstan before him or her, to modify the controller of Grobelny to include the structure of Dunstan because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 2). Therefore, it would have been obvious to combine Dunstan with Grobelny to obtain the invention as specified in the instant claims.
Grobelny/Dunstan does not appear to explicitly disclose wherein the mux comprises a plurality of control signal output pins, and wherein “n” is less than the plurality of control signal output pins.
However, Matula discloses (figure 2) wherein the mux (215, figure 2)comprises a plurality of control signal output pins, and wherein “n” is less than the plurality of control signal output pins (output signals 280, sideband signals 275, figure 2, paragraphs 28 and 30).
Grobelny/Dunstan and Matula are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan and Matula before him or her, to modify the controller of Grobelny/Dunstan to include the structure of Matula because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance network handling (paragraph 2). Therefore, it would have been obvious to combine Matula with Grobelny/Dunstan to obtain the invention as specified in the instant claims.
7. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 2, Grobelny teaches a device, wherein the second plurality is greater than the first plurality (associated pins for the first, second, and third control signals wherein the sideband are utilized in a manner less than the overall plurality of pins including for the second vs first, paragraph 53).
8. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 3, Grobelny teaches a device, wherein the pins are disposed on a multiplexer (mux) (mux 342/344, figure 3).
9. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 4, Dunstan teaches a device, wherein the mux is a time division mux (TDM, paragraph 104).
10. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 5, Grobelny teaches a device, wherein the pins are disposed on a de-multiplexer (demux) (demultiplexing, paragraph 59).
11. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 6, Grobelny teaches a device, wherein at least one sideband signal input pin of the third plurality of sideband signal input pins is a vendor specific sideband signal input pin (PCIe standard specific, paragraph 43).
12. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 9, Grobelny teaches a device, wherein the controller is configured to deliver sideband signals from the third plurality of sideband signal input pins to each of the memory devices (via 108, figure 1).
13. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 10, Grobelny teaches a device, wherein each memory device is coupled to the controller by a fourth plurality of signal lines that are each coupled to the second plurality of control signal output pins (additional signal lines seen interfaced to controller 334, figure 3).
14. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 1 above, as per claim 11, Grobelny teaches a device, wherein the fourth plurality is equal to the first plurality (PCIe configuration, figure 3).
15. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 16 above, as per claim 17, Grobelny teaches a device, wherein the mux has a plurality of ports (figure 3, plurality of ports, paragraph 42).
16. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 16 above, as per claim 18, Grobelny teaches a device, wherein the means to store data is coupled to the controller through the plurality of ports (plurality of ports, paragraph 17).
17. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 16 above, as per claim 19, Grobelny teaches a device, wherein the controller is configured to send sideband signals to the means to store data through a system management bus (SMBus) controller (SMBus, paragraphs 46 and 47).
18. Grobelny modified by the teachings of Dunstan/Matula as seen in claim 16 above, as per claim 20, Grobelny teaches a device, wherein “n” is greater than 1 (more than 1 connectivity, figure 3).
19. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Grobelny in view of Dunstan in view of Matula further in view of Panian et al. (US Publication Number 2024/0094792, hereinafter “Panian”)
20. As per claim 7, Grobelny/Dunstan/Matula does not appear to explicitly disclose at least one sideband signal input pin of the third plurality of sideband signal input pins is a power loss acknowledge (PLA) input pin.
However, Panian discloses at least one sideband signal input pin of the third plurality of sideband signal input pins is a power loss acknowledge (PLA) input pin (paragraph 55).
Grobelny/Dunstan/Matula and Panian are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan/Matula and Panian before him or her, to modify the controller of Grobelny/Dunstan/Matula to include the structure of Panian because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 7). Therefore, it would have been obvious to combine Panian with Grobelny/Dunstan/Matula to obtain the invention as specified in the instant claims.
21. As per claim 8, Grobelny/Dunstan/Matula does not appear to explicitly at least one sideband signal input pin of the third plurality of sideband signal input pins is a wake pin.
However, Panian discloses at least one sideband signal input pin of the third plurality of sideband signal input pins is a wake pin (paragraph 55).
Grobelny/Dunstan/Matula and Panian are analogous art because they are from the same field of endeavor of PCIe handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Grobelny/Dunstan/Matula and Panian before him or her, to modify the controller of Grobelny/Dunstan/Matula to include the structure of Panian because it would enhance the controller functionality.
One of ordinary skill would be motivated to make such modification in order to enhance I/O handling (paragraph 7). Therefore, it would have been obvious to combine Panian with Grobelny/Dunstan/Matula to obtain the invention as specified in the instant claims.
Response to Arguments
22. Applicant’s arguments with respect to claims 1, 2, 4, 6 – 11, and 16 - 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument in view of Matula.
Conclusion
23. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hong/Bhat/Heismann/Huang/Kirkpatrick/Wentroble/Khamesra/
Schnell/Zhao/Schiff/Wildhagen have teachings of mux interfacing with sideband/input/output signals.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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