DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on July 10th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election without traverse of Species III directed to Figs. 6-7 (claims 1-20) in the reply filed on July 10th, 2026 is acknowledged.
Claim Objections
Claims 9 and 13 are objected to because of the following informalities:
Claim 9 recites “an other” in line 2 and should be amended to “another” for avoiding confusing language. Appropriate correction is required.
Claim 13 recites “an other” in line 4 and should be amended to “another” for avoiding confusing language. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7-8, and 15-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 7 recites limitation “a second ratio” in line 1 while claims 1 and 7 fails to recite “a first ratio”. It is unclear to the examiners how can the second ratio exist before having the first ratio.
Claim 8 is rejected for depending on claim 7 and having the above issue incorporated into the claim.
Claim 15 recites limitation “another substrate” in line 6 while claim 15 fails to recite “a substrate”. It is unclear to the examiners how can another substrate exist before having the substrate which referring to two different substrates.
Claims 16-18 are rejected for depending on claim 15 and having the above issue incorporated into the claims.
Claim 19 recites “a forming one or more posts between a first substrate and a second substrate” in lines 1-2 while further claiming “the first layer of the first substrate comprising a first post…the second layer on the first layer of the substrate comprising a second post” in lines 3-6. It is unclear to the examiner if one or more posts are the same as the first and second posts. Furthermore, it is unclear how can the first and second posts locating between the first substrate and the second substrate while the first and second posts being parts of the first substrate.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-8, 15, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (Pub. No.: US 2022/0406723 A1), hereinafter as Tsai.
Regarding claim 1, Tsai discloses a system in Fig. 16 comprising: a first substrate (interposer 400) comprising: a first layer (a combination of first dielectric 22 and plurality of vias 42a) comprising a first post (an outermost via 42a on the left of Fig. 16) having a first width (a width of the outermost via 42a) (see [0075] and [0077]); and a second layer (a combination of dielectric layer 12 and bonding structures 18) coupled to the first layer and comprising an outer surface of the first substrate (the bottom surface of interposer 400) and a second post (an outermost bonding structure 18 on the left of Fig. 16) having a second width (a width of the outermost bonding structure 18) connected to the first post, wherein the first width is less than the second width (bonding structure 18 is wider than via 42a) (see [0041-0042); and a solder (an outermost solder material portion 450 on the left of Fig. 16) connected to the second post and configured to connect the second post to a first connector (a bonding pad 268) on a second substrate (package substrate 200) (See [0097-0098]).
Regarding claim 6, Tsai discloses the system of claim 1, wherein a first thickness of the first post (thickness of via 42a is controlled by thickness of first dielectric layer 22) is about a same thickness as a second thickness of the second post (thickness of bonding structure 18 is controlled by thickness of dielectric layer 12) (both thicknesses of dielectric layer 22 and dielectric layer 12 can be equal) (see Fig. 16 and [0041], [0075]).
Regarding claim 7, Tsai discloses the system of claim 1, wherein a second ratio between a first thickness of the first post (thickness of via 42a is controlled by thickness of first dielectric layer 22) and a second thickness of the second post (thickness of bonding structure 18 is controlled by thickness of dielectric layer 12) is greater than or about equal to 1.28 (the ratio of thickness of dielectric layer 22 to thickness of dielectric layer 12 can be selected to be 1.28) (see Fig. 16 and [0041], [0075]).
Regarding claim 8, Tsai discloses the system of claim 7, wherein the first thickness of the first post is about 37 micrometers or more (thickness of via 42a is controlled by thickness of first dielectric layer 22) (see [0075]).
Regarding claim 15, Tsai discloses a system in Fig. 16 comprising: a first layer (a combination of first dielectric 22 and plurality of vias 42a) comprising a first post (an outermost via 42a on the left of Fig. 16) having a first width (a width of the outermost via 42a) (see [0075] and [0077]); and a second layer (a combination of dielectric layer 12 and bonding structures 18) coupled to the first layer and comprising an outer surface of the first substrate (the bottom surface of interposer 400) and a second post (an outermost bonding structure 18 on the left of Fig. 16) having a second width (a width of the outermost bonding structure 18) connected to the first post, wherein the first width is less than the second width (bonding structure 18 is wider than via 42a) (see [0041-0042); and a solder (an outermost solder material portion 450 on the left of Fig. 16) connected to the second post and configured to connect the second post to a first connector (a bonding pad 268) on a another substrate (package substrate 200) (See [0097-0098]).
Regarding claim 19, Tsai discloses a method of forming a forming one or more posts (vias 42a and bonding structures 18) between a first substrate (interposer 400) and a second substrate (package substrate 200), in Fig. 16 comprising: forming a first layer (a combination of first dielectric 22 and plurality of vias 42a) of the first substrate comprising a first post (an outermost via 42a on the left of Fig. 16) having a first width (a width of the outermost via 42a) (see [0075] and [0077]); and forming a second layer (a combination of dielectric layer 12 and bonding structures 18) on the first layer of the first substrate comprising a second post (an outermost bonding structure 18 on the left of Fig. 16) having a second width (a width of the outermost bonding structure 18), wherein the second layer is an outer layer of the first substrate (the bottom layer of interposer 400) and connected to the first post, wherein the first width is less than the second width (bonding structure 18 is wider than via 42a) (see [0041-0042).
Regarding claim 20, Tsai discloses the method of claim 19, further comprising: forming a solder (an outermost solder material portion 450 on the left of Fig. 16) between the second post and a connector of the second substrate (a bonding pad 268) to connect the second post to the connector of the second substrate (See [0097-0098]).
Claims 1-3, 12, 14-15 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ino (Pub. No.: US 2008/0315415 A1).
Regarding claim 1, Ino discloses a system in Fig. 17 comprising: a first substrate (package 10A) comprising: a first layer (combination of core material 16 and through electrodes 28) comprising a first post (an outermost through electrode 28 on the left of Fig. 17) having a first width (a width of through electrode 28) (see [0040] and [0048]); and a second layer (combination of solder resist 42 and lands 30) coupled to the first layer and comprising an outer surface of the first substrate (bottom surface of package 10A) and a second post (an outermost land 30 on the left of Fig. 17) having a second width (a width of land 30) connected to the first post, wherein the first width is less than the second width (land 30 is wider than through electrode 28) (see [0044-0044]); and a solder (an outermost solder ball 76 on the left of Fig. 17) connected to the second post and configured to connect the second post to a first connector (an outermost connecting pad 74 on the left of Fig. 17) on a second substrate (motherboard 72) (see [0148-0149]).
Regarding claim 2, Ino discloses the system of claim 1, wherein the first substrate is a printed circuit board (package 10a can function as printed circuit board) and wherein the second substrate is a motherboard (motherboard 72), and wherein the solder connects the second post of the first substrate to the first connector on the second substrate (see Fig. 17 and [0048], [0148-0149]).
Regarding claim 3, Ino discloses the system of claim 1, wherein the second width of the second post is about a same width as a corresponding third width of the first connector on the second substrate (lands 30 and connecting pads 74 are identical in size) (see Fig. 17 and [0148]).
Regarding claim 12, Ino discloses the system of claim 1, wherein a first shape of the first post is configured as at least one of a bar shape or a block shape (see Fig. 17), and wherein a second shape of the second post is a same shape as the first shape of the first post (see Fig. 17).
Regarding claim 14, Ino discloses the system of claim 1, further comprising: a third layer (layer 50 and terminals 36) coupled to the first layer opposite the second layer and comprising a first interconnect (terminal 36 on the left of Fig. 17) connected to the first post (see [0041]); and a die (an upper chip 44) coupled (coupled through solder balls 78) to the third layer opposite the first layer and comprising a second connector (metal wire 48/electrodes of upper chip 44) connected to the first interconnect (see Fig. 17, [0041], [0046-0047]).
Regarding claim 15, Ino discloses a system in Fig. 17 comprising: a first layer (combination of core material 16 and through electrodes 28) comprising a first post (an outermost through electrode 28 on the left of Fig. 17) having a first width (a width of through electrode 28) (see [0040] and [0048]); and a second layer (combination of solder resist 42 and lands 30) coupled to the first layer and comprising an outer surface of the first substrate (bottom surface of package 10A) and a second post (an outermost land 30 on the left of Fig. 17) having a second width (a width of land 30) connected to the first post, wherein the first width is less than the second width (land 30 is wider than through electrode 28) (see [0044-0044]); and a solder (an outermost solder ball 76 on the left of Fig. 17) connected to the second post and configured to connect the second post to a first connector (an outermost connecting pad 74 on the left of Fig. 17) on a another substrate (motherboard 72) (see [0148-0149]).
Regarding claim 19, Ino discloses a method of forming a forming one or more posts (through electrodes 28) between a first substrate (package 10A) and a second substrate (motherboard 72), the method comprising: in Fig. 17 comprising: forming a first layer (combination of core material 16 and through electrodes 28) of the first substrate comprising a first post (an outermost through electrode 28 on the left of Fig. 17) having a first width (a width of through electrode 28) (see [0040] and [0048]); and forming a second layer (combination of solder resist 42 and lands 30) on the first layer of the first substrate comprising a second post (an outermost land 30 on the left of Fig. 17) having a second width (a width of land 30) connected to the first post, wherein the second layer is an outer layer of the first substrate (bottom surface of package 10A) wherein the first width is less than the second width (land 30 is wider than through electrode 28) (see [0044-0044]).
Regarding claim 20, Ino discloses the method of claim 19, further comprising: forming a solder (an outermost solder ball 76 on the left of Fig. 17) between the second post and a first connector (an outermost connecting pad 74 on the left of Fig. 17) of the second substrate (motherboard 72) to connect the second post to the connector of the second substrate (see [0148-0149]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (Pub. No.: US 2022/0406723 A1), hereinafter as Tsai as applied to claims 1 and 15 above.
Regarding claim 4, Tsai discloses the system of claim 1, but fails to disclose wherein a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375 because the required ratio can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 5, Tsai discloses the system of claim 4, but fails to disclose wherein the first width of the first post is about 70 micrometers or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the first width of the first post is about 70 micrometers or less because the width of the first post can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 16, Tsai discloses the system of claim 15, but fails to disclose wherein a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375 because the required ratio can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 17, Tsai discloses the system of claim 16, but fails to disclose wherein the first width of the first post is about 70 micrometers or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the first width of the first post is about 70 micrometers or less because the width of the first post can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 18, Tsai discloses the system of claim 17, wherein a second ratio between a first thickness of the first post (thickness of via 42a is controlled by thickness of first dielectric layer 22) and a second thickness of the second post (thickness of bonding structure 18 is controlled by thickness of dielectric layer 12) is greater than or about equal to 1.28 (the ratio of thickness of dielectric layer 22 to thickness of dielectric layer 12 can be selected to be 1.28) (see Fig. 16 and [0041], [0075]).
Claim 4-5, 7-8 and 16-18 is rejected under 35 U.S.C. 103 as being unpatentable over Ino (Pub. No.: US 2008/0315415 A1), as applied to claim 1 above.
Regarding claim 4, Ino discloses the system of claim 1, but fails to disclose wherein a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375 because the required ratio can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 5, Ino discloses the system of claim 4, but fails to disclose wherein the first width of the first post is about 70 micrometers or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the first width of the first post is about 70 micrometers or less because the width of the first post can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 7, Ino discloses the system of claim 1, but fails to disclose wherein a second ratio between a first thickness of the first post and a second thickness of the second post is greater than or about equal to 1.28.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein a second ratio between a first thickness of the first post and a second thickness of the second post is greater than or about equal to 1.28 because the required ratio can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 8, Ino discloses the system of claim 7, but fails to disclose wherein the first thickness of the first post is about 37 micrometers or more.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the first thickness of the first post is about 37 micrometers or more because the required thickness of the first post can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 16, Tsai discloses the system of claim 15, but fails to disclose wherein a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein a first ratio between the first width of the first post and the second width of the second post is less than or about equal to 0.375 because the required ratio can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 17, Tsai discloses the system of claim 16, but fails to disclose wherein the first width of the first post is about 70 micrometers or less.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have wherein the first width of the first post is about 70 micrometers or less because the width of the first post can be controlled for reducing contact resistance at the same time for lowering the manufacturing cost. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 18, Tsai discloses the system of claim 17, but fails to disclose wherein a second ratio between a first thickness of the first post and a second thickness of the second post) is greater than or about equal to 1.28.
Claims 1, 9-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over YAMADA (Pub. No.: US 2011/0155442 A1) in view of Ino (Pub. No.: US 2008/0315415 A1).
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Regarding claim 1, YAMADA discloses a system in Fig. 1 comprising: a first substrate (wiring package 10) comprising: a first layer (combination of insulating layer 16 and plurality of vias 17) comprising a first post (the middle via 17 on the right as shown in annotated Fig. 1 above) having a first width (a width of the middle via 17) (see [0019]); and a second layer (combination of solder resist 19 and plurality of wiring layers 18) coupled to the first layer and comprising an outer surface of the first substrate (bottom surface of wiring package 10) and a second post (the middle wiring layer 18 as shown in annotated Fig. 1 above) having a second width (a width of the middle wiring
layer 18) connected to the first post, wherein the first width is less than the second width (the middle wiring layer 18 is wider than each of the middle vias 17) (see [0022-0023]); and a solder (middle solder ball 20 as shown in annotated Fig. 1 above) connected to the second post and configured to connect the second post to a second substrate (a motherboard not shown in drawing) (see [0023]).
YAMADA fails to disclose the system comprising the solder connected the second post to a first connector on the second substrate.
Ino discloses a system in Fig. 17 comprising: a solder (an outermost solder ball 76 on the left of Fig. 17) connected to a second post (an outermost land 30 on the left of Fig. 17) and configured to connect the second post to a first connector (an outermost connecting pad 74 on the left of Fig. 17) on a second substrate (motherboard 72) (see [0148-0149]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the first connector of Ino into the system of YAMADA for having the solder connected the second post to the first connector on the second substrate because having the modified structure would provide a reliable way and low manufacturing cost for creating signal communication between the IC chips to the peripheral devices.
Regarding claim 9, the combination of YAMADA and Ino discloses the system of claim 1, wherein the first layer further comprises an other first post (the other middle via 17 as shown in annotated Fig. 1 above) coupled to the second post (see annotated Fig. 17 of YAMADA above).
Regarding claim 10, the combination of YAMADA and Ino discloses the system of claim 9, wherein a third width of the other first post is about a same width as the first width of the first post (all vias 17 have about the same width) (see annotated Fig. 1 of YAMADA above).
Regarding claim 11, the combination of YAMADA and Ino discloses the system of claim 9, wherein the first width of the first post and a third width of the other first post combined are less than the second width of the second post (a combined width of two middle vias 17 is less than the width of the middle wiring layer 18 as shown in annotated Fig. 1 of YAMADA above).
Regarding claim 13, the combination of YAMADA and Ino discloses the system of claim 1, wherein the second post is configured as at least one of a bar shape or a block shape (see annotated Fig. 1 of YAMADA above) and wherein the first layer further comprises an other first post (the other middle via 17 as shown in annotated Fig. 1 of YAMADA above) coupled to the second post.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
