DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
2. Claims 1–20 are pending in the application. Claims 1, 7, and 15 are independent. This is a first non-final Office action on the merits.
Claim Objections
3. Claim 5 is objected to because the claim concludes with a semicolon rather than a period. Appropriate correction is required.
Claim Rejections — 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 2-6 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventors regard as the invention. Claims 2-6 recite “The device of claim 1.” Claim 1 recites “A power amplifier,” rather than “a device”. Therefore, it is unclear whether “the device” in claims 2-6 refers to the power amplifier of claim 1. For examination purposes, “The device of claim 1” is interpreted as “The power amplifier of claim 1”. Appropriate correction is required.
Claim Rejections — 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1, 4, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Vorapipat et al. (“A Class-G Voltage-Mode Doherty Power Amplifier,” IEEE Journal of Solid-State Circuits, vol. 52, no. 12, pp. 3348–3360, December 2017) in view of Paul et al. (U.S. Patent Application Publication No. 2013/0281040 A1).
Figure 5 of Vorapipat has been annotated by the Examiner and will be used in the discussion of the rejection below.
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Regarding claims 1 and 15:
Vorapipat discloses ‘a power amplifier comprising: a main switched capacitor power amplifier (SCPA); and a peak SCPA in parallel with the main SCPA,’ wherein the Main PA is the main SCPA and the Peak PA is the peak SCPA. Vorapipat further discloses that ‘the main SCPA comprises a plurality of first cells electrically coupled in parallel,’ wherein cells 1–4 are coupled in parallel, and each first cell comprises ‘a first inverter’ and ‘a first capacitor electrically coupled in series with the first inverter’ (Vorapipat, Figs. 4(b) and 5 and Section III-C, p. 3351). Vorapipat also discloses ‘first control logic to apply a local oscillator (LO) signal to the first inverter or set the first inverter to a static logic state in response to a first control signal’ (Vorapipat, Fig. 13 and Section V-B, p. 3355).
Vorapipat does not disclose ‘a tri-state second inverter in parallel with the first inverter,’ that ‘the first capacitor [is] electrically coupled in series with the first inverter and the second inverter,’ or control logic to ‘apply the LO signal to the second inverter or set the second inverter to a high-impedance state in response to a second control signal.
Paul discloses two parallel amplifier portions in Figure 5, wherein transistors 3 and 4 continue active RF amplification while transistors 1 and 2 are placed in a high-impedance state by switch elements 41 and 42 connecting their gates to their sources (Paul, Fig. 5 and ¶ [0042]). Paul further discloses that the disabled elements behave as if disconnected and that this low-power configuration improves efficiency (Paul ¶ [0043]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify each first cell of Vorapipat to apply Paul’s selectively disabled parallel amplifier arrangement by providing “a tri-state second inverter in parallel with the first inverter,” coupling the second inverter to the first capacitor, and controlling the second inverter to receive the LO signal when enabled or enter a high-impedance state in response to a second control signal, to reduce power consumption and improve efficiency during low-power operation.
Vorapipat discloses “receiving an input signal at a power amplifier” (Vorapipat, Fig. 13 and Section V-B, p. 3355).
Vorapipat further discloses “generating a main output signal component via a main switched capacitor power amplifier (SCPA) of the power amplifier based on the input signal, the main SCPA comprising a plurality of first cells electrically coupled in parallel” (Vorapipat, Figs. 4(b), 5, and 13, pp. 3351 and 3355).
Vorapipat discloses each first cell comprising “a first inverter” that is activated or inactivated based on the input signal (Vorapipat, Fig. 4(b), p. 3351; Fig. 13 and Section V-B, p. 3355). Paul discloses selectively activating or inactivating parallel amplifiers, including placing one amplifier in a high-impedance state while the other amplifier continues to drive the load (Paul, Fig. 5 and ¶¶ [0042]–[0043]). It would have been obvious to operate the modified first cells of Vorapipat such that each first cell comprises “a first inverter and a tri-state second inverter in parallel with the first inverter, the first inverter and the second inverter each activated or inactivated based on the input signal,” to reduce power consumption during low-power operation.
Vorapipat discloses “generating a peak output signal component via a peak SCPA of the power amplifier” and “generating an output signal in response to the main output signal component and the peak output signal component” (Vorapipat, Fig. 5 and Section III-C, p. 3351).
Regarding Claim 4:
Vorapipat discloses “the peak SCPA comprises a plurality of second cells,” wherein the Peak PA includes parallel unit cells. Each second cell comprises “a third inverter” and “a second capacitor electrically coupled in series with the third inverter” (Vorapipat, Figs. 4(b) and 5 and Section III-C, p. 3351). Vorapipat also discloses “second control logic to apply the LO signal to the third inverter or set the third inverter to a static logic state in response to the second control signal” (Vorapipat, Fig. 13 and Section V-B, p. 3355).
6. Claims 2, 5, 7, 8, 10, 11, 14, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Vorapipat et al. in view of Paul et al., and further in view of Walling et al. (U.S. Patent Application Publication No. 2016/0336909 A1).
Regarding claims 7 and 14:
Vorapipat discloses a power amplifier having main and peak SCPAs, wherein the main SCPA includes parallel cells having an inverter, a series capacitor, and control logic responsive to an LO signal and a control signal (Vorapipat, Figs. 4(b), 5, and 13 and Sections III-C and V-B, pp. 3351 and 3355). Paul discloses selectively placing a parallel amplifier portion in a high-impedance state while another amplifier portion remains active (Paul, Fig. 5 and ¶¶ [0042]–[0043]).
Walling discloses “a controller; a transceiver communicatively coupled to the controller, the transceiver comprising a power amplifier; and an antenna circuit electrically coupled to the transceiver” (Walling, Figs. 1-4 and ¶¶ [0005]-[0006], [0025]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the power amplifier of Vorapipat, as modified by Paul, into the wireless communication system of Walling to transmit wireless signals.
Vorapipat discloses “the transceiver comprises a Bluetooth or Wi-Fi transceiver” by operating with 802.11 Wi-Fi modulation (Vorapipat, Introduction, p. 3348, and Section VI-B, pp. 3358-3359).
Regarding claims 2 and 8: Vorapipat in view of Paul do not disclose wherein each first inverter comprises a first high side switch and a first low side switch connected to the first high side switch at a first drain node, wherein each tri-state second inverter comprises a second high side switch and a second low side switch connected to the second high side switch at a second drain node, wherein each first cell further comprises: a first driver stage connected to the first high side switch and the first low side switch of the first inverter; a second driver stage connected to the second high side switch of the second inverter; and a third driver stage connected to the second low side switch of the second inverter.
Walling discloses, in Figure 7, wherein each first inverter (701-704) comprises a first high side switch (MP1) and a first low side switch (MN1) connected to the first high side switch (MP1) at a first drain node (MP1 and MN1 drains are connected together), wherein each tri-state second inverter (705-708) comprises a second high side switch (MP1) and a second low side switch (MN1) connected to the second high side switch at a second drain node (MP1 and MN1 drains are connected together), wherein each first cell further comprises: a first driver stage (710, 711) connected to the first high side switch (MP1) and the first low side switch (MN1) of the first inverter (701-704); a second driver stage (712, 713) connected to the second high side switch (MP1) of the second inverter (705-708); and a third driver stage connected to the second low side switch of the second inverter.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the inverters taught by Walling with the amplifier taught by Vorapipat and Paul, in order to reduce the size of the capacitor arrays and unary coders driving equally sized capacitors to advantageously improve the accuracy (Walling ¶ 0040).
Regarding claims 4 and 10:
Vorapipat further discloses “the peak SCPA comprises a plurality of second cells, each second cell comprising: a third inverter; a second capacitor electrically coupled in series with the third inverter; and second control logic to apply the LO signal to the third inverter or set the third inverter to a static logic state in response to the second control signal” (Vorapipat, Fig. 5 and Section III-C, p. 3351; Fig. 13 and Section V-B, p.3355).
Regarding claims 5 and 11:
Vorapipat in view of Paul does not disclose “a fourth driver stage electrically coupled between the second control logic and the third inverter.”
Walling discloses, in Figure 7, driver stages 710–713 are positioned between the control inputs and switching inverter circuits 701–708. Thus, Walling discloses “a fourth driver stage electrically coupled between the second control logic and the third inverter” (Walling, Fig. 7 and ¶¶ [0040]–[0041]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the driver stage taught by Walling in each second cell of Vorapipat, as modified by Paul, to reduce the size of the capacitor arrays and unary coders driving equally sized capacitors and thereby improve accuracy (Walling ¶ [0040]).
7. Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Vorapipat et al. in view of Paul et al. and Walling et al., and further in view of Salem et al. (U.S. Patent Application Publication No. 2018/0097486 A1).
Regarding claims 6 and 12:
Vorapipat in view of Paul does not disclose, as recited in claim 6, “a third AND gate to receive the second control signal and the LO signal to generate a third AND gate output signal,” wherein “an output of the third AND gate is electrically coupled to an input of the third inverter.” Vorapipat in view of Paul and Walling does not disclose these limitations as recited in claim 12.
Salem discloses “a third AND gate to receive the second control signal and the LO signal to generate a third AND gate output signal,” wherein “an output of the third AND gate is electrically coupled to an input of the third inverter” (Salem, Fig. 15B and ¶¶ [0086]-[0088]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement the control logic of Vorapipat and Paul using the AND gate taught by Salem so that the LO signal is applied to the third inverter only when the second control signal is enabled, thereby allowing unused power-amplifier cells to be deactivated and providing selectable gain states for efficient power-back-off operation (Salem ¶¶ [0086]-[0088]).
8. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Vorapipat et al. in view of Paul et al. and Walling et al., and further in view of Salem et al. (U.S. Patent Application Publication No. 2018/0097486 A1).
Regarding claim 13:
Vorapipat in view of Paul discloses the claimed power amplifier comprising a main SCPA and a peak SCPA in parallel with the main SCPA (Vorapipat, Fig. 5 and Section III-C, p. 3351; Paul, Fig. 5 and ¶¶ [0042]-[0043]).
Walling discloses “a controller; a transceiver communicatively coupled to the controller, the transceiver comprising a power amplifier; and an antenna circuit electrically coupled to the transceiver” (Walling, Figs. 1-4 and ¶¶ [0005]-[0006], [0025]).
Salem discloses “the power amplifier comprises a class-D amplifier” (Salem, Fig. 2A and ¶¶ [0013], [0048]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement the power amplifier as the class-D amplifier taught by Salem to provide switched power amplification.
Regarding claims 16, 17, and 18:
Vorapipat discloses “receiving an input signal at a power amplifier,” generating a main output signal component through a main SCPA, generating a peak output signal component through a peak SCPA, and generating an output signal from the main and peak output signal components (Vorapipat, Figs. 5 and 13 and Sections III-C and V-B, pp. 3351 and 3355).
Vorapipat discloses each first cell comprising a first inverter that is activated or inactivated based on the input signal (Vorapipat, Fig. 4(b), p. 3351; Fig. 13 and Section V-B, p. 3355). Paul discloses selectively activating or inactivating parallel amplifiers, including placing one amplifier in a high-impedance state while the other amplifier continues to drive the load (Paul, Fig. 5 and ¶¶ [0042]–[0043]).
Walling discloses “transmitting the output signal via an antenna,” wherein transmitter 114 transmits wireless signals through an antenna, and load resistance RL may represent an antenna (Walling, Figs.1 and 4 and ¶¶ [0005], [0025]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the antenna taught by Walling to transmit the output signal generated by the power amplifier of Vorapipat, as modified by Paul, to provide wireless communication.
Vorapipat discloses selecting a first number of active first inverters of the plurality of first cells based on the input signal and selecting active second cells of the peak SCPA based on the input signal (Vorapipat, Section III-C, p. 3351, and Fig. 9(c), p. 3353).
It would have been obvious to modify the selected main SCPA cells of Vorapipat to include the selectively activated second parallel inverters taught by Paul, such that a second number of active second inverters and the second number of active peak SCPA cells are selected based on the input signal, to reduce power consumption during low-power operation.
Walling discloses driver stages 710-713 positioned prior to and connected to switching inverter cicuits 701-708 (Walling, Fig. 7 and ¶¶ [0040]-[0041]).
9. Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vorapipat et al. in view of Paul et al., and further in view of Yang et al. (“Quadrature Switched/Floated Capacitor Power Amplifier with Reconfigurable Self-Coupling Canceling Transformer for Deep Back-Off Efficiency Enhancement,” IEEE Journal of Solid-State Circuits, vol. 56, no. 12, pp. 3715-3727, December 2021).
Regarding claims 19 and 20:
Vorapipat discloses receiving an input signal at a power amplifier, generating main and peak output signal components through respective main and peak SCPAs, and generating an output signal from the main and peak output signal components (Vorapipat, Figs. 5 and 13 and Sections III-C and V-B, pp. 3351 and 3355).
Paul discloses selectively activating or inactivating parallel amplifiers, including placing one amplifier in a high-impedance state while the other amplifier continues to drive the load (Paul, Fig.5 and ¶¶ [0042]-[0043]).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the main SCPA cells of Vorapipat to include the selectively activated parallel amplifier taught by Paul to reduce power consumption during low-power operation.
Yang discloses that the driver power consumption increases with the number n of switched-ON unit cells because each additional selected unit cell adds input capacitance and swithing power (Yang, Fig. 2, Section II-A and Eq. (2), p. 3716).
Yang further discloses that the total equivalent source resistance is R_S/n, where n is the number of switched-ON unit cells (Yang, Fig. 2 and Section II-A, p. 3716).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to operate the modified amplifier such that ‘a DC power consumption of the main SCPA increases linearly between zero active second inverters and a maximum number of active second inverters of the plurality of first cells,’ because activating additional identical parallel unit cells proportionally increases the input capacitance being driven and the resulting switching power, as taught by Yang, thereby providing efficient power-back-off operation.
It would have been obvious to operate the modified amplifier such that ‘an on resistance of the main SCPA decreases between zero active second inverters and a maximum number of active second inverters of the plurality of first cells,’ because Yang teaches that the equivalent source resistance decreases as the number of switched-ON unit cells increases, thereby reducing resistive losses during high-power operation.
Allowable Subject Matter
10. Claims 3 and 9 are objected to as depending from rejected base claims but would be allowable if rewritten in independent form to include all limitations of their respective base claims and any intervening claims. Claim 3 remains subject to the rejection under 35 U.S.C. 112(b).
Claims 3 and 9 recite specific control logic comprising a first AND gate, an OR gate, a second AND gate, and a delay that delays the first AND gate output to align it with the OR gate and second AND gate outputs, with the delay output coupled to the first inverter and the OR gate and second AND gate outputs coupled to separate (high-side and low-side) inputs of the tri-state second inverter. The prior art of record neither teaches nor reasonably suggests this particular delay-matched dual-path control logic that independently drives the high-side and low-side of the tri-state second inverter while aligning the two drive paths (thereby mitigating amplitude-to-phase distortion). See specification ¶¶ [0028]-[0029], [0039].
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure: U.S. 2025/0080059 A1 (Nordic — SCPA cell/path deactivation); U.S. 8,547,177 B1 (all-digital switched-capacitor RF power amplification); and “A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement,” IEEE J. Solid-State Circuits (2019).
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/SIAM SADMAN/Examiner, Art Unit 2843
/JOHN W POOS/Primary Examiner, Art Unit 2843
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