DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cayton et al. (Pub. No. US 2019/0102287) in view of Makhervaks et al. (Pub. No. US 2018/0032249) and Takeuchi (Pub. No. US 2014/0149985).
Claim 1:
Cayton et al. disclose a device, comprising:
a remote direct memory access network interface card having:
a first interface to a memory bus [fig. 1; par. 0022 – Interface to local NVM. (“In contrast, local NVM 70 of the RPDMA device 50 may be directly accessible to RNIC 72, without accessing the system interface 84, system interconnects, system bus or system memory 86. Rather, the RNIC 72 may be connected to the local NVM 70 via local interconnects such as local PCie connections or local interconnect DDR connections.”)];
a second interface to a peripheral interconnect [fig. 1; par. 0021 - System interface. (“To read/write to the system memory 86, the RPDMA device 50 may need to utilize system interface 84. The system interface 84 may be a PCIe interface which may transmit and receive data over a PCIe bus, or a double-data-rate interface.”)]; and
a third interface to a computer network [fig. 1; par. 0027 – “Network interfaces 76, 78 may be connected to a network (not shown), and receive data from the network and transmit data to the network.”];
wherein the remote direct memory access network interface card is configured to transfer data between a remote apparatus connected to the computer network and a memory module configured on the memory bus in response to a command received via the peripheral interconnect [figs. 1, 7; par. 0021-0022, 0064 – A write may be received over the system interface for a network connected device. The write data may be stored in the Local NVM. (“The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.” … “For example, the local NVM logic 82 may write into and read from the local NVM 70. If another device, node or machine is to store data via the RPDMA device 50, the RPDMA device 50 determines which memory 70, 80, 86A, 86B to store the data within, and then stores the data. Therefore, the RPDMA device 50 may provide a consistent interface between local and remote memory storage operations. The RPDMA device 50 may include one form factor comprising both the RNIC 72 and the local NVM 70.” … “The write operation may originate with a device (not illustrated) of the network storage architecture 60 or an application to trigger the write operation. For example, if a specific application is launched, data associated with that application may be written into the local NVM 70. That is, an application may determine that data should be moved from the system memory 86 to the local NVM 70 because the data will be used in network operations. A write request for data stored in system memory 86 is received as illustrated by flow 400, and is detected by the RDMA network logic 66. The RDMA network logic 66 may access the memory region table 68 as illustrated by flow 402, to determine which memory region to read the data from, and which memory region to write the data into.”)].
However, Cayton et al. do not specifically disclose,
wherein the host system is configured to run a driver programmed for the remote direct memory access network interface card and configured to generate the command.
In the same field of endeavor, Makhervaks et al. disclose,
wherein the host system is configured to run a driver programmed for the remote direct memory access network interface card and configured to generate the command [fig. 13; par. 0091 – “The host computer 400 includes an RNIC driver 476, RNIC queues 477, MSIX 478 and an RNIC device interface 479.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cayton et al. to include device drivers, as taught by Makhervaks et al., in order to allow the host to communicate with the device by translating the commands into instructions that the device can understand.
Cayton et al. and Makhervaks et al. disclose all the limitations above but do not specifically disclose,
the host configured to run the driver in a hypervisor, the driver to control access to the physical function.
In the same field of endeavor, Takeuchi discloses,
the host configured to run the driver in a hypervisor, the driver to control access to the physical function [par. 0040 – “The hypervisor 110 includes a PF driver 122 using the PF 141 of the NIC 101. Each of the first guest OS 111-1 and the second guest OS 111-2 of the virtual computers 11-1 and 11-2 includes a VF driver 123 using the VFs 142 of the NIC 101. On this occasion, the first guest OS 111-1 of the virtual computer 11-1 includes a sub PF driver 122A (also illustrated in FIG. 2) which functions when the hypervisor 110 fails as described later.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Cayton et al. and Makhervaks et al. to include a hypervisor, as taught by Takeuchi, in order to increase security by isolating workloads.
Claim 2 (as applied to claim 1 above):
Cayton et al. disclose the device, further comprising:
the memory bus [fig. 1 – connection to local NVM]; and
the memory module connected to the memory bus [fig. 1 – local NVM].
Claim 3 (as applied to claim 2 above):
Cayton et al. disclose the device, further comprising:
the peripheral interconnect [fig. 1; par. 0021 - System interface. (“To read/write to the system memory 86, the RPDMA device 50 may need to utilize system interface 84. The system interface 84 may be a PCIe interface which may transmit and receive data over a PCIe bus, or a double-data-rate interface.”)]; and
a host system connected to the memory bus and connected to the peripheral interconnect to send the command [fig. 1; par. 0021 - “The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.”].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cayton et al. (Pub. No. US 2019/0102287) in view of Makhervaks et al. (Pub. No. US 2018/0032249) and Takeuchi (Pub. No. US 2014/0149985) as applied to claim 1 above, and further in view of Schmidt et al. (Pub. No. US 2013/0332696).
Claim 5 (as applied to claim 1 above):
Cayton et al., Makhervaks et al., and Takeuchi disclose all the limitations above but do not specifically disclose,
wherein the remote direct memory access network interface card is configured to implement single root input/output virtualization to provide a physical function and a plurality of virtual functions.
In the same field of endeavor, Schmidt et al. disclose,
wherein the remote direct memory access network interface card is configured to implement single root input/output virtualization to provide a physical function and a plurality of virtual functions [par. 0003 – “The existing solution allows the hypervisor to exploit the virtualization provided by the RNIC adapter vendor (referred to as Single Root-I/O Virtualization or SR-IOV). The adapter virtualization requires that the hypervisor use the hardware adapter and the PCIe interface for connectivity within a single platform. This solution can become costly and induce bottlenecks within the platform.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Cayton et al., Makhervaks et al., and Takeuchi to include single root input/output virtualization, as taught by Schmidt et al., in order to enable efficient sharing of a PCIe resource.
Claim(s) 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cayton et al. (Pub. No. US 2019/0102287) in view of Makhervaks et al. (Pub. No. US 2018/0032249) and Sharon et al. (Pub. No. US 2014/0013033).
Claim 11:
Cayton et al. disclose a method, comprising:
connecting a first interface of a remote direct memory access network interface card to a memory bus [fig. 1; par. 0022 – Interface to local NVM. (“In contrast, local NVM 70 of the RPDMA device 50 may be directly accessible to RNIC 72, without accessing the system interface 84, system interconnects, system bus or system memory 86. Rather, the RNIC 72 may be connected to the local NVM 70 via local interconnects such as local PCie connections or local interconnect DDR connections.”)];
connecting a second interface of the remote direct memory access network interface card to a peripheral interconnect [fig. 1; par. 0021 - System interface. (“To read/write to the system memory 86, the RPDMA device 50 may need to utilize system interface 84. The system interface 84 may be a PCIe interface which may transmit and receive data over a PCIe bus, or a double-data-rate interface.”)];
connecting a third interface of the remote direct memory access network interface card to a computer network [fig. 1; par. 0027 – “Network interfaces 76, 78 may be connected to a network (not shown), and receive data from the network and transmit data to the network.”];
receiving, in the remote direct memory access network interface card via the peripheral interconnect, a command [figs. 1, 7; par. 0021-0022, 0064 – A write may be received over the system interface for a network connected device. (“The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.” … “For example, the local NVM logic 82 may write into and read from the local NVM 70. If another device, node or machine is to store data via the RPDMA device 50, the RPDMA device 50 determines which memory 70, 80, 86A, 86B to store the data within, and then stores the data. Therefore, the RPDMA device 50 may provide a consistent interface between local and remote memory storage operations. The RPDMA device 50 may include one form factor comprising both the RNIC 72 and the local NVM 70.” … “The write operation may originate with a device (not illustrated) of the network storage architecture 60 or an application to trigger the write operation. For example, if a specific application is launched, data associated with that application may be written into the local NVM 70. That is, an application may determine that data should be moved from the system memory 86 to the local NVM 70 because the data will be used in network operations. A write request for data stored in system memory 86 is received as illustrated by flow 400, and is detected by the RDMA network logic 66. The RDMA network logic 66 may access the memory region table 68 as illustrated by flow 402, to determine which memory region to read the data from, and which memory region to write the data into.”)]; and
transferring, in response to the command, data between a remote apparatus connected to the computer network and a memory module configured on the memory bus [figs. 1, 7; par. 0021-0022, 0064 – A write may be received over the system interface for a network connected device. The write data may be stored in the Local NVM. (“The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.” … “For example, the local NVM logic 82 may write into and read from the local NVM 70. If another device, node or machine is to store data via the RPDMA device 50, the RPDMA device 50 determines which memory 70, 80, 86A, 86B to store the data within, and then stores the data. Therefore, the RPDMA device 50 may provide a consistent interface between local and remote memory storage operations. The RPDMA device 50 may include one form factor comprising both the RNIC 72 and the local NVM 70.” … “The write operation may originate with a device (not illustrated) of the network storage architecture 60 or an application to trigger the write operation. For example, if a specific application is launched, data associated with that application may be written into the local NVM 70. That is, an application may determine that data should be moved from the system memory 86 to the local NVM 70 because the data will be used in network operations. A write request for data stored in system memory 86 is received as illustrated by flow 400, and is detected by the RDMA network logic 66. The RDMA network logic 66 may access the memory region table 68 as illustrated by flow 402, to determine which memory region to read the data from, and which memory region to write the data into.”)].
However, Cayton et al. do not specifically disclose,
running, in the host system, a driver programmed for the remote direct memory access network interface card and configured to generate the command.
In the same field of endeavor, Makhervaks et al. disclose,
running, in the host system, a driver programmed for the remote direct memory access network interface card and configured to generate the command [fig. 13; par. 0091 – “The host computer 400 includes an RNIC driver 476, RNIC queues 477, MSIX 478 and an RNIC device interface 479.”].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Cayton et al. to include device drivers, as taught by Makhervaks et al., in order to allow the host to communicate with the device by translating the commands into instructions that the device can understand.
Cayton et al. and Makhervaks et al. disclose all the limitations above but do not specifically disclose,
wherein the memory module includes a first memory and a second memory slower than the first memory
In the same field of endeavor, Sharon et al. disclose,
wherein the memory module includes a first memory and a second memory slower than the first memory [par. 0123 – “Commonly, many MLC flash memories use an SLC buffer, also known as a binary cache, for initial fast programming of the data bits (that is data from the user, or user data). After initial fast programming, the data is copied/folded from the SLC buffer into an MLC section of the flash. The SLC buffer is a section of the flash memory containing a certain amount of cells that are partitioned into 2 states, thus storing one bit per cell.”]
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of Cayton et al. and Makhervaks et al. to include a hybrid memory, as taught by Sharon et al., in order to balance performance with storage density.
Claim 12 (as applied to claim 11 above):
Cayton et al. disclose,
wherein a host system connected to the memory bus and connected to the peripheral interconnect is configured to send the command [fig. 1; par. 0021 - “The system memory 86 and RPDMA device 50 may be on a same computing device, such as a server. In some embodiments, the system memory 86 and RPDMA device 50 may in separated computing devices, such as different servers. For example, an operating system may be present the system memory 86 and local NVM 70 to the local machine as local but virtual resources. Behind that virtual implementation the system memory 86 and local NVM 70 may be on different systems.”].
Allowable Subject Matter
Claims 18-20 allowed.
Claims 6-10 and 14-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
6 February 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139