DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
1. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
2. This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: "configured to" in claims 1-8.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-5, 9-10, 12-15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Strauss et al. (Pub. No. US20110040915) in view of Kim et al. (US Patent No. US11089016)
As per claims 1 and 9, Strauss discloses a system on chip (fig.3, system 300), comprising an interrupt controller (fig.3, APIC 308/306), a processor (fig.3, core 302/304), and an on-chip bus (fig.3, crossbar 316), wherein the interrupt controller is connected to the processor through the on-chip bus (paragraph 5, lines 10-11, A dedicated bus or a system bus (e.g., crossbar 116) may be used to communicate between APICs);
the interrupt controller is configured to: store (paragraph 20, an IDIR is stores an interrupt domain identifier of an application thread currently executing on the associated core) execution environment identifiers (e.g., interrupt domain identifier) corresponding to different execution environments (e.g., recipient identifier); and
send, after receiving a first interrupt instruction, the first interrupt instruction to the processor (paragraph 8, lines 4-5, Logic in local APIC 108 sends a message to core 104 (208)); and
the processor is configured to: obtain, in response to the first interrupt instruction, a first execution environment identifier (e.g., interrupt domain identifier) corresponding to the first interrupt instruction from the interrupt controller (paragraph 41, lines 13-14, the local APIC obtains an interrupt domain identifier and a recipient identifier); and
execute, when the first execution environment identifier is the same as a second execution environment identifier (paragraph 25, If the values match, the interrupt is destined for an application thread associated with local APIC 308 and the corresponding core (e.g., core 304)), the first interrupt instruction in a corresponding execution domain of a current execution environment (paragraph 23, lines 13-14, the interrupt domain identifier in the IDIR corresponds to the identity of the interrupt-initiating application thread), wherein the second execution environment identifier is an execution environment identifier of an execution environment to which a current execution domain belongs (paragraph 20, lines 8-10, An IDIR is a state element that stores an interrupt domain identifier of an application thread currently executing on the associated core.)
Strauss discloses all the limitations as the above but does not explicitly disclose wherein the different execution environments include at least a Rich Execution Environment (REE) and a Trusted Execution Environment (TEE); and wherein the processor is a Reduced Instruction Set Computing-Five (RISC-V) architecture-based processor. However, Kim discloses this (col.6, lines 20-29, the processor core can also be a CPU core to which the RISC-V ISA has been applied. And the secure world 120 associated with the trusted execution environment (TEE) be activated. And group 112 associated with a rich execution environment (REE) may be booted, so that the normal world 110 may be activated as further cited at col.5 lines 19-29.)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Kim with the teaching of Strauss so as to reducing the cycles so as to achieve higher performance, improved power efficiency, and faster execution speeds, thus enhance the system performance.
As per claim 12, Strauss discloses an interrupt isolation method, applied on an interrupt controller (fig.3, APIC 308/306), wherein the method comprises:
storing (paragraph 20, an IDIR is stores an interrupt domain identifier of an application thread currently executing on the associated core) execution environment identifiers (e.g., interrupt domain identifier) corresponding to different execution environments (e.g., recipient identifier); and
sending, after receiving a first interrupt instruction, the first interrupt instruction to a processor (paragraph 8, lines 4-5, Logic in local APIC 108 sends a message to core 104 (208)).
As per claims 2 and 13, Strauss discloses wherein the interrupt controller comprises a register (paragraph 20, an interrupt domain identifier register) configured to store a correspondence between an interrupt source identifier (paragraph 20, user-level interrupt) and an execution environment identifier (paragraph 20, interrupt domain identifier), and the first interrupt instruction carries a target interrupt source identifier (paragraph 20, Recipient Identifier);
the processor is further configured to: send, in response to the first interrupt instruction, an access request to the interrupt controller, the access request carrying the target interrupt source identifier (paragraph 20, Each local APIC includes an interrupt domain identifier register (i.e., IDIR) and a recipient identifier register (i.e., RIR). An IDIR is a state element that stores an interrupt domain identifier of an application thread currently executing on the associated core); and
the interrupt controller is further configured to: obtain, in response to the access request, the first execution environment identifier corresponding to the target interrupt source identifier based on the stored correspondence between the interrupt source identifier and the execution environment identifier (paragraph 41, lines 13-14, the local APIC obtains an interrupt domain identifier and a recipient identifier from the payload.); and
send the first execution environment identifier to the processor (paragraph 8, lines 4-5, Logic in local APIC 108 sends a message to core 104 (208)).
As per claims 3, 10 and 14, Strauss discloses wherein the access request carries the second execution environment identifier, and the interrupt controller is further configured to: determine whether the second execution environment identifier is a stored execution environment identifier (paragraph 20, the destination is identified by a combination of the interrupt domain identifier and the recipient identifier); and
obtaining, when the second execution environment identifier is a stored execution environment identifier, the first execution environment identifier corresponding to the target interrupt source identifier (paragraph 41, lines 13-14, the local APIC obtains an interrupt domain identifier and a recipient identifier from the payload).
As per claims 4 and 15, Strauss discloses wherein the interrupt controller is further configured to reject access of the processor when the second execution environment identifier is not a stored execution environment identifier. (paragraph 25, lines 13-14, if the values do not match, then local APIC 308 sends a NACK message to local APIC 306 (416) indicating that the interrupt is not accepted by local APIC 308.)
As per claims 5 and 17, Strauss discloses wherein the interrupt controller is further configured to: obtain, after receiving the first interrupt instruction, the first execution environment identifier corresponding to the first interrupt instruction (paragraph 41, lines 13-14, the local APIC obtains an interrupt domain identifier and a recipient identifier from the payload);
add the first execution environment identifier to the first interrupt instruction (paragraph 23, an application thread executing on a core (e.g., core 302) of system 300 generates a user-level interrupt by writing to a user-level interrupt control register (i.e., UICR) of a corresponding local APIC); and
send the first interrupt instruction with the first interrupt instruction to the processor (paragraph 8, lines 4-5, Logic in local APIC 108 sends a message to core 104 (208)).
5. Claims 6-8, 11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Strauss et al. (Pub. No. US20110040915) in view of Kim et al. (US Patent No. US11089016) and further in view of Maigne et al. (US Patent No. US 8996864)
As per claims 6 and 11, Strauss discloses wherein the interrupt controller is configured to: send, when the first execution environment identifier is different from the second execution environment identifier (paragraph 20, lines 7-8, Each local APIC includes an interrupt domain identifier register (i.e., IDIR) and a recipient identifier register), the first interrupt instruction to firmware (paragraph 29, line 13-14, system-level software manages user-level applications directly.) run in a machine mode by running the current execution domain (paragraph 21, the IDIR and RIR may be saved and restored by mapping through Machine State Registers (MSR)); and
forward the first interrupt instruction by using the firmware (paragraph 20, Each local APIC includes an interrupt domain identifier register (i.e., IDIR) and a recipient identifier register (i.e., RIR). An IDIR is a state element that stores an interrupt domain identifier of an application thread currently executing on the associated core).
Strauss in view of Kim disclose all the limitation as the above but does not explicitly disclose firmware is trusted firmware. However, Maigne discloses this. (col.2, lines 33-37, all software runs in a single environment, avoiding the burden of multiple environments. Moreover, if the selected environment is a Rich Operating System (RichOS), tracking its evolutions (Internet protocol stacks in particular) is much easier.) and furthermore, Maigne notes at (col.3, lines 47-49, "trusted" execution environments are arranged to perform "critical" or "trusted" applications)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Maigne with the teaching of Strauss in view of Kim so as to create and maintain a secure and trustworthy environment for users within online platforms, services, or communities and so as to protect users from various risks, such as fraudulent activities, inappropriate content, harassment, and other forms of online harm so as to enhance the system performance.
As per claims 7 and 16, Strauss discloses all the limitations as the above but does not explicitly disclose wherein the current execution environment comprises at least a trusted execution environment and a rich execution environment, each execution environment comprises at least one execution domain comprising a corresponding operating system and application program. However, Maigne discloses this. (col.2, lines 33-37, all software runs in a single environment, avoiding the burden of multiple environments. Moreover, if the selected environment is a Rich Operating System (RichOS), tracking its evolutions (Internet protocol stacks in particular) is much easier.) and furthermore, Maigne notes at (col.3, lines 47-49, "trusted" execution environments are arranged to perform "critical" or "trusted" applications)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Maigne with the teaching of Strauss so as to create and maintain a secure and trustworthy environment for users within online platforms, services, or communities and so as to protect users from various risks, such as fraudulent activities, inappropriate content, harassment, and other forms of online harm so as to enhance the system performance.
As per claim 8, Maigne discloses wherein the interrupt controller is further configured to: set an interrupt source corresponding to the rich execution environment to a supervisor mode (col.14, lines 35-64, supervisor from the MMU point of view, although privileged instructions (e.g., CLI, STI, MOVE to/from a control register)); and set an interrupt source corresponding to the trusted execution environment to the supervisor mode or a machine mode. (col.2, lines 33-37, all software runs in a single environment, avoiding the burden of multiple environments. Moreover, if the selected environment is a Rich Operating System (RichOS), tracking its evolutions (Internet protocol stacks in particular) is much easier.) and furthermore, Maigne notes at (col.3, lines 47-49, "trusted" execution environments are arranged to perform "critical" or "trusted" applications)
Response to Amendment
6. Applicant' s amendment after final filed on 6/05/2026 have been fully considered because Chen has an earliest priority date of March 11, 2024 which is later than the earliest effective filing date (April 28,2023) of the present applicant, the finality of previous office action mailed on 4/16/2026 is hereby vacated. However, this office action is made final, it necessitated the new ground(s) of rejection presented in this office action.
7. the prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
GARBETT [Pub. No. US20240012673] discloses providing independent interrupts for routing to the different domain.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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