DETAILED ACTION
This Office action is in response to the application filed on 25 April 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature of claim 9, the primary and secondary coil conductors being located in a single plane of the semiconductor substrate, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 8 and 10-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Saegusa et al. (US 2025/0308770; “Saegusa”).
In re claim 1, Saegusa discloses a switched-mode power converter (Figs. 15-16, with further details being shown variously in Figs. 2-7 and 10) comprising a switching circuit (comprising generally the “power train” components of the converter as shown in Fig. 16, including M1, Rsns, TR, D1, C1) and a control circuit (including secondary controller 420 and primary controller 410), the switching circuit comprising a switching device (M1), the switching device configured to convert an input voltage into an output voltage by turning on and off the switching device ([0284]), the control circuit comprising:
a first control chip (410; see [0180]-[0181], Figs. 10 and 15) coupled to a control terminal of the switching device (Fig. 16: signal SG from control chip 410 provided to gate of M1);
a second control chip (420; see [0180], [0188], Figs. 10 and 15) coupled to an output terminal of the switching circuit (Fig. 16: control chip 420 receives Vdiv generated from voltage VOUT at the output terminal VCC2); and
a magnetic coupling chip (430; see [0180], [0198], Figs. 10 and 15; note that the power converter 500 of Fig. 16 is shown as part of the package 400 of Fig. 15) coupled to both the first control chip and the second control chip (see [0180] and Figs. 10 and 15), the magnetic coupling chip configured to provide a galvanically isolated communication link between the first control chip and the second control chip ([0198]; the transformer coupling provides DC-isolation which is understood to be galvanic isolation per [0037], [0049]; further note that in the power converter of Fig. 16, feedback is provided by signal Sfb from secondary side 400s to primary side 400p across the isolation barrier formed by transformer chip 430 as shown in Fig. 15).
In re claims 2 and 3, Saegusa discloses wherein the magnetic coupling chip is integrated, together with both of the first and second control chips, into an integrated circuit (IC) package (Figs. 10, 15: package 400; see also [0180]).
In re claims 7 and 8, Saegusa discloses wherein the magnetic coupling chip (see Figs. 3-7 showing more detailed views of the transformer chip: [0050]) comprises a semiconductor substrate (41; see [0051], [0053]) and first and second coil conductors both provided on the semiconductor substrate (see primary coil conductors 22, secondary coil conductors 23: Figs. 5-7 and [0050]), the first and second coil conductors providing an electromagnetic inductive communication link therebetween (i.e., they form a transformer: [0050], [0198]-[0199]), the first coil conductor coupled to the first control chip, the second coil conductor coupled to the second control chip (see Fig. 15); and wherein the first and second coil conductors are located in planes at different heights above the semiconductor substrate (see Fig. 7: coils 22 and 23 at different layers above substrate 41) and are spaced apart by an insulating layer disposed therebetween (see insulating layers 57).
In re claims 10 and 11, Saegusa discloses wherein the second control chip senses the output voltage of the switching circuit (Fig. 16: comparator 522 senses output voltage VOUT through divided voltage Vdiv) and is based on the output voltage to control the second control chip to send a control signal to the first control chip (Fig. 16: feedback control signal Sfb transmitted from secondary control chip 420 to primary control chip 410), wherein the control signal is sent to the first control chip via the magnetic coupling chip (Figs. 15; 16: magnetic coupling or transformer chip 430 situated between primary and secondary sides 400p, 400s); and wherein the control signal is in the form of short pulses (it is understood based on [0303]-[0304] that comparator 522 functions as a pulse-width modulator and thus the output Sfb is in the form of pulses which could be considered short, given there is no reference length of time for comparison).
In re claim 14, Saegusa discloses wherein the second control chip further comprises a transmitter configured to produce the control signal for turning on the switching device (Fig. 16: comparator 522 transmits the control signal Sfb).
In re claim 15, Saegusa discloses wherein the first control chip comprises a frequency-based on-time control unit (Fig. 16: 531) configured to produce a turn-off control signal (Vcp) based on a frequency of the control signal (see [0307]: given the pulsed nature of Sfb as explained above, it is understood that the charge pump output Vcp will be set to a higher or lower value in proportion to the frequency of said pulses).
In re claim 16, Saegusa discloses wherein the first control chip further comprises a drive generator module (Fig. 16: 530, 510) configured to receive the turn-off control signal (Vcp, received at comparator 533), the control signal (Sfb, received at input of 531) and a current sample signal (Vsns, received at 532) and produce a switching control signal (SG) which is applied to the control terminal of the switching device (M1).
In re claim 12, Saegusa discloses wherein the switching circuit comprises a high-frequency transformer for energy transfer, wherein the first control chip is coupled to a primary-side input terminal of the high-frequency transformer by the switching device.
In re claim 13, Saegusa discloses wherein the switching circuit is an isolated or non-isolated AC/DC converter; or the switching circuit is an isolated or non-isolated DC/DC converter (Fig. 16: circuit is an isolated DC-DC flyback converter).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Saegusa in view of Balakrishnan et al. (US 2014/0133186; “Balakrishnan”).
In re claim 4, Saegusa discloses wherein, in addition to the first control chip, the second control chip and the magnetic coupling chip, the IC package further comprises: a plurality of pins (see Fig. 15: GND1, FLT, ENA, etc.), some of which are coupled to the first control chip (e.g., GND1, FLT coupled to chip 410), and the others of which are coupled to the second control chip (e.g., VEE2, OUT1L coupled to chip 420), wherein the first control chip is coupled to the magnetic coupling chip by first metal bond wires (see example transformer chip as shown in Fig. 2: bond wires shown connecting to terminals T21-T23, for connecting to the controller chip 210 per [0046], understood as corresponding or analogous to controller chip 410), the second control chip is coupled to the magnetic coupling chip by second metal bond wires (Fig. 2: bond wires shown connecting to terminals T24, T26 for connecting with driver chip 220 per [0048], understood as corresponding or analogous to controller chip 410); and
an encapsulation body, which covers the first control chip, the second control chip, and the magnetic coupling chip (see [0199]: the three chips are “sealed,” or in other words encapsulated in the package which itself forms the body) , with the plurality of pins being exposed (it being understood that IC pins are necessarily exposed in order to connect to an external component).
Saegusa does not disclose a lead frame supporting the first control chip, the second control chip and the magnetic coupling chip and comprising the plurality of pins. Whereas Balakrishnan discloses the known use of lead frames in conventional integrated circuit packaging in order to provide mechanical support and conductive pads for the dice (chips) which may be housed within the package and to provide the pins for external connections ([0034]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Saegusa by using a lead frame partially within the encapsulation or sealing body as taught by Balakrishnan for the purpose of mechanically supporting the housed chips and to include the exposed pins as part of the lead frame in the conventional manner for providing the external connections.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Saegusa in view of Chen et al. (US 2006/0039169; “Chen”).
In re claims 5 and 6, Saegusa discloses the invention according to claim 2 as explained above, but does not disclose wherein the first control chip and the magnetic coupling chip are integrated into the IC package, and the second control chip is integrated into another IC package; and/or wherein the second control chip and the magnetic coupling chip are integrated into the IC package, and the first control chip is integrated into another IC package.
Whereas Chen discloses a power converter with isolated signal transmission means (e.g., Fig. 2A; feedback transformer Tr3) that can be integrated into chips or ICs (example shown in Fig. 6) in any suitable manner, including where the isolation transformers are in a package with the secondary-side control chip while the primary-side control chip is kept separate (as shown in Fig. 6) or conversely, the transformers could be packaged with the primary chip with the secondary chip being separate (as taught at [0043]), among other various arrangements (id.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have selected other alternative arrangements for the first control chip, the second control chip and the magnetic chip of Saegusa, including the arrangements recited in claims 5 and 6. The alternative design choices would have been chosen in an obvious manner in any instance or scenario in which they were suitable, as taught by Chen. For instance, packaging the three chips into two IC packages would enable flexibility in how the packages could be arranged on a printed circuit board.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Saegusa in view of Cheng et al. (US 2024/0014126; “Cheng”).
In re claim 9, Saegusa discloses the invention according to claim 7 as explained above, but does not further disclose wherein the first and second coil conductors are located in a single plane on the semiconductor substrate. Whereas Cheng discloses a power converter with an isolation transformer (see Fig. 2) integrated on a chip, in which the primary and secondary coils may be arranged in a same plane of the chip (see [0015] and [0055]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the transformer device of Saegusa by locating the primary and secondary coils in a single plane on the semiconductor substrate as taught by Cheng. Arranging this coils in this manner would have been expected to simplify the manufacturing of the chip by reducing the number of layers needed for fabrication.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2012/0256290 discloses an isolated power converter with primary controller, secondary controller, and an isolation transformer integrated onto separate chips;
US 2021/0376735 discloses an isolated power converter with primary controller, secondary controller, and an isolation transformer integrated onto separate chips; and
US 2024/0120964 discloses an isolated power converter with primary controller, secondary controller, and an isolation transformer integrated onto separate chips.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838