Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18646337 filed on 04/25/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election without traverse of claims 1-13, 19-25 in the reply filed on 08/06/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 24 recites the limitation “further comprising a first die coupled to the connector and a second die coupled to the connector”. The metes and bounds of the claimed limitation can not be determined for the following reasons: The highlighted terms have been defined before and lacks proper antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 19-20, 23-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mohammadighaleni et al. (US 2025/0218962).
Regarding Independent claim 1, Mohammadighaleni et al. teach a semiconductor device comprising:
a substrate (Fig. 2, elements 202, 204, 206, paragraph 0043) comprising:
two or more first layers (Fig. 2, elements 220, 218 which are vias and traces/pads analogous to the instant application, paragraph 0050-0051);
a second layer (Fig. 2, element 206, paragraph 0043),
wherein the two or more first layers are at least partially contained within the second layer (Fig. 2), and
wherein a first length of the two or more first layers is less than a second length of the second layer (Fig. 2);
a first die (Fig. 2, element 106, paragraph 0041) coupled to the second layer of the substrate (Fig. 2, paragraph 0050-0051); and
a second die (Fig. 2, element 104, paragraph 0041) coupled to the second layer (Fig. 2, paragraph 0050-0051),
wherein at least one of the two or more first layers comprises a connector layers (Fig. 2, elements 220, 218 which are vias and traces/pads, paragraph 0050-0051) coupling the first die to the second die.
Regarding claim 2, Mohammadighaleni et al. teach wherein the first die and the second die are coupled to a surface of the second layer (Fig. 2, coupled to the surface through solder balls 222, paragraph 0050) and wherein the first die is located adjacent to the second die (Fig. 2).
Regarding claim 3, Mohammadighaleni et al. teach wherein the second layer is an outermost layer of the substrate (Fig. 2).
Regarding claim 4, Mohammadighaleni et al. teach wherein the connector comprises at least one of an interconnect or a via (Fig. 2, elements 220, 218 which are vias and traces/pads, paragraph 0050-0051).
Regarding claim 5, Mohammadighaleni et al. teach wherein a first thickness of the two or more first layers is about a same thickness as a second thickness of the second layer (Fig. 2).
Regarding claim 7, Mohammadighaleni et al. teach wherein the first die is located adjacent to the second die, and wherein a first wall of the two or more first layers is located toward a first edge of the first die and a second wall of the two of more first layers is located toward a second edge of the second die (Fig. 2).
Regarding claim 8, Mohammadighaleni et al. teach wherein the first die is located adjacent to the second die, and wherein a first portion of the two or more first layers at least partially extends under a first edge of the first die and wherein a second portion of the two or more first layers at least partially extends under a second edge of the second die (Fig. 2).
Regarding claim 9, Mohammadighaleni et al. teach wherein the first portion of the two or more first layers extending under the first edge of the first die does not extend past a first center of the first die and wherein the second portion of the two or more first layers extending under the second edge of the second die does not extend past a second center of the second die (Fig. 2).
Regarding Independent claim 19, Mohammadighaleni et al. teach
a substrate (Fig. 2, elements 202, 204, 206, paragraph 0043) comprising:
two or more first layers (Fig. 2, elements 220, 218 which are vias and traces/pads analogous to the instant application, paragraph 0050-0051) comprising a connector (Fig. 2, elements 220, 218 which are vias and traces/pads, paragraph 0050-0051) configured to couple a first die (Fig. 2, element 106, paragraph 0041) to a second die (Fig. 2, element 104, paragraph 0041); and
a second layer (Fig. 2, element 206, paragraph 0043),
wherein the two or more first layers are at least partially surrounded by the second layer (Fig. 2), and
wherein a first length of the two or more first layers is less than a second length of the second layer (Fig. 2).
Regarding claim 20, Mohammadighaleni et al. teach wherein a first thickness of the two or more first layers is about a same thickness as a second thickness of the second layer (Fig. 2).
Regarding claim 23, Mohammadighaleni et al. teach wherein the two or more first layers are located only in one or more die-to-die link areas of the substrate (Fig. 2).
Regarding claim 24, Mohammadighaleni et al. teach further comprising a first die coupled to the connector and a second die coupled to the connector (Fig. 2).
Regarding claim 25, Mohammadighaleni et al. teach wherein the substrate further comprises one or more additional layers (Fig. 2, element 202, paragraph 0043), wherein the second layer is disposed on the one or more additional layers (Fig. 2), and wherein the two or more first layers are disposed on a surface of the one or more additional layers such that the second layer at least partially surrounds one or more walls of the two or more first layers (Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 10-13, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Mohammadighaleni et al. (US 2025/0218962).
Regarding claim 6, Mohammadighaleni et al. teach wherein the first die is located adjacent to the second die (Fig. 2), wherein a first length of the two or more first layers is less than a third length of the first die and the second die (paragraph 0046, 0050-0051 discloses a range of length for the circuit board 102 & dies with the motivation to reduce path length. Accordingly, the length is an art recognized variable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the lengths and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed length is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 10, Mohammadighaleni et al. teach wherein the two or more first layers comprise a first number (N) of conducting layers and a second number (N+1) of dielectric layers, wherein the dielectric layers alternate with the conducting layers (Paragraph 0048 discloses 1-10 layers. Accordingly, it would be within the grasp of one of ordinary skill in the art to choose the desired number of conducting and dielectric layers as needed taking into consideration the design dimensions, routing path etc.).
Regarding claim 11, Mohammadighaleni et al. teach wherein a second thickness of the second layer is about equal to the first number of the conducting layers multiplied by a third thickness of the conducting layers plus the second number of the dielectric layers multiplied by a fourth thickness of the dielectric layers (Paragraph 0048 discloses 1-10 layers. Accordingly, it would be within the grasp of one of ordinary skill in the art to choose the desired number of conducting and dielectric layers as needed taking into consideration the design dimensions, routing path etc. Paragraph 0049 discloses that the thickness of the conducting layers can be varied. Accordingly, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 12, Mohammadighaleni et al. teach wherein a third thickness of a conducting layer is between about a second thickness of the second layer divided by sixteen and about the second thickness of the second layer divided by eight, and wherein a fourth thickness of a dielectric layer is between about the second thickness of the second layer multiplied by five and divided by thirty-two and about the second thickness of the second layer multiplied by thirteen and divided by sixty-four (Paragraph 0048 discloses 1-10 layers. Paragraph 0049 discloses that the thickness of the conducting layers can be varied. Accordingly, the thickness is an art recognized variable. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thickness and arrive at the claimed limitation. Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention).
Regarding claim 13, Mohammadighaleni et al. teach wherein the two or more first layers comprise at least three conducting layers and at least four dielectric layers (Paragraph 0048 discloses 1-10 layers. Accordingly, it would be within the grasp of one of ordinary skill in the art to choose the desired number of conducting and dielectric layers as needed taking into consideration the design dimensions, routing path etc.), wherein the at least three conducting layers comprise a return ground layer and two routing layers (paragraph 0098 discloses the capability of conducting layers such as vias to route signal to power and ground ).
Regarding claim 21, Mohammadighaleni et al. teach wherein the two or more first layers comprise a first dielectric layer, a conducting layer disposed on the first dielectric layer, and a second dielectric layer disposed on the conducting layer (Paragraph 0048 discloses 1-10 layers. Accordingly, it would be within the grasp of one of ordinary skill in the art to choose the desired number of conducting and dielectric layers as needed taking into consideration the design dimensions, routing path etc.).
Regarding claim 22, Mohammadighaleni et al. teach wherein the first dielectric layer comprises a first via (Fig. 2, element 220, paragraph 0050), wherein the conducting layer comprises an interconnect (Fig. 2, element 218, paragraph 0051) coupled to the first via, and wherein the second dielectric layer comprises a second via (Fig. 2, element 220, paragraph 0050) coupled to the interconnect.
Citation
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20250266395 A1 discloses side by side die with a die interlink in between.
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
