Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9 recites the limitation "forming an anode region in the diode part simultaneously with the forming the base region". Based on paragraph [0058] in the specification, it appears that the applicant intended to state "forming an anode region in the diode part simultaneously with the forming of the base region". The objection can be overcome by correcting the limitation to “forming an anode region in the diode part simultaneously with the forming of the base region”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida et al. (US 20220084828 A1) hereinafter referred to as "Yoshida".
Regarding claim 1, Yoshida discloses a method of manufacturing a semiconductor device, comprising: forming a trench (Fig. 12, element 40; ¶: [0190]) from a top surface side of a semiconductor substrate of a first conductivity-type (Fig. 12, element 10; ¶: [0190, 0210]); burying an insulated gate electrode structure in the trench (Fig. 12, element 42, 44; ¶: [0225]); forming a base region of a second conductivity-type at an upper part of the semiconductor substrate so as to be in contact with the trench (Fig. 12, element 14; ¶: [0190]); forming a first main electrode region of the first conductivity-type at an upper part of the base region so as to be in contact with the trench (Fig. 12, element 12; ¶: [0190]); and forming a second main electrode region of the second conductivity-type on a bottom surface side of the semiconductor substrate (Fig. 12, element 22; ¶: [0208]), wherein a preparation condition for at least either the base region or the second main electrode region is adjusted depending on a carbon concentration in the semiconductor substrate (Fig. 29, element S1610; ¶: [0022, 0249]).
Regarding claim 2, Yoshida discloses the preparation condition being a dose amount of ion implantation for forming the second main electrode region (Fig. 12, element 22; ¶: [0265]).
Regarding claim 3, Yoshida discloses the preparation condition being a dose amount of ion implantation for forming the base region (Fig. 12, element 14; ¶: [0263]).
Regarding claim 4, Yoshida discloses the dose amount being adjusted to be lower as the carbon concentration is lower (Fig. 24, ¶: [0285, 0287]).
Regarding claim 5, Yoshida discloses the dose amount being adjusted to be lower when the carbon concentration is less than a threshold than when the carbon concentration is the threshold or greater (Fig. 24, ¶: [0285, 0287]).
Regarding claim 6, Yoshida discloses injecting a light element into the semiconductor substrate (Fig. 29, element S1608; ¶: [0105, 0106]).
Regarding claim 7, Yoshida discloses the light element being helium or proton (Fig. 29, element S1608; ¶: [0105, 0106])
Regarding claim 8, Yoshida discloses the semiconductor device being a reverse conductive insulated gate bipolar transistor further including a diode part in the semiconductor substrate (Fig. 12, element 100; ¶: [0100]).
Regarding claim 9, Yoshida discloses forming an anode region in the diode part simultaneously with the forming of the base region (Fig. 12, element 14; ¶: [0218]).
Regarding claim 10, Yoshida discloses the semiconductor substrate being manufactured by a magnetic field-applied Czochralski method (Fig. 12, element 10; ¶: [0101]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Yoshikawa (US 20090014754 A1).
Regarding claim 11, Yoshida teaches the method of manufacturing the semiconductor device of claim 1. However, Yoshida fails to teach the preparation condition being an acceleration voltage for forming the base region. Yoshikawa teaches the preparation condition being an acceleration voltage for forming the base region (Fig 5A, element 12a; ¶: [0107]).
It would have been obvious to one of ordinary skill in the art at the time of the claimed invention to form the base region by using acceleration voltage so that adjustments can be made to said voltage by changing the dose of implanted ions thus, giving more control over the base region forming process (Fig 5A, element 12a; ¶: [0107]).
Conclusion
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/I.H./Examiner, Art Unit 2899 06/04/2026
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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