Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informality: on lines 11-12, “and facing in the stiffening dielectric layer” should be “and facing the stiffening dielectric layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0267307 A1 (Lin I) in view of US 10,157,871 B1 (Yu).
Regarding claim 1, Lin I discloses, A lead frame substrate (lead frame substrate (120); FIG. 10; [0046]), comprising a circuitry layer (circuitry layer (33); FIG. 10; [0042]), terminals (terminals (23); FIG. 10; [0041]), a warpage inhibiting dielectric layer (a warpage inhibiting dielectric layer (21); FIG. 10; [0041]—an insulator is a dielectric) and a stiffening dielectric layer (stiffening dielectric layer (40); FIG. 10; [0043]—includes resin (41) which is a dielectric), wherein:
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the stiffening dielectric layer (40) laterally covers (first annotated FIG. 9, below) and is spaced from lateral surfaces of the terminals (23) by the warpage inhibiting dielectric layer (21) (first annotated FIG. 9, below);
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the circuitry layer (33) extends laterally from the terminals (23) and is located above and spaced from a top surface (first annotated FIG. 9, above) of the stiffening dielectric layer (40) by the warpage inhibiting dielectric layer (21) and has an external surface (first annotated FIG. 9, above) facing away from the stiffening dielectric layer (40) and an inner surface (first annotated FIG. 9, above) parallel to the external surface (first annotated FIG. 9, above) and facing in the stiffening dielectric layer (40);
the warpage inhibiting dielectric layer (21) includes a first interfacial portion (first annotated FIG. 9, above) between the stiffening dielectric layer (40) and the circuitry layer (33), a second interfacial portion (first annotated FIG. 9, above) between the stiffening dielectric layer(40) and the terminals (23), and a capping portion (first annotated FIG. 9, above) that extends laterally beyond a periphery (first annotated FIG. 9, above) of the circuitry layer (33) and covers the top surface (first annotated FIG. 9, above) of the stiffening dielectric layer (40).
But, Lin I does not appear to explicitly disclose, the stiffening dielectric layer has a modulus of elasticity higher than that of the warpage inhibiting dielectric layer, wherein the modulus of elasticity of the warpage inhibiting dielectric layer is less than 20 GPa.
However, in analogous art, Yu discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a modulus of elasticity of a stiffening dielectric layer (stiffening dielectric layer (316a); FIG. 1D, Col. 4, line 10) of a lead frame substrate (lead frame substrate (300); FIG. 1D; Col. 3, line 59) can be predicably formed to range between 0.5 GPa to 150 GPa (Col. 4, lines 43-44) which is higher than a modulus of elasticity of warpage inhibiting dielectric layers (warpage inhibiting dielectric layers 310a-314a); FIG. 1D, Col. 4, lines 8-9) which are formed to range between 0.1 GPa and 100 GPa (Col. 4, lines 44-47) thereby helping to alleviate deformation of lead frame substrate (300) (Col. 5, lines 1-7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Lin I and Yu before him/her that the stiffening dielectric layer (40) of Lin I has a modulus of elasticity higher than that of the warpage inhibiting dielectric layer (21) of Lin I, as taught by Yu, to alleviate deformation of the lead frame substrate (120) of Lin I, as also taught by Yu, wherein the modulus of elasticity of the warpage inhibiting dielectric layer (21) is less than 20 GPa because less than 20 GPa overlaps with the range of between 0.1 GPa and 100 GPa disclosed by Yu for a warpage inhibiting dielectric layer. Please see, MPEP 2144.05(I)—In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists.
Regarding claim 2, Lin I in view of Yu discloses, The lead frame substrate (120) of claim 1, wherein each of the terminals (23) has an external lateral surface (Lin I, annotated FIG. 10, above) at a periphery of the lead frame substrate (120) (Lin I, annotated FIG. 10, above).
Regarding claim 3, Lin I in view of Yu discloses, The lead frame substrate (120) of claim 1, wherein each of the terminals (23) includes a post portion (Lin I, second annotated FIG. 9, below) and a flange portion (second annotated FIG. 9, below), and wherein the flange portion (Lin I, second annotated FIG. 9, below) extends laterally from the post portion (Lin I, second annotated FIG. 9, below) to a periphery (Lin I, second annotated FIG. 9, below) of the lead frame substrate (120), and has a top surface (Lin I, second annotated FIG. 9, below) substantially coplanar with the external surface (Lin I, second annotated FIG. 9, below) of the circuitry layer (33) and a depression surface (Lin I, second annotated FIG. 9, below) located at a predetermined level (Lin I, second annotated FIG. 9, below) between the top surface (Lin I, second annotated FIG. 9, below) of the flange portion (Lin I, second annotated FIG. 9, below) and a bottom surface (second annotated FIG. 9, below) of the post portion (Lin I, second annotated FIG. 9, below).
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Regarding claim 4, Lin I in view of Yu discloses, The lead frame substrate (120) of claim 3, wherein the predetermined level (Lin I, second annotated FIG. 9, above) lies between the inner surface of the circuitry layer ((33); Lin I, second annotated FIG. 9, above) and the bottom surface of the post portion (Lin I, second annotated FIG. 9, above).
Regarding claim 5, Lin I in view of Yu discloses, The lead frame substrate (120) of claim 3, wherein the warpage inhibiting dielectric layer (21) has inner lateral surfaces (Lin I, third annotated FIG. 9, below) adjacent to the depression surface (Lin I, third annotated FIG. 9, below).
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Regarding claim 6, Lin I in view of Yu discloses, The lead frame substrate (120) of claim 1, wherein each of the terminals (23) has a bottom surface (third annotated FIG. 9, above) substantially coplanar with a bottom surface (third annotated FIG. 9, above) of the stiffening dielectric layer (40).
Regarding claim 12, Lin I in view of Yu discloses, A flip chip assembly (Lin I, flip chip assembly (720); FIG. 29; [0077]), comprising:
the lead frame substrate (120) of claim 1; and
a semiconductor device (Lin I, semiconductor device (81); FIG. 29; [0077]) electrically connected to the lead frame substrate (120) through bumps (Lin I, bumps (91); FIG. 29; [0077]) disposed between the semiconductor device (81) and the circuitry layer (33) of the lead frame substrate (120).
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Regarding claim 13, Lin I in view of Yu discloses, The flip chip assembly (720) of claim 12, further comprising a sealing material (Yu, sealing material (200); FIG. 1B; Col. 3, lines 28-33) encapsulating the semiconductor device (Yu, semiconductor device (100); FIG. 1B; Col. 3, lines 28-33) and extending laterally to a periphery (Yu, FIG. 1B) of the flip chip assembly (720).
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lin I in view of Yu and further in view of US 2019/0182997 A1 (Lin II).
Regarding claim 7, Lin I in view of Yu does not appear to explicitly disclose, wherein the stiffening dielectric layer is an organic material with a glass reinforcement configured to suppress crack propagation.
However, in analogous art, Lin II discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a stiffening dielectric layer (stiffening dielectric layer (45 and 47); FIG. 8; [0056] and [0063]) may be predicably fabricated to include an organic material with a glass reinforcement (organic material with a glass reinforcement (451); FIG. 8; [0056]). Lin II also discloses that organic material with a glass reinforcement (451) can restrain cracks from extending into stiffening dielectric layer (45) to ensure reliability of routing traces thereon ([0056]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Lin I, Yu, and Lin II before him/her that the stiffening dielectric layer (40) of Lin I in view of Yi is an organic material with a glass reinforcement configured to suppress crack propagation, as taught by Lin II, to ensure reliability of circuitry layer (33) thereon (Lin I, third annotated FIG. 9, above), as also taught by Lin II.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lin I in view of Yu and further in view of US 2019/0206756 A1 (Kim).
Regarding claim 8, Lin I in view of Yu does not appear to explicitly disclose, wherein the warpage inhibiting dielectric layer is an organic material with inorganic particle fillers.
However, in analogous art Kim discloses, that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that an organic material with an inorganic filler may be predicably used to suppress warpage of a semiconductor package ([0076]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Lin I, Yu, and Kim before him/her that warpage inhibiting dielectric layer (21) of Lin I in view of Yu is an organic material with inorganic particle fillers, as taught by Kim, to suppress warpage of lead frame substrate (120) of Lin I in view of Yu, as also taught by Kim.
Allowable Subject Matter
Claims 9-11 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 9, Lin I in view of Yu discloses, a thermal pad (Lin I, thermal pad (30); FIG. 9; [0042]), wherein the stiffening dielectric layer (40) laterally surrounds lateral surfaces of the thermal pad (30) (FIG. 9). However, the combination of Lin I in view of Yu does not appear to explicitly disclose that the stiffening dielectric layer (40) is spaced from lateral surfaces of the thermal pad (30) by a third interfacial portion of the warpage inhibiting dielectric layer (21).
Claims 10 and 11 are objected-to because they depend from claim 9.
Regarding claim 14, Lin I in view of Yu discloses, wherein (i) the lead frame substrate (120) further comprises a thermal pad (Lin I, thermal pad (30); FIG. 9; [0042]), (ii) the stiffening dielectric layer (40) laterally surrounds lateral surfaces of the thermal pad (30) (FIG. 9), and (iii) the semiconductor device (81) is superimposed over and thermally conductible with the thermal pad (30) through additional bumps (Lin I, bumps (91); FIG. 16; [0056])) between the semiconductor device (81) and the thermal pad (30). However, the combination of Lin I in view of Yu does not appear to explicitly disclose that the stiffening dielectric layer (40) is spaced from lateral surfaces of the thermal pad (30) by a third interfacial portion of the warpage inhibiting dielectric layer (21).
Claim 15 is objected-to because of its recitation of claim 9.
Claim 16 is objected-to because it depends on claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2019/0304916 A1 (Reichman)—Discloses that it was well-known to one of ordinary skill in the art that a dielectric stiffener layer (190b) reduces warpage by increasing stiffness of an embedded ball land substrate (100b) (FIG. 1E; [0030]) Also, discloses that dielectric stiffener layer (190b) has a modulus of elasticity (e.g., 3 GPa or greater) greater than the modulus of elasticity of coreless substrate (120b) (FIG. 1E; [0030]).
US 10,804,205 B1 (Lin III)—Discloses a stiffener ((20); FIG. 2; Col. 4, line 19) and a lead frame substrate (FIG. 6) and flip chip assembly (FIG. 6) that merit attention because they include many of the elements and limitations of the claims of the application.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights