Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1-6, 8, 12, 14-17, 19 and 20 have been considered but are moot because applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the fee set forth in 37 CFR 1.17(p) on 09/23/2023 prompted the new ground(s) of rejection presented in this Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9-12, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over LEE (Pub. No.: US 2020/0333958) in view of Jo et al. (Pub. No.: US 2025/0139000).
Regarding independent claim 1, LEE discloses a storage apparatus (Fig.2: memory system 110) comprising:
a memory device (Fig.2: memory device 150) including a first memory block (Fig.2: memory block 152) and a second memory block (Fig.2: memory block 154); and
a storage controller (Fig.2: controller 130) configured to control the memory device (Fig.2: memory device 150),
wherein the storage controller (Fig.2: controller 130) is configured to determine, when a first read data is requested by an external apparatus (Fig.2: Host 102) and is read from the first memory block (Fig.2: memory block 152) ([0053]-[0055]: after a read operation of reading data stored in the memory block or a program operation of programming data in the memory block is performed, the operation information managing circuitry 196 may modify or update data, information, a parameter or etc. of the memory block associated with the performed operation and during an operating period of one week, the memory system 110 may perform 10 read operations or hundreds of thousands of read operations according to requests of a user or a host), an attribute of the first read data set by the external apparatus (Fig.2: Host 102) ([0054]: the operation information managing circuitry 196 may not only update, manage and control operation information, state information, information parameters, etc. related to the plurality of memory blocks 40_1 in the memory device 150, but also determine an attribute of data stored in the plurality of memory blocks 40_1) and to copy the first read data having a first attribute to the second memory block ([0090]: The controller 130 may also perform a background operation on the memory device 150 using the processor 134. By way of example but not limitation, the background operation for the memory device 150 includes an operation (e.g., a garbage collection (GC) operation) for copying and storing data stored in an arbitrary memory block among the memory blocks 152, 154, and 156 in the memory device 150 to another arbitrary memory block. The background operation can include an operation (e.g., a wear leveling (WL) operation) to move or swap between data stored in at least one of the memory blocks 152, 154, and 156 in memory device 150 to at least another of the memory blocks 152, 154, and 156.).
However, Lee does not specifically teach the storage controller is configured to program write-requested data by an external apparatus in the first memory block.
Jo teaches the storage controller (Fig.1: storage controller 1210) is configured to program write-requested data (Fig.1: I/O request) by an external apparatus (Fig.1: Host 1100) in the first memory block (Fig.1: NVM 1230) (Fig.1 & Fig.2 and [0024]-[0026], [0033] and [0050]-[0053]: The host 1100 may transmit a read or write request to the storage device 1200. The storage controller
1210 may program data in the non-volatile memory device 1230 according to a write request from the host 1100. In the nonvolatile memory device 1230, only one memory block is selected from one die during a write operation. Accordingly, Jo teaches that a storage controller programs write-requested data from a host into a memory block, as recited in claims 1, 7 and 10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the host write programming operation, as taught by Jo into the system of Lee, in order to implement programming of data according to a write request from a host in a storage device comprising a storage controller and a non-volatile memory device.
Regarding independent claim 7, LEE discloses a storage apparatus (Fig.2: memory system 110) comprising: a memory device (Fig.2: memory device 150) including a first memory block (Fig.2: memory block 152) and a second memory block; and a storage controller (Fig.2: controller 130) configured to control the memory device (Fig.2: memory device 150), wherein the storage controller (Fig.2: controller 130) is configured to store data having a first attribute in the second memory block ([0090]: The controller 130 may also perform a background operation on the memory device 150 using the processor 134. By way of example but not limitation, the background operation for the memory device 150 includes an operation (e.g., a garbage collection (GC) operation) for copying and storing data stored in an arbitrary memory block among the memory blocks 152, 154, and 156 in the memory device 150 to another arbitrary memory block. The background operation can include an operation (e.g., a wear leveling (WL) operation) to move or swap between data stored in at least one of the memory blocks 152, 154, and 156 in memory device 150 to at least another of the memory blocks 152, 154, and 156.) according to a read request of an external apparatus (Fig.2: Host 102), based on a data attribute set by the external apparatus ([0064]: The controller 130 may include the wear levelling circuitry 198 that may perform a wear leveling operation based on the attribute of data stored in a memory block, which is determined by the operation information managing circuitry 196.).
However, Lee does not specifically teach the storage controller is configured to program write-requested data by an external apparatus in the first memory block.
Jo teaches the storage controller (Fig.1: storage controller 1210) is configured to program write-requested data (Fig.1: I/O request) by an external apparatus (Fig.1: Host 1100) in the first memory block (Fig.1: NVM 1230) (Fig.1 & Fig.2 and [0024]-[0026], [0033] and [0050]-[0053]: The host 1100 may transmit a read or write request to the storage device 1200. The storage controller
1210 may program data in the non-volatile memory device 1230 according to a write request from the host 1100. In the nonvolatile memory device 1230, only one memory block is selected from one die during a write operation. Accordingly, Jo teaches that a storage controller programs write-requested data from a host into a memory block, as recited in claims 1, 7 and 10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the host write programming operation, as taught by Jo into the system of Lee, in order to implement programming of data according to a write request from a host in a storage device comprising a storage controller and a non-volatile memory device.
Regarding independent claim 10, LEE discloses an operating method of a storage apparatus (Fig.2: memory system 110) that includes a storage controller (Fig.2: controller 130) configured to control a memory device (Fig.2: memory device 150) including a first memory block and a second memory block, the method comprising: reading, by the storage controller, a first read data requested by an external apparatus (Fig.2: Host 102) from the first memory block; determining, by the storage controller (Fig.2: controller 130), an attribute of the first read data set by the external apparatus; and copying, by the storage controller (Fig.2: controller 130) ([0090]: The controller 130 may also perform a background operation on the memory device 150 using the processor 134. By way of example but not limitation, the background operation for the memory device 150 includes an operation (e.g., a garbage collection (GC) operation) for copying and storing data stored in an arbitrary memory block among the memory blocks 152, 154, and 156 in the memory device 150 to another arbitrary memory block. The background operation can include an operation (e.g., a wear leveling (WL) operation) to move or swap between data stored in at least one of the memory blocks 152, 154, and 156 in memory device 150 to at least another of the memory blocks 152, 154, and 156.), when the first read data has a first attribute, the first read data to the second memory block ([0053]-[0055]: after a read operation of reading data stored in the memory block or a program operation of programming data in the memory block is performed, the operation information managing circuitry 196 may modify or update data, information, a parameter or etc. of the memory block associated with the performed operation and during an operating period of one week, the memory system 110 may perform 10 read operations or hundreds of thousands of read operations according to requests of a user or a host).
However, Lee does not specifically teach programming, by the storage controller, write-requested data by an external apparatus in the first memory block.
Jo teaches programming, by the storage controller (Fig.1: storage controller 1210), write-requested data (Fig.1: I/O request) by an external apparatus (Fig.1: Host 1100) in the first memory block (Fig.1: NVM 1230) (Fig.1 & Fig.2 and [0024]-[0026], [0033] and [0050]-[0053]: The host 1100
may transmit a read or write request to the storage device 1200. The storage controller 1210 may
program data in the non-volatile memory device 1230 according to a write request from the host 1100. In the nonvolatile memory device 1230, only one memory block is selected from one die during a write operation. Accordingly, Jo teaches that a storage controller programs write-requested data from a host into a memory block, as recited in claims 1, 7 and 10).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the host write programming operation, as taught by Jo into the system of Lee, in order to implement programming of data according to a write request from a host in a storage device comprising a storage controller and a non-volatile memory device.
Regarding claim 2, LEE teaches wherein the storage controller is configured to increase an access count to the second memory block, when a second read data is requested by the external apparatus and is read from the second memory block (Fig.6 and [0123]: updating counts in response to the read, program, or erase operations performed on the plurality of memory blocks (S34)).
Regarding claim 3, LEE teaches wherein the storage controller is configured to copy data of at least one second memory block in a closed state to the first memory block when a read reclaim operation is triggered ([0147]: monitoring parameters regarding a plurality of memory blocks and performing a read reclaim operation and a wear leveling operation based on the parameters).
Regarding claim 5, LEE teaches wherein the storage controller communicates with the external apparatus through a universal flash storage (UFS) interface protocol, and the attribute is included in a data packet in which the external apparatus transmits a request to the storage controller ([0070] and [0079]: The host interface 132 may process commands and data provided from the host 102, and may communicate with the host 102 through at least one of various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect-express (PCI-e or PCIe), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA)).
Regarding claim 6, LEE teaches wherein the attribute is included in a reserved area of the data packet (Fig.9 and [0029]: The controller can be configured to allocate a first memory block previously storing data which is determined to have a hot attribute among the plurality of memory blocks for programming with another data which is determined to have a cold attribute after the first memory block is erased, and allocate a second memory block previously storing data which is determined to have a cold attribute among the plurality of memory blocks for programming another data which is determined to have a hot attribute after the second memory block is erased).
Regarding claim 9, LEE teaches wherein the storage controller communicates with the external apparatus through a universal flash storage (UFS) interface protocol, and the data attribute is included in a data packet in which the external apparatus transmits a write request or the read request to the storage controller ([0070] and [0079]: The memory system 110 may perform a specific function or operation in response to a request from the host 102 and, in particular, may store data to be accessed by the host 102. The memory system 110 may be used as a main memory system or an auxiliary memory system of the host 102. The memory system 110 may be implemented with any one of various types of storage devices, which may be electrically coupled with the host 102, according to a protocol of a host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro-MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick).
Regarding claim 11, LEE teaches reading, by the storage controller, a second read data requested by the external apparatus from the second memory block; and increasing, by the storage controller, an access count to the second memory block (Fig.6 and [0123]: updating counts in response to the read, program, or erase operations performed on the plurality of memory blocks (S34)).
Regarding claim 12, LEE teaches copying, by the storage controller, data of at least one second memory block, transitioned from an open state to a close state, to the first memory block, as a read reclaim operation is triggered ([0147]: monitoring parameters regarding a plurality of memory blocks and performing a read reclaim operation and a wear leveling operation based on the parameters).
Regarding claim 14, LEE teaches wherein the storage controller communicates with the external apparatus through a universal flash storage (UFS) interface protocol, and the attribute is included in a data packet in which the external apparatus transmits a write request or a read request to the storage controller ([0070] and [0079]: The memory system 110 may perform a specific function or operation in response to a request from the host 102 and, in particular, may store data to be accessed by the host 102. The memory system 110 may be used as a main memory system or an auxiliary memory system of the host 102. The memory system 110 may be implemented with any one of various types of storage devices, which may be electrically coupled with the host 102, according to a protocol of a host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro-MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick).
Regarding claim 15, LEE teaches wherein the attribute is included in a reserved area of the data packet (Fig.9 and [0029]: The controller can be configured to allocate a first memory block previously storing data which is determined to have a hot attribute among the plurality of memory blocks for programming with another data which is determined to have a cold attribute after the first memory block is erased, and allocate a second memory block previously storing data which is determined to have a cold attribute among the plurality of memory blocks for programming another data which is determined to have a hot attribute after the second memory block is erased).
Allowable Subject Matter
Claims 4, 8 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 4 identifies the distinct features “wherein the storage controller is configured to change the second memory block to a closed state when the second memory block reaches data saturation or when the second memory block has an access count that exceeds a threshold value", which are not taught or suggested by the prior art of records.
Claim 8 identifies the distinct features “wherein the storage controller is configured to change the second memory block to a closed state when the second memory block is saturated or when the second memory block has an access count exceeding a threshold value, and to copy data of at least one second memory block to the first memory block when a read reclaim operation is triggered", which are not taught or suggested by the prior art of records.
Claim 13 identifies the distinct features “transitioning, by the storage controller, the second memory block to the close state when data are saturated or access count exceeds a threshold value", which are not taught or suggested by the prior art of records.
Claims 4, 8 and 13 would be allowable over the prior art of record because the claimed features as mentioned above in combination with other claimed features are not recited or suggested by the prior art of records.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bryson et al. (Pub. No.: US 2024/0411677) “SYSTEMS AND METHODS FOR REPROVISIONING A STORAGE DEVICE”
Considered for teachings related to storage devices, and more particularly to reprovisioning a storage device upon detecting a trigger condition.
Does not disclose or suggest wherein the storage controller is configured to program write-requested data by an external apparatus in the first memory block and to determine, when a first read data is requested by the external apparatus and is read from the first memory block, an attribute of the first read data set by the external apparatus and to copy the first read data having a first attribute to the second memory block.
LEE (Pub. No.: US 2020/0363991) “APPARATUS AND METHOD FOR SHARING A DATA ATTRIBUTE FROM A MEMORY SYSTEM, A DATA PROCESSING SYSTEM OR A NETWORK SERVER”
Considered for teachings related to nonvolatile memory comprising multiple namespaces.
Does not disclose or suggest wherein the storage controller is configured to program write-requested data by an external apparatus in the first memory block and to determine, when a first read data is requested by [[an]] the external apparatus and is read from the first memory block, an attribute of the first read data set by the external apparatus and to copy the first read data having a first attribute to the second memory block.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 8:00am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PMR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-irect.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/YONG J CHOE/Primary Examiner, Art Unit 2135