DETAILED ACTION
Claims 1-17 are present for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1-17) in the reply filed on 01/16/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 2-10 are objected to because of the following informalities:
In claim 2, lines 3, where it says “configured to generates read…” should be -- configured to generate read…--.
In claim 2, lines 4, where it says “logical al addresses of the N channels…” should be --logical addresses of the N channels…--.
In claim 2, line 8, where it says “write logic addresses of the N channels…” should be --write logical addresses of the N channels…--.
In claim 3, lines 9-10, where it says “write logic addresses of the N channels…” should be --write logical addresses of the N channels…--.
In claim 5, lines 4-5, where it says “read logical al addresses of the N channels…” should be --read logical addresses of the N channels…--.
In claim 6, lines 8-9, where it says “read logical al addresses of the N channels…” should be --read logical addresses of the N channels…--.
In claim 6, line 13, where it says “wherein he MAC unit…” should be --wherein the MAC unit…--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pratas et al. (US2021/0326405) in view of Barnard et al. (US 11,423,285).
With respect claim 1, Pratas et al. teaches a scratchpad memory (see Fig. 19 and paragraph 12; scratchpad memory 1900) storing image data of N channels (see Fig. 19; 6 channels accessing banks) and including M memories which are individually accessible (see Fig. 19 and paragraph 121; bank 2 is accessed at T=0; banks 2 and 3 are accessed at T=1; banks 2-4 are accessed at T=2; and banks 3-5 are accessed at T=3. One technique maps each line of the image/matrix so that it starts in a different bank for every contiguous operation. This way, if a column of N elements needs to be read in the steady state, all can be read in one cycle since they are in different banks. This mapping also ensures that every cycle we will access N banks and that these banks are going to change for every access), where M is an integer of 2 or more (see Fig. 19 and 121; 6 banks) and N is an integer of 2 or more (see Fig. 19; 6 channels accessing banks);
a memory controller configured to control access to the scratchpad memory (see Fig, 12 A and 12B; memory controller 1211. Also, in Fig. 25 and paragraph 134; control unit 2205 is responsible for controlling the memory 2201. In particular, one embodiment of the control unit 2205 indicates to the memory banks 2201 when to start read or write operations and on which lines); and
an MAC (multiply-accumulation) unit including a plurality of calculators (see paragraphs 98 and 106; processing unit (PU) contains 64 8-bit multiply-accumulate (MAC) units) to calculates pixel data of the N channels read from the scratchpad memory by using the memory controller and a weight parameter (see paragraph 93 and 108; inputs and weights are brought to the PU 901 from an Input/Output (JO) interface 902 using point-to-point buses 93… after four PU cycles (1-4), all the PUs 1300-1303 have both the inputs and weights required for the computation (a total of 128B in the illustrated embodiment), so they can perform the dot-product operation and accumulate the result with the previous computation if the neuron has many inputs. In one embodiment, only when the last inputs of the logical neuron are processed do the PUs 1300-1303 send back the outcome result to the IO interface 1310. Also in paragraph 121; using a mapping that ensures complete independence between the two data types (typically input data and partial results)… One technique maps each line of the image/matrix so that it starts in a different bank for every contiguous operation. This way, if a column of N elements needs to be read in the steady state, all can be read in one cycle since they are in different banks).
Pratas et al. does not teach wherein a memory controller configured to control access to the scratchpad memory such that pixel data of the N channels which are arranged at a same pixel position in image data of the N channels are respectively stored in different memories of the M memories.
However, Barnard et al. teaches wherein shaded memory locations in FIG. 10(a) illustrate the input data values that are written to the input data buffer during a first write cycle. As can be seen FIG. 10(a), the data is written to the input data buffer without a bank collision occurring… Again, the shaded memory locations in FIG. 10(b) illustrate the input data values that are written to memory during a first write cycle. As can be seen, in the case of FIG. 10(b) no banks collisions occur during the writing of data to the input data buffer. The second implementation allows the data to be read from memory, a single x,y location (and across all planes) at a time (i.e., data is stored at a single x,y location (and across all planes)) (see column 14, lines 30-67 and column 15, lines 1-25).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the device taught by Pratas et al. to include the above mentioned so no banks collisions occur during the writing of data (see Barnard, column 14, lines 40-44).
With respect claim 11, Pratas et al. teaches a DMA (Direct Memory Access) controller configured to control data transfer between the scratchpad memory and a main memory (see paragraph 80; DMA unit).
With respect claim 12, Pratas et al. teaches a DSP (Digital Signal Processor) performing signal operations on the image data of the N channels stored in the scratchpad memory (see paragraph 77; digital signal processing (DSP) units).
Allowable Subject Matter
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
No prior art or combination of prior art teaches or suggest wherein the memory controller includes: a read access controller configured to generates read logical al addresses of the N channels for reading the pixel data of the N channels, respectively, when the pixel data of the N channels are read from the scratchpad memory, and a write access controller configured to generate write logic addresses of the N channels for storing the pixel data of the N channels, respectively, when the pixel data of the N channels are written to the scratchpad memory as recited in claim 2.
Brandl et al. (US2018/0019006) teaches wherein physical interface 416 bidirectionally connects memory channel controller 414 to PHY 440, and conforms to the DFI Specification. Memory channel 420 includes a host interface 422, a memory channel controller 424, and a physical interface 426… Memory controller 400 is an instantiation of a memory controller having two memory channel controllers and uses a shared power engine 430 to control operation of both memory channel controller 414 and memory channel controller 424 (see Fig. 4, paragraph 39).
However, Brandl et al. does not teach wherein the memory controller includes: a read access controller configured to generates read logical al addresses of the N channels for reading the pixel data of the N channels, and a write access controller configured to generate write logic addresses of the N channels for storing the pixel data of the N channels, respectively, when the pixel data of the N channels are written to the scratchpad memory as recited in claim 2.
Lee et al. (US2020/0151070) teaches wherein each memory controller 720 manages a separate memory channel (see Fig. 7 and paragraph 95)… the memory device writes data from the scratchpad data of column[n] into the same column addressed cells in the repaired WL[k], block 676. These operations move the data from the scratchpad into the WL that has been mapped to the logical address of the failure WL (see paragraphs 83 and 86).
However, Lee et al. does not teach wherein the memory controller includes: a read access controller configured to generates read logical al addresses of the N channels for reading the pixel data of the N channels, and a write access controller configured to generate write logic addresses of the N channels for storing the pixel data of the N channels, respectively, when the pixel data of the N channels are written to the scratchpad memory as recited in claim 2.
Claims 13-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
No prior art or combination of prior art teaches or suggest a memory controller configured to control access to the scratchpad memory based on a setting value of a register; a CPU (Central Processing Unit) configured to determine the setting value of the register for the memory controller; and wherein the CPU determines the setting value of the register such that pixel data of N channels which are arranged at a same pixel position in image data of the N channels are respectively stored in different memories of the M memories as recited in claims 13.
Champion et al. (US 6,803,917) teaches wherein two pixels have been stored in parallel in two respective memories using the same address. Referring to FIGS. 6A, 6B, and 6C, pixel 0 and pixel 1 are stored at the same time at the same address in first memory device 650 and second memory device 675, respectively (see column 15, lines 46-51); and wherein memory controller 1855 receives pixel data from video source 1805 to store in memories 1810 and 1815. Memory controller 1855 retrieves pixel data from memories 1810 and 1815 and provides the pixel data to video destination 1825... Memory controller 1855 receives signals from video source 1805 and video destination 1825 through control lines 1845 and 1870, respectively, indicating whether pixel data is to be stored to or retrieved from memories 1810 and 1815. Memory controller 1855 generates addresses and supplies these addresses along with control signals to memories 1810 and 1815 (see column 22, lines 66-67 and column 23, lines 1-11).
However, Champion et al. does not teach a memory controller configured to control access to the scratchpad memory based on a setting value of a register; a CPU (Central Processing Unit) configured to determine the setting value of the register for the memory controller; and wherein the CPU determines the setting value of the register such that pixel data of N channels which are arranged at a same pixel position in image data of the N channels are respectively stored in different memories of the M memories as recited in claims 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zivkovic et al. (US2018/0095929) teaches scratchpad memory with bank tiling for localized and random data access.
Youn et al. (US11,347,652) teaches devices and methods for using a banked memory structure with accelerators.
Norrie et al. (US 2021/0232898) teaches 8shared scratchpad memory with parallel load-store.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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