Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 08/11/2026 have been fully considered but they are not persuasive.
In response to applicant’s argument in page 7, the applicant asserts that “applicant submits that memory is referenced consistently in the specification.” Examiner respectively disagrees.
As indicated by the specification in par. 68, the “the network device 300 may further include a programmable logic device (for example, an Input/Output Field Programmable Gate Array (IOFPGA) 310) which receives and utilizes the input clock signal Clk.sub.IN11 and the input synchronization signal Sync.sub.IN to synchronize the plurality of components with a reference timer 328”.
And the memory in par. 58, 59, “the second processor 224 may be configured to execute one or more instructions stored in the second memory 226 for performing one or more time/clock synchronization operations” and par. 115, “The chipset 706 can further be configured to provide an interface to a computer-readable storage medium such as a read-only memory (“ROM”) 710 or non-volatile RAM (“NVRAM”) for storing basic routines that can help with various tasks such as, but not limited to, starting up the device 700 and/or transferring information between the various components and devices”, the memory storing the instruction or routine and the processing accessing the memory to execute the instruction and not the memory executing the instruction as indicated by the claims 1-9. Therefore, the rejection is maintained.
Claim Rejections - 35 USC § 112
Claims 1, 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “memory” in claims 1, 7 is used by the claim to mean “processing or executing,” while the accepted meaning is “storing instruction or logic for processing or executing.” The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SARDA (US 20230421345) in view of HU et al. (US 20140365835 as supported by provisional app. 61831281 filed on 06/05/2013).
Regarding claim 1, SARDA (US 20230421345) teaches a device, comprising:
a plurality of components (fig. 1, par. 35, SLAVE LINE CARD 101, MASTER LINE CARD 105, PHY implemented);
a processor (fig. 1, par. 35, MASTER TIMING CARD implemented);
a network interface controller configured to provide access to a network (fig. 1, par. 25, 35, implemented); and
a memory communicatively coupled to the processor, wherein the memory comprises a phase adjusting logic (fig. 1, par. 26, 35) that is configured to:
receive an input synchronization signal (par. 26, The master timing card 103 supplies a SYNC signal and system clock signal (SYSCLK) to the slave line card 101 generated using PLL 117 and dividers (not shown)… The master timing card 103 supplies the SYSCLK and SYNC signal to all of the master line cards 105 over backplane 119);
generate a plurality of output synchronization signals by applying a plurality of phase adjustments to the input synchronization signal (par. 26, 28, Each of the line cards 101 and 105 generate the SYNC signal by dividing the SYSCLK generated by PLL 121 in a divider… The distributed SYSCLK is supplied as a reference clock to the PLL 121 within each of the line cards and the line card PLLs generate a local SYSCLK and SYNC signal that is phase and frequency aligned with the distributed SYSCLK and SYNC signal); and
provide a corresponding output synchronization signal of the plurality of output synchronization signals to each of the plurality of components (fig. 1, par. 25, The SYNC output from the master timing card (TC) is the global SYNC used by all the line cards(LC) for their ToD rollover alignment).
However, SARDA does not teach determine a delay value associated with each of the plurality of components;
select a lowest delay value of the delay values as a reference delay value;
determine a delay skew associated with each of the plurality of components based on a difference between the delay value associated with the respective component and the reference delay value;
But, HU et al. (US 20140365835) in a similar or same field of endeavor teaches determine a delay value associated with each of the plurality of components (par. 41, 42, 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
select a lowest delay value of the delay values as a reference delay value (par. 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
determine a delay skew associated with each of the plurality of components based on a difference between the delay value associated with the respective component and the reference delay value (par. 33, 34, 35, 41, 42, 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
Thus, it would have been obvious to the person of ordinary skill in the art before the effectively filing date of the claimed invention to implement the system or method as taught by HU in the system of SARDA to synchronize the signals.
The motivation would have been to align the signals causes by skews.
Regarding claim 2, SARDA (US 20230421345) teaches the device of claim 1, wherein the input synchronization signal is a pulse-per-second signal (par. 26, In many network systems the SYNC signal is 1 pulse per second (1PPS)).
Regarding claim 3, SARDA (US 20230421345) teaches the device of claim 1, wherein each of the plurality of output synchronization signals is associated with a different phase adjustment of the plurality of phase adjustments (par. 26, 28, 33, 35, Each of the line cards 101 and 105 generate the SYNC signal by dividing the SYSCLK generated by PLL 121 in a divider (not shown in FIG. 1) to the desired frequency… The distributed SYSCLK is supplied as a reference clock to the PLL 121 within each of the line cards and the line card PLLs generate a local SYSCLK and SYNC signal that is phase and frequency aligned with the distributed SYSCLK and SYNC signal).
Regarding claim 4, SARDA (US 20230421345) teaches the device of claim 1, wherein to generate the plurality of output synchronization signals (par. 26, 28), the phase adjusting logic is further configured to:
receive an input setting indicative of a delay associated with each of the plurality of components (par. 31, 32, 33, 35, While open loop and zero delay options provide solutions, if the IO delay is measured and the adjustment is made to SYNC based on the IO delay, the error can be reduced to ±50 ps… The measured IO delay can include delay caused by input buffers, the PLL 511, divide logic 517, and other clock tree buffers on the line card…The fine adjustment is made by adjusting an offset to the phase and frequency detector (PFD) 901 on the feedback divider 905 of the PTP PLL 511 shown in FIG. 9 in more detail. The combination of the coarse adjustment and the fine adjustment substantially eliminates the measured IO delay associated with the SYNC_out signal (or applies any desired offset to the SYNC_out signal));
determine a delay skew associated with each component of the plurality of components based on the input setting (par. 31, 32, 33, 35, While open loop and zero delay options provide solutions, if the IO delay is measured and the adjustment is made to SYNC based on the IO delay, the error can be reduced to ±50 ps… The fine adjustment is made by adjusting an offset to the phase and frequency detector (PFD) 901 on the feedback divider 905 of the PTP PLL 511 shown in FIG. 9 in more detail. The combination of the coarse adjustment and the fine adjustment substantially eliminates the measured IO delay associated with the SYNC_out signal (or applies any desired offset to the SYNC_out signal)); and
configure the plurality of phase adjustments based on the delay skew associated with each component of the plurality of components (par. 31, 32, 33, 35), wherein the plurality of output synchronization signals are generated in response to the configuration of the plurality of phase adjustments (par. 31, 32, 33, 35, While open loop and zero delay options provide solutions, if the IO delay is measured and the adjustment is made to SYNC based on the IO delay, the error can be reduced to ±50 ps… The fine adjustment is made by adjusting an offset to the phase and frequency detector (PFD) 901 on the feedback divider 905 of the PTP PLL 511 shown in FIG. 9 in more detail. The combination of the coarse adjustment and the fine adjustment substantially eliminates the measured IO delay associated with the SYNC_out signal (or applies any desired offset to the SYNC_out signal)).
Regarding claim 5, SARDA (US 20230421345) teaches the device of claim 4, wherein the delay comprises at least one of a trace propagation delay, a package delay, a buffer delay, or a flip-flop delay (par. 31, 32, 33, 35, The measured IO delay can include delay caused by input buffers, the PLL 511, divide logic 517, and other clock tree buffers on the line card).
Regarding claim 6, SARDA (US 20230421345) teaches the device of claim 4, wherein the plurality of phase adjustments are reconfigurable to accommodate one or more delay changes associated with one or more of the plurality of components (par. 31, 32, 33, 35, While open loop and zero delay options provide solutions, if the IO delay is measured and the adjustment is made to SYNC based on the IO delay, the error can be reduced to ±50 ps… The fine adjustment is made by adjusting an offset to the phase and frequency detector (PFD) 901 on the feedback divider 905 of the PTP PLL 511 shown in FIG. 9 in more detail. The combination of the coarse adjustment and the fine adjustment substantially eliminates the measured IO delay associated with the SYNC_out signal (or applies any desired offset to the SYNC_out signal)).
Regarding claim 7, SARDA (US 20230421345) teaches the device of claim 1, wherein the memory further comprises a reference timer configured to provide a reference time (par. 34, 35, The time stamp logic functions as a time to digital converter and converts the transitions of the SYNC_FB signal and the input SYNC signal to digital values based on an available timing reference… SYSCLK 515 as the reference clock signal).
Regarding claim 8, SARDA (US 20230421345) teaches the device of claim 7, wherein at least one of the plurality of components is configured to synchronize with the reference timer based on the corresponding output synchronization signal (par. 28, 34, The distributed SYSCLK is supplied as a reference clock to the PLL 121 within each of the line cards and the line card PLLs generate a local SYSCLK and SYNC signal that is phase and frequency aligned with the distributed SYSCLK and SYNC signal…The time stamp logic functions as a time to digital converter and converts the transitions of the SYNC_FB signal and the input SYNC signal to digital values based on an available timing reference. Difference logic 605 receives the two time stamps and determines the difference between the time stamps of SYNC_FB 503 and the currently valid SYNC signal 507. That difference 611 represents the input/output (IO) delay.).
Regarding claim 9, SARDA (US 20230421345) teaches the device of claim 1, wherein the plurality of output synchronization signals are phase aligned with each other (Par. 25, 30, maintain the ToD counters across different line cards in alignment over process, voltage, and temperature (PVT) variations so that all data_out 109 with their time stamps are aligned with each other and the incoming network time supplied on data_in 116…A mismatch exists in SYNC signal delivery due to PVT differences between the line cards including the slave line card and the master line cards. That mismatch impacts the accuracy of the timestamps in every Master LC and impacts the Continuous Time Error (CTE) budget of 5 ns for a Class D network box).
Regarding claim 10, SARDA (US 20230421345) teaches the device of claim 1, wherein the plurality of output synchronization signals are phase aligned with each other with a margin of error of less than or equal to a preset value (par. 30, 31, A mismatch exists in SYNC signal delivery due to PVT differences between the line cards including the slave line card and the master line cards. That mismatch impacts the accuracy of the timestamps in every Master LC and impacts the Continuous Time Error (CTE) budget of 5 ns for a Class D network box).
Regarding claim 11, SARDA (US 20230421345) teaches the device of claim 10, wherein the preset value corresponds to a maximum timing error associated with one or more functional applications of the device (par. 30, 31, A mismatch exists in SYNC signal delivery due to PVT differences between the line cards including the slave line card and the master line cards. That mismatch impacts the accuracy of the timestamps in every Master LC and impacts the Continuous Time Error (CTE) budget of 5 ns for a Class D network box…While open loop and zero delay options provide solutions, if the IO delay is measured and the adjustment is made to SYNC based on the IO delay, the error can be reduced to ±50 ps).
Regarding claim 12, SARDA (US 20230421345) teaches the device of claim 1, wherein the plurality of components comprise at least one communication port (par. 27, Synchronous Ethernet (SyncE) packet stream to the slave line card 101… an upstream PHY and the downstream pHY (e.g. PHY 123 in FIG. 1)).
Regarding claim 13, SARDA (US 20230421345) teaches a device, comprising:
a plurality of components (fig. 1, par. 25, 35, SLAVE LINE CARD 101, MASTER LINE CARD 105, PHY implemented);
a processor (fig. 1, par. 25, 35, MASTER TIMING CARD implemented);
a network interface controller configured to provide access to a network (fig. 1, par. 25, 35, implemented);
a memory communicatively coupled to the processor (fig. 1, par. 26, 35); and
a phase adjusting logic (fig. 1, par. 26, 35) is configured to:
receive an input clock signal and an input synchronization signal (par. 26, The master timing card 103 supplies a SYNC signal and system clock signal (SYSCLK) to the slave line card 101 generated using PLL 117 and dividers (not shown)… The master timing card 103 supplies the SYSCLK and SYNC signal to all of the master line cards 105 over backplane 119);
modify the input clock signal based on a delay skew associated with each of the plurality of components to obtain a plurality of output clock signals (fig. 4A, par. 30, 31, The Δt boxes shown in FIG. 4A represent the adjustments made to account for the delay in the SYNC and SYSCLK signals supplied from the master timing card 401…At D, input delay adjustments in the line card realign the SYSCLK edges back to the original alignment reference line 421 but do not realign SYSCLK and SYNC);
generate a plurality of output synchronization signals based on the input synchronization signal and the plurality of output clock signals (fig. 4A, par. 30, 31, 33, The Δt boxes shown in FIG. 4A represent the adjustments made to account for the delay in the SYNC and SYSCLK signals supplied from the master timing card 401…At D, input delay adjustments in the line card realign the SYSCLK edges back to the original alignment reference line 421 but do not realign SYSCLK and SYNC…Referring now to E of FIGS. 4A and 4B, if the misalignment is left without correction (open loop), the misalignment can range between 10.5 ns around the alignment reference line as shown at 425. Alternatively, a zero delay mode with respect to the SYSCLK can achieve±100 ps as shown at 427…The SYNC signal 507 is received at buffer 509 and is used, along with SYSCLK 515, to adjust the PLL 511 to ensure the SYNC_OUT and local SYSCLK 521 generated in the line card is phase and frequency aligned with the input SYNC and SYSCLK from the master timing card); and
provide the plurality of output synchronization signals to the plurality of components (fig. 1, par. 25, The SYNC output from the master timing card (TC) is the global SYNC used by all the line cards(LC) for their ToD rollover alignment).
However, SARDA does not teach determine a delay value associated with each of the plurality of components;
select a lowest delay value of the delay values as a reference delay value;
determine a delay skew associated with each of the plurality of components based on a difference between the delay value associated with the respective component and the reference delay value;
But, HU et al. (US 20140365835) in a similar or same field of endeavor teaches determine a delay value associated with each of the plurality of components (par. 41, 42, 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
select a lowest delay value of the delay values as a reference delay value (par. 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
determine a delay skew associated with each of the plurality of components based on a difference between the delay value associated with the respective component and the reference delay value (par. 33, 34, 35, 41, 42, 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
Thus, it would have been obvious to the person of ordinary skill in the art before the effectively filing date of the claimed invention to implement the system or method as taught by HU in the system of SARDA to synchronize the signals.
The motivation would have been to align the signals causes by skews.
Regarding claim 14, SARDA (US 20230421345) teaches the device of claim 13, wherein the plurality of output clock signals are associated with a plurality of phase adjustments (par. 26, 28, 33, 35, Each of the line cards 101 and 105 generate the SYNC signal by dividing the SYSCLK generated by PLL 121 in a divider (not shown in FIG. 1) to the desired frequency… The distributed SYSCLK is supplied as a reference clock to the PLL 121 within each of the line cards and the line card PLLs generate a local SYSCLK and SYNC signal that is phase and frequency aligned with the distributed SYSCLK and SYNC signal).
Regarding claim 15, SARDA (US 20230421345) teaches the device of claim 14, wherein to generate the plurality of output synchronization signals, the phase adjusting logic is further configured to apply the plurality of phase adjustments associated with the plurality of output clock signals to the input synchronization signal (par. 26, Each of the line cards 101 and 105 generate the SYNC signal by dividing the SYSCLK generated by PLL 121 in a divider).
Regarding claim 16, SARDA (US 20230421345) teaches the device of claim 15, wherein each of the plurality of output synchronization signals is a mirror of the input synchronization signal with a phase shift associated with an output clock signal of the plurality of output clock signals (fig. 1, par. 26, 28, Each of the line cards 101 and 105 generate the SYNC signal by dividing the SYSCLK generated by PLL 121 in a divider…The distributed SYSCLK is supplied as a reference clock to the PLL 121 within each of the line cards and the line card PLLs generate a local SYSCLK and SYNC signal that is phase and frequency aligned with the distributed SYSCLK and SYNC signal).
Regarding claim 17, SARDA (US 20230421345) teaches the device of claim 13, further comprising: one of a phase locked loop (PLL) or a mixed-mode clock manager (MMCM) (fig. 1, par. 25, PLL coupled with IO BUFFERS); and a plurality of buffers coupled to the one of the phase locked loop (PLL) or the mixed-mode clock manager (MMCM) (fig. 1, par. 25, PLL coupled with IO BUFFERS).
Regarding claim 18, SARDA (US 20230421345) teaches the device of claim 17, wherein the phase adjusting logic is implemented based on the plurality of buffers and one of the PLL or the MMCM (par. 32, 33, The SYNC_FB signal is time stamped and that time stamp is compared to the current valid SYNC time stamp for the SYNC input signal 507 received on input buffer 509. The measured IO delay can include delay caused by input buffers, the PLL 511, divide logic 517, and other clock tree buffers on the line card…The SYNC signal 507 is received at buffer 509 and is used, along with SYSCLK 515, to adjust the PLL 511 to ensure the SYNC_OUT and local SYSCLK 521 generated in the line card is phase and frequency aligned with the input SYNC and SYSCLK from the master timing card).
Regarding claim 19, SARDA (US 20230421345) teaches a method of time synchronization, comprising:
receiving an input synchronization signal (par. 26, The master timing card 103 supplies a SYNC signal and system clock signal (SYSCLK) to the slave line card 101 generated using PLL 117 and dividers (not shown)… The master timing card 103 supplies the SYSCLK and SYNC signal to all of the master line cards 105 over backplane 119);
generating a plurality of output synchronization signals by applying a plurality of phase adjustments on the input synchronization signal (par. 26, 28, Each of the line cards 101 and 105 generate the SYNC signal by dividing the SYSCLK generated by PLL 121 in a divider… The distributed SYSCLK is supplied as a reference clock to the PLL 121 within each of the line cards and the line card PLLs generate a local SYSCLK and SYNC signal that is phase and frequency aligned with the distributed SYSCLK and SYNC signal); and
synchronizing a plurality of components in a device with a reference timer based on the plurality of output synchronization signals (par. 28, 34, The distributed SYSCLK is supplied as a reference clock to the PLL 121 within each of the line cards and the line card PLLs generate a local SYSCLK and SYNC signal that is phase and frequency aligned with the distributed SYSCLK and SYNC signal…The time stamp logic functions as a time to digital converter and converts the transitions of the SYNC_FB signal and the input SYNC signal to digital values based on an available timing reference. Difference logic 605 receives the two time stamps and determines the difference between the time stamps of SYNC_FB 503 and the currently valid SYNC signal 507. That difference 611 represents the input/output (IO) delay.).
However, SARDA does not teach determine a delay value associated with each of the plurality of components;
select a lowest delay value of the delay values as a reference delay value;
determine a delay skew associated with each of the plurality of components based on a difference between the delay value associated with the respective component and the reference delay value;
But, HU et al. (US 20140365835) in a similar or same field of endeavor teaches determine a delay value associated with each of the plurality of components (par. 41, 42, 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
select a lowest delay value of the delay values as a reference delay value (par. 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
determine a delay skew associated with each of the plurality of components based on a difference between the delay value associated with the respective component and the reference delay value (par. 33, 34, 35, 41, 42, 54, Look for the earliest lane (i.e., the one with lowest skew), and then as reference to calculate the relative delay for the other lanes);
Thus, it would have been obvious to the person of ordinary skill in the art before the effectively filing date of the claimed invention to implement the system or method as taught by HU in the system of SARDA to synchronize the signals.
The motivation would have been to align the signals causes by skews.
Regarding claim 20, SARDA (US 20230421345) teaches the method of claim 19, further comprising reconfiguring one or more of the plurality of phase adjustments based one or more delay changes associated with one or more of the plurality of components (par. 31, 32, 33, 35, While open loop and zero delay options provide solutions, if the IO delay is measured and the adjustment is made to SYNC based on the IO delay, the error can be reduced to ±50 ps… The fine adjustment is made by adjusting an offset to the phase and frequency detector (PFD) 901 on the feedback divider 905 of the PTP PLL 511 shown in FIG. 9 in more detail. The combination of the coarse adjustment and the fine adjustment substantially eliminates the measured IO delay associated with the SYNC_out signal (or applies any desired offset to the SYNC_out signal)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
BAL et al. (US 20190223128) teaches the slave (receiving) clock generators 106b-106n are generally configured to phase lock the locally generated reference clock to the incoming synchronization signal SYNC from the master clock 106a (par. 28).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THINH D TRAN whose telephone number is (571)270-3934. The examiner can normally be reached mon-fri 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FARUK HAMZA can be reached at 5712727969. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THINH D TRAN/for /Thinh Tran/, Patent Examiner of Art Unit 2466 10/14/2026
