DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner notes the preliminary amendment dated 8/9/24, which has been entered.
1. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement, dated 8/9/24, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
2. REJECTIONS NOT BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-25 of U.S. Patent No. 11989133. Although the claims at issue are not identical, they are not patentably distinct from each other. The Examiner notes, for example, claim 1 of the US Patent is directed to reading data with a flag indicating whether the entry of the first subset of the mapping is associated with a second subset of the mapping or is associated with a starting physical address of the set of physical addresses, whereas the claim 2 of the instant application is directed to writing data with a similar flag indicating whether the entry of the first subset of the mapping is associated with a second subset of the mapping or is associated with a starting physical address of the set of physical addresses. Thus, claim 2 of the instant application would be obvious in view of the claim 1 for the reasons set forth above. Further, claim 3-21 would be obvious in view of claims 2-25 for similar reasons as set forth above.
3. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 2-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 20190294376).
With respect to claim 2, the Park reference teaches a memory system, comprising:
one or more memory devices; (see fig. 4a, NVM 120) and
processing circuitry coupled with the one or more memory devices (see fig. 4a, controller 110) and configured to cause the memory system to:
receive a write command for a set of physical addresses that are consecutively indexed; (paragraph 50, where when received write data is sequential data, controller 110 may guarantee an order of writing of the sequential data. In the present disclosure, guaranteeing the order of writing of the sequential data means that the pieces of sequential data are written based on an order in which write commands corresponding to the sequential data are received. For example, when a second write command and second sequential data are received after a first write command and first sequential data are received, controller 110 may write the first sequential data in non-volatile memory 120 and then write the second sequential data in non-volatile memory 120; and paragraph 103, where mapping manager 13 may generate mapping data by allocating a physical address (e.g., PBN) to a logical address (e.g., LBN) of write data and may store the mapping data in mapping table 12. The write data may be programmed into memory cells corresponding to the physical address in non-volatile memory 120)
write data to the set of physical addresses in response to receiving the write command; (paragraph 103, where mapping manager 13 may generate mapping data by allocating a physical address (e.g., PBN) to a logical address (e.g., LBN) of write data and may store the mapping data in mapping table 12. The write data may be programmed into memory cells corresponding to the physical address in non-volatile memory 120) and
set, in response to the set of physical addresses being consecutively indexed, a flag in an entry of a first subset of a mapping that defines a relationship between logical block addresses and physical addresses, the flag indicating whether the entry of the first subset of the mapping is associated with a second subset of the mapping or is associated with a starting physical address of the set of physical addresses. (paragraph 55, where when the command CMD is a write command CMDW, at least one bit of the flag bits FBS may be a sequential write flag bit indicating whether write data corresponding to the write command CMDW is sequential data. For example, the sequential write flag bit may be set (e.g., a value of 1) to indicate that the write data corresponding to the write command CMDW is sequential data; and paragraph 103, where mapping manager 13 may generate mapping data by allocating a physical address (e.g., PBN) to a logical address (e.g., LBN) of write data and may store the mapping data in mapping table 12. The write data may be programmed into memory cells corresponding to the physical address in non-volatile memory 120)
With respect to claim 3, the Park reference teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: set the entry of the first subset of the mapping to indicate the starting physical address in response to the set of physical addresses being consecutively indexed. (paragraph 103, where mapping manager 13 may generate mapping data by allocating a physical address (e.g., PBN) to a logical address (e.g., LBN) of write data and may store the mapping data in mapping table 12. The write data may be programmed into memory cells corresponding to the physical address in non-volatile memory 120)
With respect to claim 4, the Park reference teaches the memory system of claim 3, wherein the processing circuitry is further configured to cause the memory system to: receive a read command comprising a logical block address; read, based at least in part on the logical block address, the entry of the first subset of the mapping; read the data starting at the starting physical address of the set of physical addresses in response to setting the flag to indicate that the entry is associated with the starting physical address and reading the entry of the first subset of the mapping; and transmit the data based at least in part on reading the data. (paragraph 55, where address AD indicates a starting point to be written or read and may be a logical address. The data size DS may include data size information of read data or write data; and paragraph 67, where Mapping table 12 may include mapping data including a physical address corresponding to a logical address. For example, the logical address may include a logical block number LBN, and the physical address may include a physical block number PBN and a physical page number PPN)
With respect to claim 5, the Park reference teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: add, in response to writing the data to the set of physical addresses, a first set of entries to a first change log associated with updating entries of the mapping and a second set of entries to a second change log associated with updating entries of the mapping; and set a second flag in the first change log or the second change log, or both, that indicates whether physical addresses associated with the first set of entries of the first change log are consecutive with physical addresses associated with the second set of entries of the second change log. (paragraph 39, where journal data of a file system 220 may be sequential data. Host 200 may store or read data generated by executing an application 210 or data required for executing application 210 in or from storage device 100, based on file system 220. File system 220 allocates an address at which user data is to be stored, in response to a command from application 210. File system 220 may be updated by changes occurring while storing a file in file system 220, and the journal data may include information on details to be updated when file system 220 is updated; and paragraph 92, where controller 110 may determine whether a sequential write flag is set in the write command, based on the sequential write flag bit OSFB of the write command (operation S320). When the sequential write flag bit OSFB has a first value, for example, ‘1’, controller 110 may determine that the sequential write flag is set, and when the sequential write flag bit OSFB has a second value, for example, ‘0’, controller 110 may determine that the sequential write flag is not set)
With respect to claim 6, the Park reference teaches the memory system of claim 2, wherein the processing circuitry is further configured to cause the memory system to: receive a second write command for a second set of physical addresses, wherein one or more physical addresses of the second set are non-consecutive with other physical addresses of the second set; write second data to the second set of physical addresses in response to receiving the second write command; and set a second flag in a second entry of the first subset of the mapping in response to the second set of physical addresses being non-consecutive, the flag indicating that the second entry of the first subset of the mapping is associated with the second subset of the mapping. (paragraph 92, where controller 110 may determine whether a sequential write flag is set in the write command, based on the sequential write flag bit OSFB of the write command (operation S320). When the sequential write flag bit OSFB has a first value, for example, ‘1’, controller 110 may determine that the sequential write flag is set, and when the sequential write flag bit OSFB has a second value, for example, ‘0’, controller 110 may determine that the sequential write flag is not set; and paragraph 94, where when the sequential write flag bit OSFB is ‘1’, controller 110 may determine the write data to be sequential data)
With respect to claim 7, the Park reference teaches the memory system of claim 6, wherein the processing circuitry is further configured to cause the memory system to: set the second entry of the first subset of the mapping to indicate a location of an entry of the second subset of the mapping in response to the second set of physical addresses being non-consecutive. (paragraph 92, where controller 110 may determine whether a sequential write flag is set in the write command, based on the sequential write flag bit OSFB of the write command (operation S320). When the sequential write flag bit OSFB has a first value, for example, ‘1’, controller 110 may determine that the sequential write flag is set, and when the sequential write flag bit OSFB has a second value, for example, ‘0’, controller 110 may determine that the sequential write flag is not set; and paragraph 94, where when the sequential write flag bit OSFB is ‘1’, controller 110 may determine the write data to be sequential data. When the sequential write flag bit OSFB is ‘0’, controller 110 may determine the write data to be non-sequential data)
With respect to claim 8, the Park reference teaches the memory system of claim 7, wherein the processing circuitry is further configured to cause the memory system to: set a third flag that identifies the one or more non-consecutive physical addresses. (paragraph 94, where when the sequential write flag bit OSFB is ‘1’, controller 110 may determine the write data to be sequential data. When the sequential write flag bit OSFB is ‘0’, controller 110 may determine the write data to be non-sequential data)
With respect to claim 9, the Park reference teaches the memory system of claim 2, wherein the mapping comprises the first subset, the second subset, and a third subset, and wherein a first entry of the third subset is identified using a logical block address received in a read command, the entry of the first subset is identified using the first entry of the third subset, a second entry of the second subset is identified using the entry of the first subset, and a physical address of the memory device is identified using the second entry of the second subset. (paragraph 55, where address AD indicates a starting point to be written or read and may be a logical address. The data size DS may include data size information of read data or write data; and paragraph 67, where Mapping table 12 may include mapping data including a physical address corresponding to a logical address. For example, the logical address may include a logical block number LBN, and the physical address may include a physical block number PBN and a physical page number PPN. However)
Claims 10-17 are the non-transitory computer-readable medium implementation of claims 1-9, and rejected under a similar rationale as shown in the rejections above.
Claims 18-21 are the method implementation of claims 1-9, and rejected under a similar rationale as shown in the rejections above.
4. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Cho (US 20200057725), which teaches a data storage device may include: a nonvolatile memory device including a first memory block and a second memory block; and a processor configured to generate an invalid entry including first physical block addresses of the first memory block, corresponding to sequential logical block addresses, and generate a valid entry including second physical block addresses of the second memory block, in which data for the sequential logical block addresses are to be stored, collectively change, based on the invalid entry, bits corresponding to the first physical block addresses in a first valid page bitmap table of the first memory block to a first value, and collectively change, based on the valid entry, bits corresponding to the second physical block addresses in a second valid page bitmap table of the second memory block to a second value; and
Lin (US 20190227929), which teaches a data storage device that includes a memory device and a memory controller. The memory controller is coupled to the memory device and configured to access the memory device and establish a physical to logical address mapping table and a logical address section table. The logical address section table records statuses of a plurality of logical address sections. Each status is utilized to indicate whether the physical to logical address mapping table records any logical address that belongs to the corresponding logical address section. The logical address section table includes a plurality of section bits in a plurality of dimensions. When the memory controller receives a write command to write data of a first predetermined logical address, the memory controller determines the section bit of each dimension corresponding to the first predetermined logical address, and accordingly sets a corresponding digital value for each section bit.
5. CLOSING COMMENTS
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137