NON-FINAL REJECTION
DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 13, 2025 has been entered.
Response to Amendment
The Amendment filed November 13, 2025 has been entered. Claims 1-20 remain pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,983,434. Although the claims at issue are not identical, they are not patentably distinct from each other as shown below.
Regarding claim 1, U.S. Patent No. 11,983,434 discloses:
A device, comprising:
memory cells having a storage capacity (claim 1: local storage device having a storage capacity accessible via network storage services provided over the network interface);
a first interface to a host system (claim 1: a bus connector configured to be connected to a computer bus external to the storage product as manufactured…provide, through the bus connector, the first messages to a local host system);
a second interface to a computer network (claim 1: a network interface operable on a computer network to receive storage access messages from a remote host system) to provide storage services using the storage capacity (claim 1: local storage device having a storage capacity accessible via network storage services provided over the network interface); and
a computational storage processor (claim 1: a computational storage processor);
wherein the device is configured to provide at least a first portion of storage access messages received in the second interface to the computational storage processor (claim 1: separate the storage access messages into first messages, second messages, and third messages; claim 1: provide the second messages to the computational storage processor) and a second portion of the storage access messages to the host system in providing the storage services (claim 1: provide, through the bus connector, the first messages to a local host system, external to the storage product and connected to the computer bus), wherein the storage access messages are received in the second interface from another device via the computer network (claim 1: a network interface operable on a computer network to receive storage access messages from a remote host system).
Regarding claim 2, U.S. Patent No. 11,983,434 further discloses:
The device of claim 1, wherein the first interface is configured to operate on a computer bus external to the device manufactured as a storage product (claim 1: a bus connector configured to be connected to a computer bus external to the storage product as manufactured).
Regarding claim 3, U.S. Patent No. 11,983,434 discloses:
The device of claim 2, wherein the second interface is configured as a network interface of the storage product to operate on the computer network (claim 1: a network interface operable on a computer network to receive storage access messages from a remote host system).
Regarding claim 4, U.S. Patent No. 11,983,434 discloses:
The device of claim 3, further comprising:
a logic circuit (claim 2: a processing device) configured to separate the first portion of the storage access messages and the second portion of the storage access messages (claim 1: wherein the storage product is configured to: separate the storage access messages into first messages, second messages, and third messages).
Regarding claim 5, U.S. Patent No. 11,983,434 discloses:
The device of claim 4, wherein the storage services are provided via executing commands in:
a third portion of the storage access messages that does not go through the host system and does not go through the computational storage processor (claim 1: the third messages from the network interface without going through the local host system and the computational storage processor);
first messages from the computational storage processor, responsive to the first portion of the storage access messages (claim 1: provide the second messages to the computational storage processor to generate fifth messages); and
second messages from the host system, responsive to the second portion of the storage access messages (claim 1: the first messages to a local host system, external to the storage product and connected to the computer bus, to generate fourth messages).
Regarding claim 6, U.S. Patent No. 11,983,434 discloses:
The device of claim 5, wherein the logic circuit is further configured to reconstruct the storage access messages from incoming packets received at the network interface from the computer network (claim 2: a processing device coupled to the network interface to generate the storage access messages from incoming packets received at the network interface from the computer network).
Regarding claim 7, U.S. Patent No. 11,983,434 discloses:
The device of claim 6, wherein the logic circuit includes a processor separate from the computational storage processor (claim 3: the processing device is separate from the computational storage processor).
Regarding claim 8, U.S. Patent No. 11,983,434 discloses:
The device of claim 6, wherein the logic circuit is configured to set up, based on the second messages, computation instructions (claim 6: the local host system is configured to set up computation instructions via processing the first messages); and
the computational storage processor is configured via the computation instructions to process the first portion of the storage access messages (claim 6: the computational storage processor is configured via the computation instructions to generate the fifth messages from processing of the second messages).
Regarding claim 9, U.S. Patent No. 11,983,434 discloses:
The device of claim 8, wherein the storage product is configured in a form of an expansion card connected to the computer bus via insertion into an expansion slot on a mother board (claim 9: wherein the storage product is configured in a form of an expansion card connected to the computer bus via insertion into an expansion slot on a mother board).
Regarding claim 10, U.S. Patent No. 11,983,434 discloses:
The device of claim 8, further comprising:
a casing or housing configured to enclose the storage product as manufactured (claim 10: a casing or housing enclosing the network interface, the local storage device, the computational storage processor, and the processing device).
Claims 11-20 of the instant application recite limitations that are substantially similar to the limitation of claim 1-10 rejected above. Additionally, claims 11-20 of the instant application correspond to various limitations as recited in claims 1-20 of the US Patent No. No. 11,983,434. Therefore, claims 11-20 of the instant application and are rejected on the ground of nonstatutory obviousness-type double patenting on the same rationale as claims 1-10 above.
In the event that any claim is not completely anticipated by at least one claim of a patent
above, the claims would still be rejected on the grounds of obvious nonstatutory double
patenting in further view of the prior art below that teaches or makes obvious that missing part,
and one of ordinary skill in the art could have incorporated such teachings prior to the effective
filings date of the claimed invention.
Please note that MPEP § 804 states:
“A complete response to a nonstatutory double patenting (NSDP) rejection is
either a reply by applicant showing that the claims subject to the rejection are patentably
distinct from the reference claims or the filing of a terminal disclaimer in accordance with
37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP §
1490 for a discussion of terminal disclaimers). Such a response is required even when
the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer,
or filing a showing that the claims subject to the rejection are patentably distinct from the
reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements
as to form not necessary for further consideration of the claims may be held in abeyance
until allowable subject matter is indicated. Replies with an omission should be treated as
provided in MPEP § 714.03.”
In accordance with MPEP § 804 and §714.03 the examiner will hold any
response/amendments to this office action as NON-COMPLIANT without any additional
extensions of time that do not contain:
a. an approved terminal disclaimer, or
b. a complete and concise explanation of how the inventions are patentably distinct from one another.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-4, 11, 12, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kachare et al. (US 2022/0083257) and Strong et al. (US 2015/0199298).
Regarding claim 1, Kachare et al. disclose:
A device, comprising:
memory cells having a storage capacity (FIG. 4 Memory 228, 224, 204; [0024] SSDs which may include solid state media such as not-AND (NAND) flash memory; [0026] SSDs which may include solid state media such as not-AND (NAND) flash memory; [0028] memory 228 such as DRAM, SRAM, nonvolatile memory, and/or the like; One of ordinary skill in the art before the effective filing date of the claimed invention would understand that memory of the storage device has a storage capacity and is composed memory cells);
a first interface to a host system (FIG. 4 Host Interface 406);
a second interface to a computer network to provide storage services using the storage capacity (FIG. 4 NIC 460; [0054] the NIC 460 may be configured to use some or all of the compute resources 426 of the attachable compute module 420 to function as a computational NIC, which may receive offloaded compute tasks from the host 418 and/or any other devices connected to the one or more network connectors 462); and
a computational storage processor (FIG. 5 Attachable Compute Module 420);
wherein the device is configured to provide at least a first portion of storage access messages received in the second interface to the computational storage processor (FIG. 4 468; [0052] The NIC 460 may be configured to access the compute resources 426 of the attachable compute module 420 directly through an interface 468, which may also be implemented using any suitable interconnect and/or network interface and/or protocol including any of those mentioned above) and a second portion of the storage access messages to the host system in providing the storage services (FIG. 4 470; [0053] The NIC 460 may be configured to access the host interface 406 directly through an interface 470, which may also be implemented using any suitable interconnect and/or network interface and/or protocol including any of those mentioned above), wherein the storage access messages are received in the second interface from another device via the computer network (FIG. 4 NIC 460; [0054] the NIC 460 may be configured to use some or all of the compute resources 426 of the attachable compute module 420 to function as a computational NIC, which may receive offloaded compute tasks from the host 418 and/or any other devices connected to the one or more network connectors 462; It is noted that “another device” does not limit the structure of the claimed “device” and does not serve as a patentable distinction).
Kachare et al. disclose the limitations of claim 1. Under the broadest reasonable interpretation of “storage access messages,” Kachare’s teachings of a communication to access resources on a storage device are storage access messages. However, in the alternative, Strong et al. disclose:
storage access messages ([0019] a message (e.g., a write request) includes a command to access a storage device)
Kachare et al. and Strong et al. are analogous art because they teach storage systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kachare et al. and Strong et al. before him/her, to modify the teachings of Kachare et al. with the Strong et al. teachings of messages because such a modification would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 I.A.) It is a well-known that messages may be write requests. Sending a message in the form of a write request would have yielded the predictable result of notifying the device of a command to write data to the device.
Regarding claim 2, Kachare et al. further disclose:
The device of claim 1, wherein the first interface is configured to operate on a computer bus external to the device manufactured as a storage product ([0030] The host interface 206 may connect the storage device 200 to a host 218 through a connection 216 using any storage interface and/or protocol such as PCIe, NVMe, NVMe-oF, Ethernet, InfiniBand, Fibre Channel, and/or the like).
Regarding claim 3, Kachare et al. further disclose:
The device of claim 2, wherein the second interface is configured as a network interface of the storage product to operate on the computer network (FIG. 4 NIC 460; [0054] the NIC 460 may be configured to use some or all of the compute resources 426 of the attachable compute module 420 to function as a computational NIC, which may receive offloaded compute tasks from the host 418 and/or any other devices connected to the one or more network connectors 462).
Regarding claim 4, Kachare et al. further disclose:
The device of claim 3, further comprising:
a logic circuit configured to separate the first portion of the storage access messages and the second portion of the storage access messages (FIG. 4 NIC 460 separates messages through 468 and 470).
The limitations of claims 11, 12, 16, and 17 correspond the limitations of claims 1-3. Therefore, claims 11, 12, 16, and 17 are rejected under the same reasoning as the rejection of claims 1-3.
Claims 5, 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kachare et al. and Strong et al. as applied to claim 4 above, and further in view of Shin et al. (US 2012/0110277).
Regarding claim 5, Kachare et al. further disclose:
The device of claim 4, wherein the storage services are provided via executing commands ([0019] A storage device controller may be configured to communicate with the attachable compute module through one or more command extensions of a storage protocol, by utilizing a proprietary communication protocol, and/or the like. A method may include transferring control of one or more functions, such as data processing functions, of the storage device to an attachable compute module. In some embodiments, an attachable compute module may include a control and/or status data structure configured to be read and/or written by a storage device controller) in:
a third portion of the storage access messages that does not go through the host system and does not go through the computational storage processor (FIG. 4 466);
Kachare et al. and Strong et al. do not appear to explicitly teach “first messages from the computational storage processor, responsive to the first portion of the storage access messages; and second messages from the host system, responsive to the second portion of the storage access messages,” However, Shin et al. disclose:
first messages from the computational storage processor, responsive to the first portion of the storage access messages (FIG. 5 Write Status 533; Read Data and Status 533/534 are responses to Read 530/531 and Write commands 532; [0024] The commands and responses to the commands are generally packaged within communications messages that include headers which identify the sending and receiving entities as well as the command or response type, length of included data, and other information; One of ordinary skill in the art before the effective filing date of the claimed invention would understand than response messages are sent in response to storage access messages); and
second messages from the host system, responsive to the second portion of the storage access messages (FIG. 5 Write Status 533; Read Data and Status 533/534 are responses to Read 530/531 and Write commands 532; [0024] The commands and responses to the commands are generally packaged within communications messages that include headers which identify the sending and receiving entities as well as the command or response type, length of included data, and other information; One of ordinary skill in the art before the effective filing date of the claimed invention would understand than response messages are sent from devices in response to storage access messages).
Kachare et al., Strong et al., and Shin et al. are analogous art because they teach storage systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kachare et al., Strong et al., and Shin et al. before him/her, to modify the combined teachings of Kachare et al. and Strong et al. with the Shin et al. teachings of storage command responses because sending responses to storage commands would have amounted to little more than combining “familiar elements according to known methods” and would have been obvious because it would have done “no more than yield predictable results.” (MPEP 2143 IA.) Sending responses to storage commands is a known technique for providing read data and status updates. Therefore, implementing response messages would have resulted in the predictable result of providing read data and status updates.
The limitations of claims 14 and 19 correspond the limitations of claim 5. Therefore, claims 14 and 19 are rejected under the same reasoning as the rejection of claim 5.
Allowable Subject Matter
Claims 6-10, 13, 15, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the double patenting rejection of the claims is overcome.
Response to Arguments
Applicant's arguments filed November 13, 2025 have been fully considered but they are not persuasive.
Regarding applicant’s argument (Remarks page 3) that Kachare does not teach “storage access messages,” the examiner disagrees. Based on the broadest reasonable interpretation of a “message,” a communication to access resources on a storage device are storage access messages. However, in the interest of compact prosecution, a new ground(s) of rejection is made in view of Strong.
Regarding applicant’s argument (Remarks page 3) that Kachare does not teach “the device is configured to provide…a second portion of the storage access messages to the host system in providing the storage services,” the examiner disagrees. The host interface connects the host to the NIC. As shown in Figure 4, messages sent between the host the NIC flow through the host interface
Regarding applicant’s argument (Remarks page 4) that Kachare does not teach “wherein the storage access messages are received in the second interface from another device via the computer network,” the examiner disagrees. It is noted that “another device” does not limit the structure of the claimed “device” and does not serve as a patentable distinction. However, Kachare discloses at paragraph [0054] that the “other devices” communicate with the NIC 460 via the network connector.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137