Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 08/13/2026 has been entered. Claims 1 – 25 ( Group I ) have been elected without traverse, claim 2 – 9 , 14 – 15 ( Species A ) have been elected with traverse. Claims 1 – 9, 14 – 15, 25 are pending in the application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 9, 14 – 15, 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee ( Pub. No. US 20220310577 A1 ), hereinafter Lee.
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Regarding Independent claim 1 (Original), Lee teaches A package comprising:
a package substrate ( Lee, FIG. 4B, 110, 120, 200, 300, 700, 350, 410; [0028], The interposer structure may include a first redistribution layer 110 … a second redistribution layer 120 … a bridge structure 200, a passive device 300, and conductive structures 350; [0104], electronic device 700; [0077], lower mold layer 410 ) comprising:
(i) an encapsulated portion ( Lee, FIG. 4B, the portion between 110 and 120 ) comprising:
a first interconnection portion block ( Lee, FIG. 4B, 200 );
a second interconnection portion block ( Lee, FIG. 4B, 700 ), wherein the second interconnection portion block ( Lee, FIG. 4B, 700 ) is a different (Lee, [0100], The electronic device 700 may be an active device. For example, the electronic device 700 may be a semiconductor chip. As an example, the electronic device 700 may be an input/output chip (I/O chip) or a power management chip; [0063], the bridge structure 200 may be used as an electrical connection path between the first and second semiconductor chips 610 and 620) type of interconnection portion block from the first interconnection portion block ( Lee, FIG. 4B, 200 );
a plurality of pillar interconnects ( Lee, FIG. 4B, 280, 780 ; [0061], First pillar patterns 280; [0101], third pillar patterns 780 ), wherein the plurality of pillar interconnects comprises:
a first ( Lee, FIG. 4B, 280 ) plurality of pillar interconnects coupled to the first ( Lee, FIG. 4B, 200 ) interconnection portion block; and
a second ( Lee, FIG. 4B, 780 ) plurality of pillar interconnects coupled to the second ( Lee, FIG. 4B, 700 ) interconnection portion block; and
an encapsulation layer ( Lee, FIG. 4B, 410; [0077], The lower mold layer 410 may be formed of or include at least one of insulating polymers (e.g., epoxy molding compound) ) at least partially encapsulating the first ( Lee, FIG. 4B, 200 ) interconnection portion block, the second ( Lee, FIG. 4B, 200 ) interconnection portion block, and the plurality of pillar interconnects ( Lee, FIG. 4B, 280, 780 );
(ii) a first metallization portion ( Lee, FIG. 4B, 120; [0048, second redistribution layer 120 ) coupled to a first surface of the encapsulated ( Lee, FIG. 4B, 410 ) portion;
and
(iii) a second metallization portion ( Lee, FIG. 4B, 110; [0043], first redistribution layer 110 ) coupled to a second surface of the encapsulated ( Lee, FIG. 4B, 410 ) portion; and
a first integrated device ( Lee, FIG. 4B, 610; [0052], first semiconductor chip 610 may be one of a logic chip, a buffer chip, and a system-on-chip (SOC) ) coupled to the package substrate ( Lee, FIG. 4B, 110, 120, 200, 300, 700, 350, 410 ) through a first plurality of solder interconnects ( Lee, FIG. 4B, 510; [0053], Each of the first bonding bumps 510 may include at least one of a solder ball, a solder pillar, and/or combinations thereof. The first bonding bumps 510 may be formed of or include at least one of soldering materials or copper ).
Regarding claim 2 (Original), Lee teaches the package as claimed in claim 1, on which this claim is dependent, Lee further teaches: comprising:
wherein the first interconnection portion block ( Lee, FIG. 4B, 200 ) includes a coreless substrate block, a cored substrate block, an embedded passive substrate ( Lee, FIG. 4B, 210; [0038], base substrate 210 ) block, a metallization portion block ( Lee, FIG. 4B, 260, 255; [0084], metal patterns 260; [0038], connection pads 255 ) or a die block ( Lee, FIG. 4B, 200 ) comprising through substrate vias ( Lee, FIG. 4B, [0084], penetration structures 270 ).
Regarding claim 3 (Original), Lee teaches the package as claimed in claim 1, on which this claim is dependent, Lee further teaches:
wherein the second interconnection portion block ( Lee, FIG. 4B, 700 ) includes a coreless substrate block, a cored substrate block ( Lee, [0100], The electronic device 700 may be an active device. For example, the electronic device 700 may be a semiconductor chip. As an example, the electronic device 700 may be an input/output chip (I/O chip) or a power management chip ), an embedded passive substrate block, a metallization portion block ( Lee, [0100], The conductive pads 715 may be formed of or include at least one of metallic materials (e.g., copper, nickel, gold, and/or aluminum) ) or a die block comprising through substrate vias ( Lee, FIG. 4B, 750; [0105], penetration vias 750 ).
Regarding claim 4 (Original), Lee teaches the package as claimed in claim 1, on which this claim is dependent, Lee further teaches:
wherein the first metallization portion ( Lee, FIG. 4B, 120 ) includes a first plurality of metallization interconnects comprising a first minimum width and a first minimum spacing ( Lee, [0045], The second redistribution patterns 123 may be spaced apart from each other and may be electrically disconnected from each other … The second conductive pattern 1233 may include a second via portion 1233V and a second wire portion 1233W …The second wire portion 1233W may have a width or length in the first direction that is larger than a width of the second via portion 1233V in the first direction ), and
wherein the second metallization portion ( Lee, FIG. 4B, 110 ) includes a second plurality of metallization interconnects comprising a second minimum width and a second minimum spacing ( Lee, [0031], The first redistribution patterns 113 may be laterally spaced apart from each other and may be electrically separated from each other … The first conductive pattern 1133 may include a first via portion 1133V and a first wire portion 1133W … The first wire portion 1133W may have a width in the first direction that is larger than a width of the first via portion 1133V in the first direction ).
Regarding claim 5 (Original), Lee teaches the package as claimed in claim 1, on which this claim is dependent, Lee further teaches:
wherein the first integrated device ( Lee, FIG. 4B, 610 ) is coupled to the first metallization portion ( Lee, FIG. 4B, 120 ) of the package substrate through the first plurality of solder interconnects ( Lee, FIG. 4B, 510 ).
Regarding claim 6 (Original), Lee teaches the package as claimed in claim 5, on which this claim is dependent, Lee further teaches:
wherein the first integrated device ( Lee, FIG. 4B, 610 ) includes a first core and a second core ( Lee, [0052], first semiconductor chip 610 may be one of a logic chip, a buffer chip, and a system-on-chip (SOC). In an embodiment, the first semiconductor chip 610 may be an application specific integrated circuit (ASIC) chip or an application processor (AP) chip. The ASIC chip may include an application specific integrated circuit. In another embodiment, the first semiconductor chip 610 may include a central processing unit (CPU) or a graphic processing unit (GPU) ),
wherein a first electrical path ( Lee, FIG. 4B, 280, 270; [0061], First pillar patterns 280; [0084], penetration structures 270 ) for a first signal to the first core of the first integrated device ( Lee, FIG. 4B, 610 ) comprises the first interconnection portion block ( Lee, FIG. 4B, 200 ), and
wherein a second electrical path ( Lee, FIG. 4B, 780, 750; [0101], third pillar patterns 780; [0105], penetration vias 750 ) for a second signal to the second core of the first integrated device ( Lee, FIG. 4B, 610 ) comprises the second interconnection portion block ( Lee, FIG. 4B, 700 ).
Regarding claim 7 (Original), Lee teaches the package as claimed in claim 5, on which this claim is dependent, Lee further teaches:
further comprising a second integrated device ( Lee, FIG. 4B, 620; [0055], second semiconductor chips 620 ) coupled to the first metallization portion ( Lee, FIG. 4B, 120 ) of the package substrate ( Lee, FIG. 4B, 110, 120, 200, 300, 700, 350, 410 ) through a second plurality of solder interconnects ( Lee, FIG. 4B, 520 ).
Regarding claim 8 (Original), Lee teaches the package as claimed in claim 7, on which this claim is dependent, Lee further teaches:
wherein a first electrical path ( Lee, FIG. 4B, 280, 270 ) for a first signal to the first integrated device ( Lee, FIG. 4B, 610 ) comprises the first interconnection portion block ( Lee, FIG. 4B, 200 ), and
wherein a second electrical path ( Lee, FIG. 4B, 780, 750 ) for a second signal to the second integrated device ( Lee, FIG. 4B, 620 ) comprises the second interconnection portion block ( Lee, FIG. 4B, 700; [0106], The electronic device 700 may be electrically connected to the first redistribution pattern 113 through the second solder patterns 570. The first or second semiconductor chips 610 or 620 may be electrically connected to the first redistribution pattern 113 through the second redistribution layer 120 and the penetration structures 270. ).
Regarding claim 9 (Original), Lee teaches the package as claimed in claim 7, on which this claim is dependent, Lee further teaches:
wherein a first electrical path ( Lee, FIG. 4B, 275, 270, 260, 255 ) for a first signal between the second metallization portion ( Lee, FIG. 4B, 110 ) and the first integrated device ( Lee, FIG. 4B, 610 ) comprises interconnects from the first interconnection portion block ( Lee, FIG. 4B, 200 ), a pillar interconnect from the first plurality of pillar interconnects ( Lee, FIG. 4B, 280 ), metallization interconnects from the first metallization portion ( Lee, FIG. 4B, 123 ), and a first solder interconnect from the first plurality of solder interconnects ( Lee, FIG. 4B, 510 ), and
wherein a second electrical path ( Lee, FIG. 4B, 725, 750, 715 ) for a second electrical signal between the second metallization portion ( Lee, FIG. 4B, 110 ) and the second integrated device ( Lee, FIG. 4B, 620 ) comprises interconnects from the second interconnection portion block ( Lee, FIG. 4B, 700 ), a pillar interconnect from the second plurality of pillar interconnects ( Lee, FIG. 4B, 780 ), other metallization interconnects from the first metallization portion ( Lee, FIG. 4B, 123 ), and a second solder interconnect from the second plurality of solder interconnects ( Lee, FIG. 4B, 520 ).
Regarding claim 14 (Original), Lee teaches the package as claimed in claim 1, on which this claim is dependent, Lee further teaches:
wherein the first interconnection portion block ( Lee, FIG. 4B, 200 ) includes a first number of metal layers ( Lee, FIG. 4B, 255, 250, 260, 275 ), and
wherein the second interconnection portion block ( Lee, FIG. 4B, 700 ) includes a second number of metal layers ( Lee, FIG. 4B, 715, 725 ) that is different than the first number of metal layers.
Regarding claim 15 (Original), Lee teaches the package as claimed in claim 1, on which this claim is dependent, Lee further teaches:
wherein a first electrical path ( Lee, FIG. 4B, 275, 270, 260, 255 ) for a first electrical signal between the second metallization portion ( Lee, FIG. 4B, 110 ) and the first integrated device ( Lee, FIG. 4B, 610 ) comprises interconnects from the first interconnection portion block ( Lee, FIG. 4B, 200 ), a pillar interconnect from the first plurality of pillar interconnects ( Lee, FIG. 4B, 280 ), metallization interconnects from the first metallization portion ( Lee, FIG. 4B, 123 ), and a first solder interconnect from the first plurality of solder interconnects ( Lee, FIG. 4B, 510 ), and
wherein a second electrical path ( Lee, FIG. 4B, 725, 750, 715 ) for a second electrical signal between the second metallization portion ( Lee, FIG. 4B, 110 ) and the first integrated device ( Lee, FIG. 4B, 610 ) comprises interconnects from the second interconnection portion block ( Lee, FIG. 4B, 700 ), a pillar interconnect from the second plurality of pillar interconnects ( Lee, FIG. 4B, 780 ), other metallization interconnects from the first metallization portion ( Lee, FIG. 4B, 123 ), and a second solder interconnect from the first plurality of solder interconnects ( Lee, FIG. 4B, 510 ).
Regarding claim 25 (Original), Lee teaches the package as claimed in claim 1, on which this claim is dependent, Lee further teaches:
wherein the package is implemented in a device is that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle ( Lee, FIG. 4B, 610, 620, 700; [0052], first semiconductor chip 610 may be one of a logic chip, a buffer chip, and a system-on-chip (SOC); [0055], the second semiconductor chips 620 may be a logic chip, and the others may be memory chips. The memory chip may include a high bandwidth memory (HBM) chip … second semiconductor chips 620 may be a controller chip which is configured to control memory chips … second semiconductor chips 620 may be a memory chip; [0100], The electronic device 700 may be an active device. For example, the electronic device 700 may be a semiconductor chip. As an example, the electronic device 700 may be an input/output chip (I/O chip) or a power management chip ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
