DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 04/25/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 07/16/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 19, the limitations cites “wherein the second entity is configured to generate a plurality of latch triggers based on the data strobe signal from the first entity and a plurality of preset delay times with respect to the first entity; generate a plurality of latched data by latching the data line connected to the first entity based on the plurality of latch triggers; and determine reception data based on the plurality of latched data”, it is unclear how the second entity generates a plurality of latch triggers based on the data strobe signal from the first entity when the first entity as cited in claim 17, also generates a plurality of latch triggers based on the plurality of delay times and a data strobe signal from second entity? The terms “a first and second entity” used in claim 19 are vague and are not clear as to the meaning of the technical features to which the terms refer. For the purpose of persecution, it will be treated as transmitter e.g., please see independent claims 1, 9 and Figure 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-12 & 16-20 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Ku et al (US7755402).
Regarding claim 1, Ku discloses an electronic apparatus(FIG 4; 400), comprising: a latch trigger generator configured to generate a plurality of latch triggers based on a data strobe signal and a plurality of delay times(FIG 4 & 6; 430 440 generating latch triggers 435 and 445 based on 212 and delay times 610 620) ; a data latch unit configured to latch a data line based on the plurality of latch triggers to generate a plurality of latched data(FIG 4; 450 460(unit), 450 using data line e.g., output of 410 and latching data values from 430 440 note 450 460 as unit outputting latched data values); and a processor configured to set the plurality of delay times and determine reception data based on the plurality of latched data (FIG 2; col 5, lines 15-19 and col 6 lines 17-25; discloses GPU 110 determining reception data based on the plurality of latched data e.g., latching data in response to an edge of a signal and so on).
Regarding claim 2, Ku discloses wherein the latch trigger generator generates the plurality of latch triggers at time points, corresponding to the plurality of delay times(FIG 6; 435 445 different time points corresponding to the plurality of delay times e.g., 610-620) , elapsed from a time point when the data strobe signal is changed from a low to a high level, or from a high to a low level(elapsed time from a time point e.g., 410 at 445 different from 435 high to low or low to high at 620), and wherein the data latch unit latches the data line at time points when the plurality of latch triggers are generated(FIG 2 & 6; col 3, lines 37- lines 49 & col 29-48 discloses timing relation among read data 211, 110 latches data on data lines in response to transition of a data strobe signal 213 e.g., when 610 620 are generated).
Regarding claim 3, Ku discloses wherein the processor is configured to determine a value having a highest frequency from among values of the plurality of latched data as the reception data (FIG 6; when 435 445 is at high).
Regarding claim 4, Ku discloses wherein the processor is configured to determine the plurality of delay times through a training based on the data strobe signal and the latched data (FIG 2 & 6; 110 determining delay times through a training based on 213 and latched data 450 460 from 430 and 440).
Regarding claim 8, Ku discloses wherein when receiving data from a plurality of external electronic devices(FIG 2 & 4 e.g., 110 receiving signals from 120), the processor is configured to set a plurality of delay times that are different from one another with respect to each of the plurality of external electronic devices(FIG 4 & 6; 430 440 generating latch triggers 435 and 445 based on 212 and delay times 610 620), and wherein when receiving data from one among the plurality of external electronic devices, the processor is configured to provide a plurality of delay times corresponding to the external electronic devices to the latch trigger generator(FIG 2; col 5, lines 15-19 and col 6 lines 17-25; discloses GPU 110 determining reception data based on the plurality of latched data e.g., latching data in response to an edge of a signal and so on).
Regarding claim 9, Ku discloses a storage device, comprising: a memory having at least one die(FIG 4; 400); and a memory controller configured to(100): set a plurality of delay times for the at least one die(FIG 4 & 6), generate a plurality of latch triggers based on the plurality of delay times and a data strobe signal from the memory when reading data(FIG 4 & 6; 430 440 generating latch triggers 435 and 445 based on 212 and delay times 610 620 when reading data 211), generate a plurality of latched data by latching a data line connected to the at least one die based on the plurality of latch triggers(FIG 4; 450 460(unit), 450 using data line e.g., output of 410 and latching data values from 430 440 note 450 460 as unit outputting latched data values), and determine reception data based on the plurality of latched data (FIG 2; col 5, lines 15-19 and col 6 lines 17-25; discloses GPU 110 determining reception data based on the plurality of latched data e.g., latching data in response to an edge of a signal and so on).
Regarding claim 10, Ku discloses wherein the memory controller is configured to: generate the plurality of latch triggers at time points when the plurality of delay times elapse from a time point when the data strobe signal is changed from a low to a high level , or from a high to a low level(FIG 6; 435 445 different time points corresponding to the plurality of delay times e.g., 610-620, elapsed time from a time point e.g., 410 at 445 different from 435 high to low or low to high at 620), and latch the data line at time points when the plurality of latch triggers are generated(FIG 2 & 6; col 3, lines 37- lines 49 & col 29-48 discloses timing relation among read data 211, 110 latches data on data lines in response to transition of a data strobe signal 213 e.g., when 610 620 are generated).
Regarding claim 11, Ku discloses wherein the memory controller is configured to determine a value having a highest frequency from among values of the plurality of latched data as the reception data (FIG 6; when 435 445 is at high).
Regarding claim 12, Ku discloses wherein the memory controller is configured to determine the plurality of delay times for the at least one die through a training based on the data strobe signal and the latched data (FIG 2 & 6; 110 determining delay times through a training based on 213 and latched data 450 460 from 430 and 440).
Regarding claim 16, Ku discloses wherein when the memory has a plurality of dies(FIG 2 & 4 e.g., 110 receiving signals from 120), the memory controller is configured to set a plurality of delay times that are different from one another with respect to each of the plurality of dies(FIG 4 & 6; 430 440 generating latch triggers 435 and 445 based on 212 and delay times 610 620), and wherein when receiving data from one among the plurality of dies, the memory controller is configured to generate the plurality of latch triggers using the plurality of delay times corresponding to the dies(FIG 2; col 5, lines 15-19 and col 6 lines 17-25; discloses GPU 110 determining reception data based on the plurality of latched data e.g., latching data in response to an edge of a signal and so on).
Regarding claim 17, Ku discloses an electronic apparatus(FIG 2 & 4; 400), comprising: at least one second entity(FIG 2; 120); and a first entity configured to transmit or receive data together with the at least one second entity(FIG 2; 110 receiving 211), wherein the first entity is configured to: set a plurality of delay times for the at least one second entity(FIG 4 & 6 e.g., for 211); , generate a plurality of latch triggers based on the plurality of delay times and a data strobe signal from the at least one second entity when reading data(FIG 4 & 6; 430 440 generating latch triggers 435 and 445 based on 212 and delay times 610 620 when reading data 211), generate a plurality of latched data by latching a data line connected to the at least one second entity based on the plurality of latch triggers(FIG 4; 450 460(unit), 450 using data line e.g., output of 410 and latching data values from 430 440 note 450 460 as unit outputting latched data values), and determine reception data based on the plurality of latched data(FIG 2; col 5, lines 15-19 and col 6 lines 17-25; discloses GPU 110 determining reception data based on the plurality of latched data e.g., latching data in response to an edge of a signal and so on).
Regarding claim 18, Ku discloses wherein the second entity is provided in plurality, wherein the first entity is configured to set a plurality of delay times which are different from one another with respect to each of a plurality of second entities(FIG 4 & 6; 430 440 generating latch triggers 435 and 445 based on 212 and delay times 610 620), and wherein when receiving data from one among the plurality of second entities, the first entity is configured to generate the plurality of latch triggers using a plurality of delay times corresponding to the plurality of second entities(FIG 2; col 5, lines 15-19 and col 6 lines 17-25; discloses GPU 110 determining reception data based on the plurality of latched data e.g., latching data in response to an edge of a signal and so on).
Regarding claim 19, Ku discloses wherein in order to transmit data to the at least one second entity, the first entity is configured to transmit the data strobe signal and data being synchronized to the data strobe signal through the data line(FIG 2, 4 & 6; 400 receiving data signal 211, and transmit 213 sync data through 211) , and wherein the second entity is configured to generate a plurality of latch triggers based on the data strobe signal from the first entity and a plurality of preset delay times with respect to the first entity(FIG 2, 2 & 6; 120 transmitting 211 and 213 so 100 generates those latch triggers430 440 of preset delay times e.g., 435 445 different starting point) ; generate a plurality of latched data by latching the data line connected to the first entity based on the plurality of latch triggers(610 620); and determine reception data based on the plurality of latched data(FIG 2; col 5, lines 15-19 and col 6 lines 17-25; discloses GPU 110 determining reception data based on the plurality of latched data e.g., latching data in response to an edge of a signal and so on).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-7 & 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ku et al in view of Hori et al (US20180054336).
Regarding claim 5, Ku discloses wherein the processor is configured to: generate a first plurality of latch triggers based on the first plurality of delay times and the data strobe signal from an external electronic device by transmitting a read request to the external electronic device (FIG 2 & 6; col 3, lines 37- lines 49 & col 29-48 discloses timing relation among read data 211, 110 latches data on data lines in response to transition of a data strobe signal 213 e.g., when 610 620 are generated).
However, Ku does not discloses set a first plurality of delay times arbitrarily; obtain a first plurality of latched data by latching the data line based on the first plurality of latch triggers; determine the first plurality of delay times as a final set value of the plurality of delay times when all the first plurality of latched data have a same value; and repeat, when all the first plurality of latched data do not have a same value, changing the first plurality of delay times, generating the first plurality of latch triggers and obtaining the first plurality of latched data until all the first plurality latched data have the same value.
In the same field of endeavor, Hori discloses set a first plurality of delay times arbitrarily(FIG 4; delay times setting values arbitrarily at line of 24). ; obtain a first plurality of latched data by latching the data line based on the first plurality of latch triggers(FIG 4; 15a 15b from 14); determine the first plurality of delay times as a final set value of the plurality of delay times when all the first plurality of latched data have a same value(FIG 6-8; [0066] discloses when initial value is set to D0); and repeat, when all the first plurality of latched data do not have a same value, changing the first plurality of delay times(FIG 7 & 9;[0067-0068] when setting value obtained through searching in a phase e.g., D1 e.g., increasing delay circuit 13a and so on), generating the first plurality of latch triggers and obtaining the first plurality of latched data until all the first plurality latched data have the same value(FIG 7; when Data =L).
Ku and Hori are analogous art because they are all directed to a device comprising a delay circuit, latches and calibration of delay times for data strobe signals, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Ku to include Hori because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Hori in the teachings of Ku for the benefits avoiding a use of large electric power and an increase in the data transmission rates that causes a reduction in time duration of the device ([0005 & 0010] Hori).
Regarding claim 6, The combination of Ku in view of Hori discloses wherein the processor is configured to: change the first plurality of delay times by adding a same amount of time to the first plurality of delay times(FIG 4 & 7; [0078-0080] discloses increasing by adding same amount e.g., one when reception data 36 is determined as “L”), or change, when a largest delay time after adding the same amount of time to the first plurality of delay times is larger than a time for which the data strobe signal is maintained to be in a low or a high level(FIG 7; [0082-0083] adding until a predetermine reference value is reached e.g., when signal is determined “L”), the first plurality of delay times to reduce and to equalize time gaps among the first plurality of delay times (FIG 4; [0084] 23 up/down e.g., increase or decrease).
Regarding claim 7, The combination of Ku in view of Hori discloses wherein the processor is configured to: perform the training for determining the plurality of delay times at a regular time interval(FIG 6; time interval between 610 and 620), or perform the training for determining the plurality of delay times whenever power is supplied to the electronic apparatus, or perform the training for determining the plurality of delay times when a difference between a temperature at which the plurality of delay times has been previously determined and a current temperature is equal to or more than a preset value, or perform the training for determining the plurality of delay times when values of all the plurality of latched data are not the same during determination of the reception data.
Regarding claim 13, Ku discloses wherein the memory controller is configured to: generate a first plurality of latch triggers based on the first plurality of delay times and the data strobe signal from the at least one die by transmitting a read request to the memory(FIG 2 & 6; col 3, lines 37- lines 49 & col 29-48 discloses timing relation among read data 211, 110 latches data on data lines in response to transition of a data strobe signal 213 e.g., when 610 620 are generated read data 211).
However, Ku does not disclose set a first plurality of delay times arbitrarily; obtain a first plurality of latched data by latching the data line based on the first plurality of latch triggers; determine the first plurality of delay times as a final set value of the plurality of delay times when all the first plurality of latched data have a same value; and repeat, when all the first plurality of latched data do not have a same value, changing the first plurality of delay times, generating the first plurality of latch triggers and obtaining the first plurality of latched data until all the first plurality latched data have the same value.
In the same field of endeavor, set a first plurality of delay times arbitrarily(FIG 4; delay times setting values arbitrarily at line of 24); obtain a first plurality of latched data by latching the data line based on the first plurality of latch triggers(FIG 4; 15a 15b from 14); determine the first plurality of delay times as a final set value of the plurality of delay times when all the first plurality of latched data have a same value(FIG 6-8; [0066] discloses when initial value is set to D0); and repeat, when all the first plurality of latched data do not have a same value, changing the first plurality of delay times(FIG 7 & 9;[0067-0068] when setting value obtained through searching in a phase e.g., D1 e.g., increasing delay circuit 13a and so on), generating the first plurality of latch triggers and obtaining the first plurality of latched data until all the first plurality latched data have the same value(FIG 7; when Data =L).
Ku and Hori are analogous art because they are all directed to a device comprising a delay circuit, latches and calibration of delay times for data strobe signals, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Ku to include Hori because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Hori in the teachings of Ku for the benefits avoiding a use of large electric power and an increase in the data transmission rates that causes a reduction in time duration of the device ([0005 & 0010] Hori).
Regarding claim 14, Ku discloses wherein the memory controller is configured to: change the first plurality of delay times by adding a same amount of time to the first plurality of delay times(FIG 4 & 7; [0078-0080] discloses increasing by adding same amount e.g., one when reception data 36 is determined as “L”), or change, when a greatest delay time after adding the same amount of time to the first plurality of delay times is greater than a time for which the data strobe signal is maintained to be in a low or a high level(FIG 7; [0082-0083] adding until a predetermine reference value is reached e.g., when signal is determined “L”), the first plurality of delay times such that time gaps between the first plurality of delay times are reduced and equalized(FIG 4; [0084] 23 up/down e.g., increase or decrease).
Regarding claim 15, Ku discloses wherein the memory controller is configured to: perform the training for determining the plurality of delay times at a regular time interval(FIG 6; time interval between 610 and 620), or perform the training for determining the plurality of delay times whenever power is supplied to the storage device, or perform the training for determining the plurality of delay times when a difference between a temperature at which the plurality of delay times has been previously determined and a current temperature is equal to or more than a preset value, or perform the training for determining the plurality of delay times when all values of the plurality of latched data are not the same during determination of the reception data.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Penney et al (US10176862 FIG 1), Do et al (US20060245101 FIG 5) & Dabral et al (US20040044919 FIG 1).
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827