DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species A, Group IA in the reply filed on 08/03/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, 11 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sumitomo et al. US 2015/0129927.
Regarding claim 1, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose a semiconductor device comprising:
a semiconductor substrate [0026] including a first main surface and a second main surface opposite to the first main surface;
an upper-surface electrode 23 formed on the first main surface of the semiconductor substrate;
a lower-surface electrode 24 formed on the second main surface of the semiconductor substrate;
a first gate pad 19a; and
a second gate pad 19b controlled independently of the first gate pad 19a,
wherein the semiconductor substrate includes
a first-conductivity-type drift layer 13,
a second-conductivity-type base layer 14 formed on a side of the first main surface of the drift layer,
a first-conductivity-type source layer 20 formed on the side of the first main surface of the base layer,
a plurality of first trenches 15 that penetrate the base layer 14 from the source layer 20 to reach the drift layer 13, and
a gate electrode 17a, 17b embedded in each of the plurality of first trenches through an insulating film 16, the gate electrode includes a first gate electrode 17a electrically connected to the first gate pad 19a, and a second gate electrode 17b electrically connected to the second gate pad 19b, and
a charge period and a discharge period of gate capacitance parasitic on the second gate electrode 17b are shorter than a charge period and a discharge period of gate capacitance parasitic on the first gate electrode 17a, respectively [0038]-[0051].
Regarding claim 10, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1, further comprising: a first built-in gate resistor R1 provided between the first gate electrode and the first gate pad; and a second built-in gate resistor R2 provided between the second gate electrode and the second gate pad, wherein the second built-in gate resistor is smaller than the first built-in gate resistor [0038].
Regarding claim 11, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 10, wherein the first built-in gate resistor R1 includes a first gate wiring 18 that connects the first gate electrode and the first gate pad, the second built-in gate resistor R2 includes a second gate wiring that connects the second gate electrode and the second gate pad, and a resistivity of the second gate wiring is smaller than a resistivity of the first gate wiring [0046]-[0047].
Regarding claim 18, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1, wherein the semiconductor device is an RC-IGBT.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumitomo et al. US 2015/0129927 as applied to claim 1 above, and further in view of Misumi US 2013/0134521.
Regarding claim 2, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1, but do not expressly disclose wherein resistivity of the second gate electrode is lower than resistivity of the first gate electrode.
However, Misumi in [0039] teaches an IGBT with a width of one trench 19 is made wider than the width of the other trench 19, or the resistance value of the gate electrode is made different by making the concentration of impurities contained in the gate electrode 22 different and the turn-on time is made different. Accordingly, the short-circuit capacity of the entire semiconductor device in the case where the semiconductor device operates in a short-circuit state can be enhanced.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Misumi in the device of Sumitomo et al. for the purpose of enhancing the performance of the device.
Regarding claim 3, Sumitomo et al. in view of Misumi teach the semiconductor device according to claim 2. Misumi [0039] teaches wherein impurity concentration of a semiconductor material configuring the second gate electrode is higher than impurity concentration of a semiconductor material configuring the first gate electrode.
Regarding claim 4, Sumitomo et al. in view of Misumi teach the semiconductor device according to claim 2. Misumi [0038] teaches wherein a sectional area of the second gate electrode is larger than a sectional area of the first gate electrode.
Regarding claim 5, Sumitomo et al. in view of Misumi teach the semiconductor device according to claim 2, but do not expressly disclose wherein the second gate electrode is made of metal. The material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See MPEP 2144.07
Regarding claim 19, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1, but do not expressly disclose wherein the semiconductor device is a MOSFET. However, Misumi in [0050] teaches an MOSFET.
Regarding claim 20, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1, but do not expressly disclose wherein the semiconductor substrate is made of a wide band gap semiconductor. However, Misumi in [0050] teaches wherein the semiconductor substrate is made of a wide band gap semiconductor GaN material.
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumitomo et al. US 2015/0129927 as applied to claim 1 above, and further in view of Iwakaji et al. US 2020/0303525.
Regarding claim 6, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1 but do not expressly disclose wherein the gate capacitance parasitic on the second gate electrode is smaller than the gate capacitance parasitic on the first gate electrode.
However, Iwakaji et al. in Figs. 1 and 6 and [0064]-[0065], [0099],[0105]-[0110] teach an IGBT with first gate electrode 51 and second gate electrode 52 including first and second gate trenches 21, 22 connected to first and second gate electrode pads 101, 102 in order to shorten the turn sound time and the turn off time and a thickness of a gate insulating film 41 of the first gate trench 21 is thicker than a gate insulating film 42 or the second gate trench 22 in order to reduce the gate capacitance.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Iwakaji et al. in the device of Sumitomo et al. for the purpose of improving the device performance.
Regarding claim 7, Sumitomo et al. in view of Iwakaji et al. teach the semiconductor device according to claim 6. Iwakaji et al. in Figs. 1 and 6 and [0064]-[0065], [0099],[0105]-[0119] teach wherein a second gate insulating film that is the insulating film formed between the second gate electrode and an inner wall of the first trench is thicker than a first gate insulating film that is the insulating film formed between the first gate electrode and the inner wall of the first trench.
Regarding claim 8, Sumitomo et al. in view of Iwakaji et al. teach the semiconductor device according to claim 6. Iwakaji et al. in Figs. 1 and 6 and [0056] teach wherein a surface area of the second gate electrode is smaller than a surface area of the first gate electrode.
Regarding claim 9, Sumitomo et al. in view of Iwakaji et al. teach the semiconductor device according to claim 6. Iwakaji et al. in Figs. 1 and 6 and [0056] teach wherein the second gate electrode is made of amorphous silicon.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumitomo et al. US 2015/0129927 as applied to claim 1 above, and further in view of Ogura et al. JP 2022-145934.
Regarding claim 12, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1, but do not expressly disclose wherein in at least one first trench of the plurality of first trenches, the second gate electrode is embedded in a lower stage, the first gate electrode is embedded in an upper stage, and a boundary insulating film that insulates the first gate electrode and the second gate electrode from each other is provided between the first gate electrode and the second gate electrode.
However, Ogura et al. in Figs. 15-19 and [0019],[0070]-[0072],[0081]-[0087] teach an IGBT having a trench 21, a first gate electrode 17 in the trench electrically connected to a first gate pad 52 via a first gate wiring on the upper stage of a second gate electrode 19 via an inter-electrode insulating film 20.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Ogura et al. in the device of Sumitomo et al. for the purpose of providing an IGBT with low ON voltage and reduced switching loss.
Regarding claim 13, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1, but do not expressly disclose wherein the second gate pad is turned on after the first gate pad is turned on, and the first gate pad is turned off after the second gate pad is turned off.
However, Ogura et al. in Figs. 15-19 and [0019],[0070]-[0072],[0081]-[0087] teach an IGBT having a trench 21, a first gate electrode 17 in the trench electrically connected to a first gate pad 52 via a first gate wiring on the upper stage of a second gate electrode 19 via an inter-electrode insulating film 20. Ogura et al. further teach a second gate electrode 19 electrically connected to a second gate pad 53 via a second gate wiring, and after being turned on by the first gate voltage Vg1 applied to a first gate electrode 17, it is turned on by a second gate Vg2 and after being turned off by the second gate voltage Vg2, it is turned off by the first gate voltage Vg1.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Ogura et al. in the device of Sumitomo et al. for the purpose of providing an IGBT with low ON voltage and reduced switching loss.
Claim(s) 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sumitomo et al. US 2015/0129927 as applied to claim 1 above, and further in view of Satoh US 2023/0147438.
Regarding claim 14, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1 but do not expressly disclose the semiconductor device further comprising a third gate pad controlled independently of the first gate pad and the second gate pad, wherein the gate electrode includes a third gate electrode electrically connected to the third gate pad, and a charge period and a discharge period of the gate capacitance parasitic on the third gate electrode are shorter than a charge period and a discharge period of the gate capacitance parasitic on the second gate electrode, respectively.
However, Satoh teaches in Figs. 1-3 and [0008]-[0125] a multi-gate IGBT using a third gate as an auxiliary gate, to control dIon/dt or dVoff/dt more precisely than when controlled by a first and second gate. Satoh further teaches that the auxiliary gate inputs a turn-on control signal earlier than the auxiliary gate by the adjustment time TonH at the time of turn-on switching, and inputs a turn-off control signal later than the auxiliary gate by the adjustment time ToffH at the time of turn-off switching.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Satoh in the device of Sumitomo et al. for the purpose of reducing switching loss in the IGBT.
Regarding claim 15, Sumitomo et al. in view of Satoh teach the semiconductor device according to claim 14. Satoh in Figs. 1-3 and [0008]-[0125] teaches wherein the second gate pad is turned on after the third gate pad is turned on, and the first gate pad is turned off after the third gate pad is turned off.
Regarding claim 16, Sumitomo et al. in Figs. 1, 2, 4 and 5-7, [0026]-[0067] disclose the semiconductor device according to claim 1 but do not expressly disclose wherein the semiconductor substrate includes at least one second trench reaching the drift layer from the second main surface, and the second gate electrode is embedded inside the second trench instead of the first trench.
However, Satoh teaches in Figs. 1-3 and [0008]-[0125] a multi-gate IGBT including semiconductor substrate 30 and at least one second trench 21 penetrating the p-type collector region 2 and further reaching the inside of the n-type base layer 1 from a second main surface, and a second gate electrode 17 is embedded inside the second trench 21 instead of the first trench.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Satoh in the device of Sumitomo et al. for the purpose of reducing switching loss in the IGBT.
Regarding claim 17, Sumitomo et al. in view of Satoh teach the semiconductor device according to claim 16. Satoh in Figs. 1-3 and [0008]-[0125] teaches wherein the first gate pad is turned off after the second gate pad is turned on.
Conclusion
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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