DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/04/2025 has been entered.
Claim Objections
Claims 5-6 and 10 are objected to because of the following informalities:
As per claims 5 and 6, the limitation “the multiplexer” should be “the demultiplexer”.
As per claim 10, the limitation “wherein the hold capacitor comprises a seventh transistor comprising a control terminal coupled to control terminal of the first transistor, a first terminal coupled to the supply terminal, and a second terminal coupled to the supply terminal” should be “wherein the hold capacitor comprises a seventh transistor comprising a control terminal coupled to the control terminal of the first transistor, a first terminal coupled to the supply terminal, and a second terminal coupled to the supply terminal”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 and 6 recites the limitation “the multiplexer”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 9, 11, 13, 15, 18-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sang (US 20230097941) in view of Shin (US 20050110727).
As per claim 1, Sang discloses a pixel circuit (Fig. 1; [0068]), the pixel circuit comprising:
a sample circuit (#T1) coupled to a data line (#21; [0074]);
a first transistor (#DT) comprising a control terminal coupled to the sample circuit (#T1), a first terminal coupled to a supply terminal (#VDD), and a second terminal ([0071]);
a second transistor (#T2) comprising a first terminal coupled to the control terminal of the first transistor (#DT), and a second terminal coupled to the second terminal of the first transistor (#DT);
a third transistor (#T4) comprising a first terminal coupled to the second terminal of the first transistor (#DT), and a second terminal ([0077]);
a light-emitting diode (LED) (#EL) comprising a first terminal coupled to the second terminal of the third transistor (#T4), and a second terminal coupled to a ground terminal (#VSS); and
a fourth transistor (#T5) comprising a first terminal coupled to the first terminal of the light-emitting diode (#EL), and a second terminal coupled to a reset terminal ([0078]; [0082]-[0083]);
wherein in an initial mode, the sample circuit (#T3) is enabled and the fourth transistor (#T5) is turned on ([0082]).
However, Sang does not teach a sample circuit coupled to a data line via a demultiplexer to sample pixel data.
Shin teaches a demultiplexer (Figs. 2 and 10) to sample pixel data ([0059]-[0060]; [0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the sample circuit of Sang coupled to the data line via the demultiplexer as disclosed by Shin so as to provide a demultiplexer that samples and holds the data current corresponding to a pixel of the same color (Shin: [0009]).
As per claims 3 and 15, Sang in view of Shin discloses the pixel circuit (display device) of Claim 1 (Claim 13), wherein (each of the row of) pixel circuit(s) is switched to a compensation mode after the initial mode (Sang: Figs. 2B and 3B; [0080]-[0081]; [0084]-[0085]).
As per claim 7, Sang in view of Shin discloses the pixel circuit of Claim 3, further comprising:
a sixth transistor (Sang: #T3) comprising a first terminal coupled to the first terminal of the second transistor (Sang: #T2); and
a second terminal coupled to the first terminal of the fourth transistor (Sang: #T5).
As per claim 9, Sang in view of Shin discloses the pixel circuit of Claim 1, further comprising:
a hold capacitor (Sang: Fig. 4A, #Cst) comprising a first terminal coupled to the supply terminal (Sang: #VDD), and a second terminal coupled to the control terminal of the first transistor (Sang: #DT).
As per claims 11 and 21, Sang in view of Shin discloses the pixel circuit (display device) of Claim 3 (Claim 15), (wherein each of the row of pixel circuits) further comprising:
a sixth transistor (Sang: #T3) comprising a first terminal coupled to the supply terminal (Sang: #VDD); and a second terminal coupled to the first terminal of the first transistor (Sang: Fig. 2A, #DT).
As per claim 13, Sang discloses a display device (Fig. 31; [0193]) comprising:
a plurality of scan lines (#103; [0194]);
a plurality of data lines (#102; [0194]); and
a pixel array (#101) comprising a row of pixel circuits ([0194]-[0195]; [0198]), each of the row of pixel circuits comprising:
a sample circuit (#T1) coupled to one of the plurality of scan lines ([0074]),
a first transistor (#DT) comprising a control terminal coupled to the sample circuit (#T3), a first terminal coupled to a supply terminal (#VDD), and a second terminal ([0071]);
a second transistor (#T2) comprising a first terminal coupled to the control terminal of the first transistor (#DT), and a second terminal coupled to the second terminal of the first transistor (#DT);
a third transistor (#T4) comprising a first terminal coupled to the second terminal of the first transistor (#DT), and a second terminal ([0077]);
a light-emitting diode (LED) (#EL) comprising a first terminal coupled to the second terminal of the third transistor (#T4), and a second terminal coupled to a ground terminal (#VSS); and
a fourth transistor (#T5) comprising a first terminal coupled to the first terminal of the light-emitting diode (#EL), and a second terminal coupled to a reset terminal ([0078]; [0082]-[0083]);
wherein in an initial mode, the sample circuit (#T3) is enabled and the fourth transistor (#T5) is turned on ([0082]).
However, Sang does not teach a demultiplexer coupled to one of the plurality of data lines; and
a sample circuit coupled to the demultiplexer to sample pixel data.
Shin teaches a demultiplexer (Figs. 2 and 10) coupled to one of the plurality of data lines ([0059]; [0088]); and the demultiplexer to sample pixel data ([0059]-[0060]; [0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the sample circuit of Sang coupled to the data line via the demultiplexer as disclosed by Shin so as to provide a demultiplexer that samples and holds the data current corresponding to a pixel of the same color (Shin: [0009]).
As per claim 18, Sang in view of Shin discloses the display device of Claim 13, wherein the sample circuit comprises:
a fifth transistor (Sang: #T1) comprising a control terminal coupled to the one of the plurality of scan lines (Sang: #31), a first terminal coupled to the one of the plurality of data lines (Sang: #21); and a second terminal; and
a sense capacitor (Sang: #Cst) comprising a first terminal coupled to the second terminal of the fifth transistor (Sang: #T1), and a second terminal coupled to the control terminal of the first transistor (Sang: #DT).
As per claim 19, Sang in view of Shin discloses the display device of Claim 15, wherein each of the row of pixel circuits further comprises:
a sixth transistor (Sang: #T3) comprising a first terminal coupled to the first terminal of the second transistor (Sang: #T2); and
a second terminal coupled to the first terminal of the fourth transistor (Sang: #T5).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sang in view of Shin in view of Han (US 20140118229).
As per claim 17, Sang in view of Shin discloses the display device of Claim 13.
However, Sang and Shin do not teach the sample circuit comprises:
a sense capacitor comprising a first terminal coupled to the one of the plurality of data lines, and a second terminal; and
a fifth transistor comprising a control terminal coupled to the one of the plurality of scan lines, a first terminal coupled to the second terminal of the sense capacitor; and
a second terminal coupled to the control terminal of the first transistor.
Han teaches the sample circuit comprises:
a sense capacitor (Fig. 3, #C1) comprising a first terminal coupled to the one of the plurality of data lines (#data[j]), and a second terminal; and
a fifth transistor (#TR1) comprising a control terminal coupled to the one of the plurality of scan lines (#S[i]), a first terminal coupled to the second terminal of the sense capacitor (#C1); and
a second terminal coupled to the control terminal of the first transistor (#TR2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the sample circuit of Sang in view of Shin configured according to Han so as to provide one electrode coupled to the data line and the other electrode coupled to a first node.
Allowable Subject Matter
Claims 4, 8, 12, 16, 20 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of a pixel circuit comprising a sample circuit, a first transistor, a second transistor, a third transistor, a fourth transistor and a light-emitting diode (LED) does not teach or fairly suggest in the compensation mode, the sample circuit is enabled, the fourth transistor is turned on, the second transistor is turned on, and the third transistor is turned off; in a program mode, the sample circuit is enabled, the fourth transistor is turned on, the second transistor is turned off, and the third transistor is turned off; and in an emission mode, the sample circuit is disabled, the fourth transistor is turned off, the second transistor is turned off, and the third transistor is turned on, in the initial mode, the sixth transistor is turned on, the second transistor is turned off, and the third transistor is turned off; and in the compensation mode, a program mode and an emission mode, the sixth transistor is turned off, in the initial mode, the sixth transistor is turned off, the second transistor is turned on, and the third transistor is turned on; and in the compensation mode, a program mode and an emission mode, the sixth transistor is turned on.
Claims 23 and 24 are allowed.
The following is an examiner’s statement of reasons for allowance: The prior art of a pixel circuit, the pixel circuit comprising a sample circuit; a first transistor comprising a control terminal coupled to the sample circuit, a first terminal coupled to a supply terminal, and a second terminal; a second transistor comprising a first terminal coupled to the control terminal of the first transistor, and a second terminal coupled to the second terminal of the first transistor; a third transistor comprising a first terminal coupled to the second terminal of the first transistor, and a second terminal; a light-emitting diode (LED) comprising a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a ground terminal; and a fourth transistor comprising a first terminal coupled to the first terminal of the light-emitting diode and a second terminal, and a second terminal coupled to a reset terminal; wherein the pixel circuit is switched to a compensation mode after an initial mode does not teach or fairly suggest in the compensation mode, the sample circuit is enabled, the fourth transistor is turned on, the second transistor is turned on, and the third transistor is turned off, in a program mode, the sample circuit is enabled, the fourth transistor is turned on, the second transistor is turned off, and the third transistor is turned off, and in an emission mode, the sample circuit is disabled, the fourth transistor is turned off, the second transistor is turned off, and the third transistor is turned on.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1 and 13 have been considered but are moot because of the new grounds of rejection as presented above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached on 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/Examiner, Art Unit 2627
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627