DETAILED ACTION
1. This action is in response to the application filed on 4/26/24.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1, 8, 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Panter et al. (US 20240427362).
Regarding claim 1: Panter et al. a power conversion circuit (i.e. figures 1A and 2), comprising:
a first input circuit (i.e. 110), configured to receive a first input voltage (i.e. VSUP1) through a first input terminal (i.e. terminal of 110);
a second input circuit (i.e. circuit includes 218, 220, 222, 224), configured to receive a second input voltage (i.e. VSUP2) through a second input terminal (i.e. terminal of 108),
wherein the first input voltage (i.e. VSUP1) is higher than the second input voltage (i.e. VSUP2) (i.e. ¶ 22-24);
a linear regulator (i.e. 106), configured to receive the first input voltage (i.e. VSUP1) or the second input voltage (i.e. VSUP2) to output an output voltage (i.e. VOUT_LDO);
a switch (i.e. 126 or 128), having a first terminal and a second terminal, wherein the first terminal is coupled (i.e. electrically coupled) to the first input circuit (i.e. 110), and the second terminal is coupled (i.e. electrically coupled) to the second input circuit (i.e. 108) and the linear regulator (i.e. 106); and
a switch control circuit (i.e. control circuit of 1A and 2), configured to output a control signal (i.e. from 116) to open the switch (i.e. 126 or 128) when receiving the second input voltage (i.e. VSUP2) that reaches a predetermined level (i.e. predetermined threshold), so that the first input circuit (i.e. 110) is disconnected (i.e. switch 126 OFF) from the linear regulator (i.e. 106), and the linear regulator (i.e. 106) outputs the output voltage (i.e. VOUT_LDO) according to the second input voltage (i.e. VSUP2) (i.e. ¶ 22-24 and 29-32).
Regarding claim 8: (i.e. figures 1A and 2) wherein the linear regulator is a low dropout linear regulator (i.e. 106).
Regarding claim 10: (i.e. figures 1A and 2) wherein when the second input voltage (i.e. VSUP2) is interrupted or has not reached the predetermined level (i.e. predetermined threshold), the switch control circuit short-circuits (i.e. control circuit of 1A and 2) the switch (i.e. 126 or 128) to reconnect the first input circuit (i.e. terminal of 110) and the linear regulator (i.e. 106), so that the linear regulator (i.e. 106) outputs the output voltage (i.e. VOUT_LDO) according to the first input voltage (i.e. VSUP1) (i.e. ¶ 22-24 and 29-32).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Panter et al. (US 20240427362) in view of Kayama (US 20140145504).
Regarding claim 2: Panter et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a voltage conversion circuit, configured to convert the first input voltage into the second input voltage, and output the second input voltage to the switch control circuit.
Kayama disclose circuit a voltage conversion circuit (i.e. figure 5), configured to convert the first input voltage (i.e. Vin) into the second input voltage (i.e. voltage at DDOUT2), and output the second input voltage (i.e. DDOUTT2) to the switch control circuit (i.e. provide to circuit R3, MP2, MP3 of circuit 12141).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Panter et al.’s invention with the power supply as disclose by Kayama to employ a high-efficiency DC-DC converter to generate an almost constant DC voltage.
Regarding claim 3: Panter et al. disclose (i.e. figures 1A and 2) wherein the switch control circuit comprises: a test circuit (i.e. circuit includes 226), configured to output an enable signal (i.e. Rep_Sup2) when determining that the second input voltage (i.e. VSUP2) has reached the predetermined level (i.e. predetermined threshold); and a control circuit (i.e. control circuit of 1A and 2), configured to receive the enable signal (i.e. Rep_Sup2) and output the control signal (i.e. from 116) (i.e. ¶ 38-42).
7. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Panter et al. (US 20240427362) in view of Huang (US 20110127984).
Regarding claim 7: Panter et al. discloses the limitation of the claim(s) as discussed above, but does not specifically disclose the first input circuit is a first diode, wherein an anode of the first diode is configured as the first input terminal, and a cathode of the first diode is coupled to the first terminal of the switch; and the second input circuit is a second diode, wherein an anode of the second diode is configured as the second input terminal, and a cathode of the second diode is coupled to the second terminal of the switch.
Huang discloses a circuit (i.e. figure 2) comprising the first input circuit is a first diode (i.e. D1), wherein an anode of the first diode is configured as the first input terminal (i.e. terminal of D1), and a cathode of the first diode (i.e. D1) is coupled to the first terminal of the switch (i.e. Q1); and the second input circuit is a second diode (i.e. D2), wherein an anode of the second diode is configured as the second input terminal (i.e. terminal of D2), and a cathode of the second diode is coupled to the second terminal of the switch (i.e. Q1).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Panter et al.’s invention with the circuit as disclose by Huang to provide efficient power management capability.
8. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Panter et al. (US 20240427362) in view of Yannaguchi (US 6060789).
Regarding claim 9: Panter et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a third input circuit, configured to receive a third input voltage through a third input terminal, wherein the first input voltage is higher than the third input voltage, and the third input voltage is higher than the second input voltage.
Yannaguchi disclose a power supply (i.e. figure 2) comprising a third input circuit (i.e. circuit for 203), configured to receive a third input voltage (i.e. from 203) through a third input terminal, wherein the first input voltage (i.e. from 201) is higher than the third input voltage (i.e. from 203), and the third input voltage (i.e. from 203) is higher than the second input voltage (i.e. 204) (i.e. voltage from 201 is 5V, the series voltage from battery 203 and 204 is 6 V total. Overtime the voltage from battery 204 may be lower than the voltage 203. Therefore, the first input voltage is higher than the third input voltage and the third input voltage is higher than the second input voltage) (i.e. Col. 5 through 6).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Panter et al.’s invention with the power supply as disclose by Yannaguchi so that the voltage of an external power source for the portable device can be supplied to the portable device without causing dissipation of the built-in batteries if the voltage of the external power source for the portable device, although lower than the voltage of the built-in batteries, is not lower than a fixed level.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/Primary Examiner, Art Unit 2838