Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 26, 2024 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description:
Figs. 3/5/6: elements FMb and BMb
Fig. 5: element SCb
Figs. 25/26/28: element ET12.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Device with Back-side and Front-side Alignment Structures.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitations "the lower active contact" and “the lower gate contact” in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim since claim 13 depends from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-11, 15, 19-20 are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US20210367036A1) in view of Zhu et al. (US8299583B2).
Regarding Claim 1:
Kim discloses a semiconductor device comprising (Fig. 1):
a substrate (Fig. 2A element 100) comprising a logic cell region (Fig. 1 element LC) comprising active patterns (Fig. 2C element AP1/2) spaced apart in a first direction (D1) and extending in a second direction (D2) different from the first direction;
source/drain patterns (Fig. 2C elements SD1/2) on the active patterns (elements AP1/2) of the logic cell region (element LC) and spaced apart in the second direction (D2);
a channel pattern (Figs. 2A-B elements CH1/2) between the source/drain patterns (elements SD1/2, paragraphs 41-42); and
a gate pattern extending (Figs. 2A-D elements GE) in the first direction, crossing between the source/drain patterns (elements SD1/2), and surrounding at least a part of the channel pattern (paragraph 54), and
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wherein the substrate (Fig. 2A element 100) has an upper surface and a lower surface (See annotated fig. attached below) facing each other in a third direction (D3) different from the first direction and the second direction.
However, Kim does not explicitly teach an overlay region comprising a back-side and a front-side key pattern nor their arrangements.
Zhu discloses an analogous semiconductor structure (Fig. 12), comprising an overlay key region (Fig. 5 element 8) comprising a back-side key pattern (element 14') and a front-side key pattern (element 12');
wherein the back-side key pattern (Figs. 1-7 element 14') of the overlay key region extends into the lower surface of the substrate (elements 80 and 9', paragraph 32).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include an overlay region comprising a front-side key pattern and a back-side key pattern – extending into the lower surface of the substrate – because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process while reducing the overall cost (Zhu, paragraphs 5-6 and 18).
Regarding Claim 2:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, however Kim does not explicitly teach where a lower surface of the back-side key pattern and substrate are coplanar.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein a lower surface of the back-side key pattern (second end surface; Figs. 1-7 element 14') and the lower surface of the substrate (element 9') are generally coplanar (paragraph 34).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include where a lower surface of the back-side key pattern and lower surface of the substrate are generally coplanar because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 3:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, however Kim does not explicitly teach the back-side key pattern extending from the lower to upper surface of the substrate.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein the back-side key pattern (Fig. 12 element 14') extends in the third direction (D3; see annotated fig. attached below) from the lower surface (element 9') of the substrate to the upper surface (element 7).
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It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include where the back-side key pattern extends from the lower surface to the upper surface of the substrate – in the third direction – because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 4:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, however Kim does not explicitly teach where the front-side key pattern is spaced apart from the lower surface of the substrate.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein the front-side key pattern (Fig. 12 element 12') is spaced apart from the lower surface of the substrate (paragraph 18).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include where the front-side key pattern is spaced apart from the lower surface of the substrate because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 5:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, however Kim does not explicitly teach where a lower surface of the back-side key pattern is located closer to the lower surface of the substrate than that of the front-side key pattern.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein a lower surface of the back-side key pattern (second end surface; Figs. 1-7 element 14') is located closer to the lower surface of the substrate (element 9') than a lower surface of the front-side key pattern (second end surface; element 12', paragraphs 17-18).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include where a lower surface of the back-side key pattern is located closer to the lower surface of the substrate than a lower surface of the front-side key pattern because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 6:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, however Kim does not explicitly teach where both of the upper surfaces of the front-side and back-side key patterns extend into the upper surface of the substrate.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein an upper surface of the back-side key pattern (first end surface; Fig. 4 element 14') extends into the upper surface of the substrate (element 7, paragraph 18), and
an upper surface of the front-side key pattern (first end surface; Fig. 4 element 12') extends into the upper surface of the substrate (element 7, paragraph 18).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include where the upper surfaces of the back-side and front-side key patterns extend into the upper surface of the substrate because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 7:
The combination of Kim and Zhu disclose a semiconductor device according to claim 6, however Kim does not explicitly teach where the upper surfaces of the back-side key pattern and substrate are located at the same level nor where the upper surfaces of the front-side key pattern and substrate are coplanar.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein the upper surface of the back-side key pattern (first end surface; Fig. 12 element 14') and the upper surface of the substrate (element 7) are located at a same level in the third direction (D3; see annotated fig. attached above), and
the upper surface of the front-side key pattern (first end surface; Fig. 12 element 12') and the upper surface of the substrate are generally coplanar (paragraph 22).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include where the upper surfaces of the back-side key pattern and substrate are located at the same level – in the third direction. Furthermore, where the upper surfaces of the front-side key pattern and substrate are coplanar because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 8:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, however Kim does not explicitly teach a length of the back-side key pattern that is greater than that of the front-side key pattern.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein a length of the back-side key pattern in the third direction is greater a length of the front-side key pattern in the third direction (paragraphs 17-18).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include a length of the back-side key pattern to be greater – in the third direction – than a length of the front-side key pattern because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 9:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, further comprising an upper active contact (Fig. 2C elements AC) above the source/drain patterns (elements SD1/2) and connected to the source/drain patterns (paragraph 70) in the third direction (D3) with the lower surface of the substrate being a base reference plane (See annotated fig. attached above); and
an upper gate contact (Fig. 2D element GC) above the gate pattern (element GE) in the third direction with the lower surface of the substrate being the base reference plane (See annotated fig. attached above) and connected to the gate pattern (paragraph 73).
Regarding Claim 10:
The combination of Kim and Zhu disclose a semiconductor device according to claim 9, further comprising a first upper interlayer insulating layer (Fig. 2C-D element 130) above the upper active contact (element AC) and the upper gate contact (element GC) in the third direction (D3) with the lower surface of the substrate being the base reference plane (See annotated fig. attached above) and including a first upper metal layer (element M1).
Regarding Claim 11:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, further comprising an interlayer insulating layer on the substrate (Fig. 2C elements 120 and 100, paragraph 65). However, Kim does not explicitly teach where upper surfaces of a back-side and front-side key pattern contact a lower surface of said interlayer insulating layer.
Zhu discloses an analogous semiconductor structure (Fig. 12), comprising an upper surface of the back-side key pattern (first end surface; Fig. 12 element 14') and an upper surface of the front-side key pattern (first end surface; Fig. 12 element 12').
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu such the lower surface of the interlayer insulating layer is in contact with the upper surfaces of the back-side and front-side key patterns because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 15:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, however Kim does not explicitly teach where the back-side and front-side key patterns include silicon oxide.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein the back-side key pattern (Figs. 1-7 elements 14' and 10) includes silicon oxide (paragraphs 19), and the front-side key pattern (elements 12' and 10) includes silicon oxide (paragraphs 19).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include where both the back-side and front-side key patterns contain silicon oxide because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Regarding Claim 19:
Kim discloses a semiconductor device comprising (Fig. 1):
a substrate (Fig. 2A element 100) comprising active patterns spaced apart (Fig. 2C element AP1/2) in a first direction (D1) and extending in a second direction (D2) different from the first direction, a device isolation pattern (element ST) between the active patterns in the first direction (paragraphs 37-38), and
sacrificial layers (Fig. 4B elements SAL) and active layers (element ACL) on the active patterns (elements AP1/2) and alternately stacked in a third direction different from the first direction and the second direction (paragraph 102).
However, Kim does not explicitly teach a back-side or front-side key pattern on the device isolation pattern nor their arrangements.
Zhu discloses an analogous semiconductor structure (Fig. 12), comprising a back-side key pattern (Figs. 1-7 element 14') and a front-side key pattern (element 12');
wherein the back-side key pattern extends (Fig. 12 element 14'), and
wherein the front-side key pattern extends (element 12'), and is spaced apart from a lower surface of the substrate (paragraph 18).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include back-side and front-side key patterns that extend into the lower surface of the device isolation pattern because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process while reducing the overall cost (Zhu, paragraphs 5-6 and 18).
Regarding Claim 20:
The combination of Kim and Zhu disclose a semiconductor device according to claim 19, however Kim does not explicitly teach where a lower surface of the front-side key pattern is a lower level that the sacrificial layers.
Zhu discloses an analogous semiconductor structure (Fig. 12), comprising a lower surface of the front-side key pattern (second end surface; Figs. 1-7 element 12') extending in a third direction (D3; paragraphs 17-18).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu to explicitly include a front-side key pattern with a lower surface at a lower level than the sacrificial layers – with the lower surface of the substrate being the base reference plane – because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US20210367036A1) in view of Zhu et al. (US8299583B2) as applied to claim 1 above, and further in view of Huang et al. (US20220352326A1) and Kim et al. (US20200066683A1), hereinafter referred to as "Kim '683".
Regarding Claim 12:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, but neither Kim nor Zhu explicitly teach a lower active contact or a lower gate contact nor their arrangements.
Huang, however, discloses an analogous semiconductor device (Fig. 25 element 200), comprising a lower active contact (Fig. 25 element 268) below the source/drain patterns (elements 232S/D), extending into the active patterns (paragraph 66), and electrically connected to the source/drain patterns (paragraph 42), but Huang does not explicitly teach a lower gate contact.
Kim '683, however, discloses an analogous semiconductor device (Fig. 9), comprising a lower gate contact (Fig. 9 element 175) below the gate pattern (element 230), extending into the active patterns (paragraph 39), and electrically connected to the gate pattern (paragraphs 109-110).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim and Zhu further in view of Huang and Kim '683 to explicitly include a lower active contact, electrically connected to source/drain patterns, and a lower gate contact, electrically connected to the gate pattern, because all are directed to analogous semiconductor devices. Doing so improves the integration of semiconductor devices while increasing the density (Kim '683, paragraphs 3-4; Huang, paragraphs 1-2).
Regarding Claim 13:
The combination of Kim and Zhu disclose a semiconductor device according to claim 1, but neither Kim nor Zhu explicitly teach a first lower interlayer insulating layer comprising a first lower metal layer.
Kim '683, however, discloses an analogous semiconductor device (Fig. 9), further comprising a first lower interlayer insulating layer (Fig. 9 element 105) below a lower gate contact (element 175) in the third direction (D3; see annotated fig. attached below), but does not explicitly teach a lower active contact nor that the layer includes a metal layer.
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Huang, however, discloses an analogous semiconductor device (Fig. 25 element 200), comprising a lower active contact (Fig. 25 element 268) and a first lower metal layer (element 272, paragraphs 39 and 43).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim and Zhu further in view of Huang and Kim '683 to explicitly include a first lower interlayer insulating layer – comprising a first lower metal layer – below a lower active and gate contact because all are directed to analogous semiconductor devices. Doing so improves the integration of semiconductor devices while increasing the density (Kim '683, paragraphs 3-4; Huang, paragraphs 1-2).
Regarding Claim 14:
The combination of Kim, Zhu, Huang, and Kim '683 disclose a semiconductor device according to claim 13, but neither Kim, Huang, nor Kim ‘683 explicitly teach where the lower surface of the back-side key pattern is in contact with the upper surface of the first lower interlayer insulating layer.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein a lower surface of the back-side key pattern (second end surface; Figs. 1-7 element 14') contacts an upper surface of a lower interlayer insulating layer (elements 98 and 90, paragraph 39-41).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim, Huang, and Kim '683 further in view of Zhu to explicitly include a lower surface of the back-side key pattern in contact with an upper surface of the first lower interlayer insulating layer because both are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US20210367036A1) in view of Zhu et al. (US8299583B2), Huang et al. (US20220352326A1), and Kim '683.
Regarding Claim 16:
Kim discloses a semiconductor device (Fig. 1) comprising:
a substrate (Fig. 2A element 100) comprising a logic cell region (Fig. 1 element LC) comprising active patterns (Fig. 2C element AP1/2) spaced apart in a first direction (D1) and extending in a second direction (D2) different from the first direction, the substrate having an upper surface and a lower surface facing each other in a third direction (D3) different from the first direction and the second direction (See annotated fig. attached above);
source/drain patterns (Fig. 2C elements SD1/2) on the active patterns (elements AP1/2) of the logic cell region (element LC) and spaced apart in the second direction (D2);
a channel pattern (Figs. 2A-B elements CH1/2) located between the source/drain patterns (elements SD1/2, paragraphs 41-42); and
a gate pattern extending (Figs. 2A-D elements GE) in the first direction, crossing between the source/drain patterns (elements SD1/2), and surrounding at least a part of the channel pattern (paragraph 54).
However, Kim does not explicitly teach an overlay region comprising front-side and back-side patterns, a lower active and gate contact, or a lower interlayer insulating layer nor their arrangements.
Zhu discloses an analogous semiconductor structure (Fig. 12), comprising an overlay key region (Fig. 5 element 8) comprising a front-side key pattern (element 12') and a back-side key pattern (element 14'); and a lower surface of the back-side key pattern (second end surface; Figs. 1-7 element 14') of the overlay key region (element 8), but does not explicitly teach where the lower surface in is contact with a first lower interlayer insulating layer.
Kim '683, however, discloses an analogous semiconductor device (Fig. 9), further comprising a lower gate contact below a gate pattern (Fig. 9 elements 175 and 230) in the third direction (D3) with the lower surface of the substrate being the base reference plane, extending into the active patterns (see annotated figs. attached above), and electrically connected to the gate pattern (paragraphs 109-110); and a first lower interlayer insulating layer (Fig. 9 element 105). Kim ‘683 does not explicitly teach a lower active contact.
Huang, however, discloses an analogous semiconductor device (Fig. 25 element 200), comprising a lower active contact (Fig. 25 element 268) below source/drain patterns (elements 232S/D) in the third direction (-Z) with the lower surface of the substrate (element 202) being a base reference plane, extending into the active patterns (paragraph 66), and electrically connected to the source/drain patterns (elements 232S/D, paragraph 42), and a first lower metal layer (element 272, paragraphs 39 and 43).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim further in view of Zhu, Huang and Kim '683 to explicitly include front-side and back-side patterns, a lower active and gate contact, a lower interlayer insulating layer and their arrangements because all are directed to analogous semiconductor devices. Doing so improves the integration of semiconductor devices, the accuracy and efficiency of the alignment process, while also allowing for the increase of density (Kim '683, paragraphs 3-4; Huang, paragraphs 1-2; Zhu, paragraphs 5-6 and 18).
Regarding Claim 17:
The combination of Kim, Zhu, Huang, and Kim '693 disclose a semiconductor device according to claim 16, wherein Kim further discloses an upper active contact (Fig. 2C elements AC) located above the source/drain patterns (elements SD1/2) in the third direction (D3) with the lower surface of the substrate being a base reference plane (See annotated fig. attached above) and connected to the source/drain patterns (paragraph 70);
an upper gate contact (Fig. 2D element GC) located above the gate pattern (element GE) in the third direction with the lower surface of the substrate being the base reference plane (See annotated fig. attached above) and connected to the gate pattern (paragraph 73);
a first upper interlayer insulating layer (Fig. 2C-D element 130) above the upper active contact (element AC) and the upper gate contact (element GC) in the third direction (D3) with the lower surface of the substrate being the base reference plane (See annotated fig. attached above) and including a first upper metal layer (element M1).
Regarding Claim 18:
The combination of Kim, Zhu, Huang, and Kim '693 disclose a semiconductor device according to claim 17, but neither Kim, Huang, nor Kim '683 explicitly teach where an upper surface of a back-side and front-side key pattern contacts a lower surface of the first upper interlayer insulating layer.
Zhu discloses an analogous semiconductor structure (Fig. 12), wherein an upper surface of the back-side key pattern (first end surface; Fig. 12 element 14') contacts a lower surface of the first upper interlayer insulating layer (element 48, paragraphs 41 and 46), and
an upper surface of the front-side key pattern (first end surface; Fig. 12 element 12') contacts the lower surface of the first upper interlayer insulating layer (element 48, paragraphs 41 and 46).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure described in Kim, Huang, and Kim '683 further in view of Zhu to include an upper surface of a back-side and front-side key patterns in contact with a lower surface of the first upper interlayer insulating layer because all are directed to analogous semiconductor devices. Doing so improves the accuracy and efficiency of the alignment process (Zhu, paragraphs 5-6 and 18).
The applied references have a common assignee with the instant application. Based upon the earlier effectively filed date of the references, it constitutes prior art under 35 U.S.C. 102(a)(2). Based upon the earlier publication date of the references, it constitutes as prior art under 35 U.S.C. 102(a)(1).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jin et al. (US 11437378 B2), Oyu et al. (US 20120199916 A1), Sharma et al. (US 20240006416 A1), Jung et al. (US 20200027992 A1), Anderson et al. (US 20240006313 A1), Herrin et al. (US 20110177435 A1), Jeong et al. (US 20210183859 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST.
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/Chloë E Benton/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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