DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
Claim 20 is rejected under 35 U.S.C. 101 because 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claim 20 are rejected because the claimed invention, appearing to be comprised of software alone without claiming associated computer hardware required for execution, is not supported by either a specific and substantial asserted utility (i.e., transformation of data) or a well established utility (i.e. a practical application).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Krueger (US PG Pub No. 2018/0203638 A1).
Krueger was disclosed in IDS dated 08/11/2025.
Regarding claim 1, Krueger teaches an apparatus comprising:
a requesting processing element (par [0046], Fig 1, ref 6) configured to issue a storage transaction in response to a storage access request from a process running on the requesting processing element, the process associated with an identifier (par [0048], par [0053], Fig 2, ref 30 and "Each of these software execution environments can be allocated a given partition identifier (partition ID or PARTID)", par [0060], Fig 5 and par [0185]); and
regulation circuitry ("Memory transaction progression control circuitry then controls progression of the memory transaction based on the partition identifier by selecting memory transaction progression parameters (also referred to as "memory system component partitioning control settings") associated with the transaction identifier.", par [0185]) configured to control a bandwidth utilisation available to storage transactions requested by processes associated with the identifier ("when said current bandwidth usage is between said lower limit and said higher limit, said memory transaction routing control circuitry sets a preference of said transactions specifying said given partition identifier to a second level, of lower importance than said first level; and when said current bandwidth usage is above said upper limit, said memory transaction routing control circuitry sets a preference of said transactions specifying said given partition identifier to a third level, of lower importance than said second level.", par [0195]), wherein when operating in at least one mode the regulation circuitry is configured to control the bandwidth utilisation, based on a transaction feedback signal issued by circuitry other than the requesting processing element and indicative of a resource utilisation parameter ("FIG. 19 shows a memory system component 372, in this case an interconnect, using one or more buffers 374, 376 for memory transactions. Transactions in the queue are stalled or blocked if the transaction at the front of the queue is unable to be transmitted to the slave due to that slave being busy (potentially engaged in another transaction from another master). For example, the front transaction in the buffer 374 of master 1 is directed to slave S1. However, if S1 is busy, then the transaction cannot proceed and so other transactions in that buffer 374 will be blocked. Meanwhile, the transaction in the front of the buffer 376 associated with the second master M2 may be able to proceed. In this embodiment, the masters are processors, each of which provides multiple execution environments. Each execution environment is associated with a partition, and the partitions have an associated buffer depth limit. Also in this embodiment, master 1 is shown to execute a non-blocking transaction 378 directed towards S1.", par [0205], Fig 19):
when the resource utilisation parameter satisfies a resource utilisation condition, to apply a control to restrict the bandwidth utilisation to a predefined limit assigned to the identifier ("bandwidth limit said memory transaction routing control circuitry sets a preference of said transactions, par [0195] and "Also in this embodiment, master 1 is shown to execute a non-blocking transaction 378 directed towards S1. In this embodiment, a non-blocking transaction is such that it always moves to the front of the buffer and also cause blocking transactions to be cancelled so that it can proceed immediately without being blocked. The number of non-blocking transactions that can be issued in respect of each partition is another example of a limit that can be associated with each partition.", par [0205]); and
when the resource utilisation parameter does not satisfy the resource utilisation condition, to apply a modification to the control based on the resource utilisation parameter ("However, if S1 is busy, then the transaction cannot proceed and so other transactions in that buffer 374 will be blocked. Meanwhile, the transaction in the front of the buffer 376 associated with the second master M2 may be able to proceed.", par [0205]).
Regarding claim 2, Krueger teaches wherein the resource utilisation parameter indicates utilisation of resources by processes associated with the identifier ("Each execution environment is associated with a partition, and the partitions have an associated buffer depth limit.", par [0205], Fig 19).
Regarding claim 3, Krueger teaches wherein the resource utilisation parameter comprises an indication of utilisation of resources other than the requesting processing element ("For example, the front transaction in the buffer 374 of master 1 is directed to slave S1. However, if S1 is busy, then the transaction cannot proceed and so other transactions in that buffer 374 will be blocked.", par [0205]).
Regarding claim 4, Krueger teaches wherein the resource utilisation parameter comprises processing element identifying information ("In this embodiment, the masters are processors, each of which provides multiple execution environments. Each execution environment is associated with a partition, and the partitions have an associated buffer depth limit.", par [0205]) indicative of processing elements running processes associated with the identifier (Fig 2, Fig 5), and the resource utilisation condition comprises a processing element condition satisfied when the requesting processing element is the only processing element identified as running processes associated with the identifier (Fig 2, Fig 5).
Regarding claim 7, Krueger teaches interconnect circuitry (par [0205], Fig 19) configured to store processing element utilisation information indicative of a number of processing elements issuing transaction requests associated with the identifier wherein the interconnect is configured to issue the feedback signal indicating the number of processing elements ("Each execution environment is associated with a partition, and the partitions have an associated buffer depth limit. par [0205]).
Regarding claim 8, Krueger teaches wherein the interconnect is configured to apply an aging mechanism to the processing element utilisation information (par [0199]).
Regarding claim 9, Krueger teaches wherein the aging mechanism comprises storing the processing element utilisation information over a sliding window (par [0199]).
Regarding claim 10, Krueger teaches wherein the resource utilisation parameter comprises a congestion parameter indicative of congestion of storage requests and the resource utilisation condition comprises a congestion condition satisfied when the congestion parameter exceeds a congestion threshold ("However, if S1 is busy, then the transaction cannot proceed Each execution environment is associated with a partition, and the partitions have an associated buffer depth limit.", par [0205], Fig 19).
Regarding claim 11, Krueger teaches wherein the restriction circuitry is configured, when applying the modification, to allow the processing element to issue requests at a rate greater than the predefined limit ("Meanwhile, the transaction in the front of the buffer 376 associated with the second master M2 may be able to proceed.", par [0205], Fig 19).
Regarding claim 12, Krueger teaches wherein the restriction circuitry is configured, when applying the modification, to apply a soft limit to the bandwidth utilisation, the soft limit allowing the bandwidth utilisation to exceed the predefined limit ("Meanwhile, the transaction in the front of the buffer 376 associated with the second master M2 may be able to proceed.", par [0205], Fig 19).
Regarding claim 13, Krueger teaches wherein the utilisation parameter is issued by a storage hierarchy ("Downstream priorities control priorities communicated downstream to another memory system component (for example to an interconnect or memory controller). "Downstream" refers to the communication direction for requests.", par [0182], par [0188]).
Regarding claim 14, Krueger teaches one or more software accessible registers, wherein the predefined limit is stored in the one or more registers (par [0143], Fig 13, ref 320).
Regarding claim 15, Krueger teaches wherein the identifier is one of a plurality of identifiers, each assignable to one or more processes and the predefined limit is set on a per identifier basis (par [0143], Fig 13, ref 320).
Regarding claim 16, Krueger teaches wherein the requesting processing element is operable in a further mode in which the regulation circuitry is configured to restrict the bandwidth utilisation to the predefined limit independent of the transaction feedback signal (par [0206]).
Regarding claim 17, Krueger teaches wherein the requesting processing element is configured to stall execution of the process in response to the one or more limits being met (par [0206]).
Regarding claim 18, Krueger teaches wherein the identifier (par [0152]) associated with the process (Fig 2, ref 30) is defined in a software-configurable register ([0054-55]).
Regarding claims 19-20, they are the method and computer program claims of claim 1 above. Therefore, they are rejected for the same reasons as claim 1 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krueger (US PG Pub No. 2018/0203638 A1).
Regarding claim 5, Krueger teaches wherein the processing element identifying information ("In this embodiment, the masters are processors, each of which provides multiple execution environments. Each execution environment is associated with a partition, and the partitions have an associated buffer depth limit.", par [0205]) indicates a number of processing elements running processes associated with the identifier (Fig 2, Fig 5).
Krueger does not explicitly teach the modification comprises restricting the bandwidth utilisation to a reduced limit based on the number of processing elements. Krueger provides for some use cases where multiple requesting processing elements are identified as running processes associated with the identifier and thus the bandwidth is shared. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to restrict the bandwidth utilisation to a reduced limit based on the number of processing elements. One would be motivated by the desire to limit this bandwidth as a function of the number of processing elements running processes associated with the identifier if each of the processes require the same priority.
Regarding claim 6, Krueger does not explicitly teach wherein the reduced limit is calculated by dividing the bandwidth utilisation limit by the number of processing elements running processes associated with the identifier.
Krueger does not explicitly teach the modification comprises restricting the bandwidth utilisation to a reduced limit based on the number of processing elements. Krueger provides for some use cases where multiple requesting processing elements are identified as running processes associated with the identifier and thus the bandwidth is shared. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to restrict the bandwidth utilisation to a reduced limit based on the number of processing elements. One would be motivated by the desire to limit this bandwidth as a function of the number of processing elements running processes associated with the identifier if each of the processes require the same priority.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC C WAI whose telephone number is (571)270-1012. The examiner can normally be reached Monday - Friday 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Eric C Wai/Primary Examiner, Art Unit 2195
Prosecution Insights