DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1st Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 3, 4, 9, 10, 11, 12, 13, 18, 19, and 20 are rejected under 35 U.S.C. 103 as obvious over US Patent Publication 2025 0391012 A1, (Vega Martίnez et al.) in view of US Patent Publication 2023 0385507 A1, (Zhu et al.).
Claim 1
Regarding claim 1, Vega Martίnez et al. teach a computer-implemented method of analyzing a particular computing product, including: receiving a plurality of images of a particular layout of the particular computing product; ("The system 100 comprises an image sensor configured to obtain a first image of at least a portion of the supporting region 151," par. 57) ("The auxiliary frame 150 comprises a supporting region 151 configured to support the printed circuit board 10 and/or electronic components," par. 53) segmenting, using a classification model, the plurality of images to identify computing components of the particular computing product; ("The input of the third neural network may comprise the second image and the output may comprise segmentations of elements of interest. Elements of interest may comprise the printed circuit board and/or electronic components mounted on the board or in a tray," par. 114) analyzing the particular layout, including, for each computing component of the particular layout: ("the controller may be configured to compute the layout of the printed circuit board from the output of the first neural network and determine a test to be performed on the printed circuit board 10 by comparing the layout of the printed circuit board with pre-determined layouts and associated tests," par. 65) identifying a predetermined layout weight of the computing component; ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65) calculating a computing component score for the computing component for the particular layout based on ii) the predetermined layout weight of the computing component ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65).
Vega Martίnez et al. do not explicitly teach all of approximating a physical size of the computing component; determining a proximity of the component to each other computing component; calculating a computing component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; and determining a layout score of the particular layout based on the computing component score of each of the computing components.
However, Zhu et al. teach approximating a physical size of the computing component; ("The size parameter refers to the component size," par. 42) determining a proximity of the component to each other computing component; ("The group scheme parameter determines whether certain components are grouped together to obtain better placement results," par. 43) calculating a computing component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining a layout score of the particular layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34) based on the computing component score of each of the computing components ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores," par. 42).
Therefore, taking the teachings of Vega Martίnez et al. and Zhu et al. as a whole, it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention of the instant application to modify electronic component detection method as taught by Vega Martίnez et al. to use the parameter scoring and global placement model as taught by Zhu et al. The suggestion/motivation for doing so would have been that, “The methods 70 and/or 71 (FIG. 5A) therefore enhance performance at least to the extent that generating the global placement model based on the aggregated parameter results and scores is faster than manual placement” as noted by the Zhu et al. disclosure in paragraph [0045], which also motivates combination because the combination would predictably have a higher productivity as there is a reasonable expectation that aggregating the parameter results and scores would provide a more precise and optimized global placement, resulting in reduced manual intervention and enhanced accuracy of the electronic component detection; and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
The rejection of method claim 1 above applies mutatis mutandis to the corresponding limitations of system claim 10 and non-transitory computer-readable medium claim 19 while noting that the rejection above cites to both system and non-transitory computer-readable medium disclosures. Claims 10 and 19 are mapped below for clarity of the record and to specify any new limitations not included in claim 1.
Claim 2
Regarding claim 2, Vega Martίnez et al. and Zhu et al. teach the computer-implemented method of claim 1 as noted above.
Vega Martίnez et al. teach calculating an updated computing component score for the computing component for the permutated layout based ii) the predetermined layout weight of the computing component ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65).
Vega Martίnez et al. do not explicitly teach all of identifying, from a data store, physical constraints associated with the computing components of the particular computing product; iteratively permutating, based on the physical constraints associated with the computing components of the particular computing product, the particular layout to define a plurality of permutated layouts of the particular computing product; for each of the permutated layouts: analyzing the permutated layout, including, for each computing component: determining an updated proximity of the computing component to each other computing component; calculating an updated computing component score for the computing component for the permutated layout based on i) the physical size of the computing component and iii) the updated proximity of the computing component to each other computing component; and determining an updated layout score of the permutated layout based on the updated computing component score of each of the computing components.
However, Zhu et al. teach identifying, from a data store, physical constraints associated with the computing components of the particular computing product; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area," par. 42) iteratively permutating, based on the physical constraints associated with the computing components of the particular computing product, the particular layout to define a plurality of permutated layouts of the particular computing product; ("Block 75 conducts the one or more placements of the subcircuit in the bounded area with the received one or more parameters to obtain one or more parameterized placements.," par. 40) for each of the permutated layouts: analyzing the permutated layout, including, for each computing component: ("Block 77 conducts score collections for the parameterized placements. In one example, the score collections are parameterized score collections," par. 40) determining an updated proximity of the computing component to each other computing component; ("The local fine tune parameter fine tunes the locations of each component to obtain better placement results," par. 43) calculating an updated computing component score for the computing component for the permutated layout based on i) the physical size of the computing component and iii) the updated proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining an updated layout score of the permutated layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34 wherein placement is the layout) based on the updated computing component score of each of the computing components ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores," par. 42).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 3
Regarding claim 3, Vega Martίnez et al. and Zhu et al. teach the computer-implemented method of claim 2 as noted above.
Vega Martίnez et al. do not explicitly teach all of determining, from the updated layout score for each of the permutated layouts, a greatest layout score; and generating the permutated layout associated with the greatest layout score for the particular computing product.
However, Zhu et al. teach determining, from the updated layout score for each of the permutated layouts, a greatest layout score; ("the local rating sessions 50 may be conducted for a plurality of entities (e.g., with each entity including one or more users). Each local rating session 50 has full access to all placement information and the user can repetitively rate placements to train the learning procedure," par. 31) and generating the permutated layout associated with the greatest layout score for the particular computing product ("If the exit condition has not been satisfied, the method 70 returns to block 74 (e.g., for a new user/entity). Otherwise, block 80 generates a global placement model based on the aggregated parameter results and scores," par. 44).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 4
Regarding claim 4, Vega Martίnez et al. and Zhu et al. teach the computer-implemented method of claim 1 as noted above.
Vega Martίnez et al. teach receiving a training set of images of an additional particular layout of an additional particular computing product; ("The method 700 may comprise training the first neural network with a set of training first images with an associated classification label," par. 117) and training, based on the training set of images, the classification model, including generating rules for segmenting the training set of images to identify computing components of the additional particular computing product ("The first neural network may be trained with a set of training first copies. This way, the first neural network may be more flexible to multiple pixel density values. In each training first copy, an electronic component is classified and located for a particular pixel density value," par. 117).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 9
Regarding claim 9, Vega Martίnez et al. and Zhu et al. teach the computer-implemented method of claim 2 as noted above.
Vega Martίnez et al. do not explicitly teach all of updating, for each of the permutated layouts, an index indicating the updated layout score of the permutated layout.
However, Zhu et al. teach updating, for each of the permutated layouts, an index indicating the updated layout score of the permutated layout ("A federated learning approach can be applied to aggregate the “results” (e.g., the user-ranked scores) from local learning sessions. Since the results from local learning are purely parameters (e.g., design information and/or layout information is excluded), those results can used to build a global parameter/scoring model that can be distributed back to the entire user base," par. 37).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 10
Regarding claim 10, Vega Martίnez et al. receiving a plurality of images of a particular layout of the particular computing product; ("The system 100 comprises an image sensor configured to obtain a first image of at least a portion of the supporting region 151," par. 57) ("The auxiliary frame 150 comprises a supporting region 151 configured to support the printed circuit board 10 and/or electronic components," par. 53) segmenting, using a classification model, the plurality of images to identify computing components of the particular computing product; ("The input of the third neural network may comprise the second image and the output may comprise segmentations of elements of interest. Elements of interest may comprise the printed circuit board and/or electronic components mounted on the board or in a tray," par. 114) analyzing the particular layout, including, for each computing component of the particular layout: ("the controller may be configured to compute the layout of the printed circuit board from the output of the first neural network and determine a test to be performed on the printed circuit board 10 by comparing the layout of the printed circuit board with pre-determined layouts and associated tests," par. 65) identifying a predetermined layout weight of the computing component; ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65) calculating a computing component score for the computing component for the particular layout based on ii) the predetermined layout weight of the computing component ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65).
Vega Martίnez et al. do not explicitly teach all of an information handling system comprising a processor having access to memory media storing instructions executable by the processor to perform operations, comprising: approximating a physical size of the computing component; determining a proximity of the component to each other computing component; calculating a computing component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; and determining a layout score of the particular layout based on the computing component score of each of the computing components.
However, Zhu et al. teach an information handling system comprising a processor having access to memory media storing instructions executable by the processor to perform operations, comprising: ("the host processor 282 execute instructions 300 retrieved from the system memory 286 and/or the mass storage 302 to perform one or more aspects of the placement flow," par. 52) approximating a physical size of the computing component; ("The size parameter refers to the component size," par. 42) determining a proximity of the component to each other computing component; ("The group scheme parameter determines whether certain components are grouped together to obtain better placement results," par. 43) calculating a computing component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining a layout score of the particular layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34) based on the computing component score of each of the computing components ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores," par. 42).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 11
Regarding claim 11, Vega Martίnez et al. and Zhu et al. teach the information handling system of claim 10 as noted above.
Vega Martίnez et al. teach calculating an updated computing component score for the computing component for the permutated layout based ii) the predetermined layout weight of the computing component ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65).
Vega Martίnez et al. do not explicitly teach all of identifying, from a data store, physical constraints associated with the computing components of the particular computing product; iteratively permutating, based on the physical constraints associated with the computing components of the particular computing product, the particular layout to define a plurality of permutated layouts of the particular computing product; for each of the permutated layouts: analyzing the permutated layout, including, for each computing component: determining an updated proximity of the computing component to each other computing component; calculating an updated computing component score for the computing component for the permutated layout based on i) the physical size of the computing component and iii) the updated proximity of the computing component to each other computing component; and determining an updated layout score of the permutated layout based on the updated computing component score of each of the computing components.
However, Zhu et al. teach identifying, from a data store, physical constraints associated with the computing components of the particular computing product; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area," par. 42) iteratively permutating, based on the physical constraints associated with the computing components of the particular computing product, the particular layout to define a plurality of permutated layouts of the particular computing product; ("Block 75 conducts the one or more placements of the subcircuit in the bounded area with the received one or more parameters to obtain one or more parameterized placements.," par. 40) for each of the permutated layouts: analyzing the permutated layout, including, for each computing component: ("Block 77 conducts score collections for the parameterized placements. In one example, the score collections are parameterized score collections," par. 40) determining an updated proximity of the computing component to each other computing component; ("The local fine tune parameter fine tunes the locations of each component to obtain better placement results," par. 43) calculating an updated computing component score for the computing component for the permutated layout based on i) the physical size of the computing component and iii) the updated proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining an updated layout score of the permutated layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34 wherein placement is the layout) based on the updated computing component score of each of the computing components ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores," par. 42).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 12
Regarding claim 12, Vega Martίnez et al. and Zhu et al. teach the information handling system of claim 11 as noted above.
Vega Martίnez et al. do not explicitly teach all of determining, from the updated layout score for each of the permutated layouts, a greatest layout score; and generating the permutated layout associated with the greatest layout score for the particular computing product.
However, Zhu et al. teach determining, from the updated layout score for each of the permutated layouts, a greatest layout score; ("the local rating sessions 50 may be conducted for a plurality of entities (e.g., with each entity including one or more users). Each local rating session 50 has full access to all placement information and the user can repetitively rate placements to train the learning procedure," par. 31) and generating the permutated layout associated with the greatest layout score for the particular computing product ("If the exit condition has not been satisfied, the method 70 returns to block 74 (e.g., for a new user/entity). Otherwise, block 80 generates a global placement model based on the aggregated parameter results and scores," par. 44).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 13
Regarding claim 13, Vega Martίnez et al. and Zhu et al. teach the information handling system of claim 10 as noted above.
Vega Martίnez et al. teach receiving a training set of images of an additional particular layout of an additional particular computing product; ("The method 700 may comprise training the first neural network with a set of training first images with an associated classification label," par. 117) and training, based on the training set of images, the classification model, including generating rules for segmenting the training set of images to identify computing components of the additional particular computing product ("The first neural network may be trained with a set of training first copies. This way, the first neural network may be more flexible to multiple pixel density values. In each training first copy, an electronic component is classified and located for a particular pixel density value," par. 117).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 18
Regarding claim 18, Vega Martίnez et al. and Zhu et al. teach the information handling system of claim 11 as noted above.
Vega Martίnez et al. do not explicitly teach all of updating, for each of the permutated layouts, an index indicating the updated layout score of the permutated layout.
However, Zhu et al. teach updating, for each of the permutated layouts, an index indicating the updated layout score of the permutated layout ("A federated learning approach can be applied to aggregate the “results” (e.g., the user-ranked scores) from local learning sessions. Since the results from local learning are purely parameters (e.g., design information and/or layout information is excluded), those results can used to build a global parameter/scoring model that can be distributed back to the entire user base," par. 37).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 19
Regarding claim 19, Vega Martίnez et al. teach a non-transitory computer-readable medium storing software comprising instructions executable by one or more computers which, upon such execution, cause the one or more computers to perform operations comprising: ("The controller 690 may be a processor, a chip, a computational device or processing resources that executes sequences of machine-readable instructions contained in a memory," par. 99) receiving a plurality of images of a particular layout of the particular computing product; ("The system 100 comprises an image sensor configured to obtain a first image of at least a portion of the supporting region 151," par. 57) ("The auxiliary frame 150 comprises a supporting region 151 configured to support the printed circuit board 10 and/or electronic components," par. 53) segmenting, using a classification model, the plurality of images to identify computing components of the particular computing product; ("The input of the third neural network may comprise the second image and the output may comprise segmentations of elements of interest. Elements of interest may comprise the printed circuit board and/or electronic components mounted on the board or in a tray," par. 114) analyzing the particular layout, including, for each computing component of the particular layout: ("the controller may be configured to compute the layout of the printed circuit board from the output of the first neural network and determine a test to be performed on the printed circuit board 10 by comparing the layout of the printed circuit board with pre-determined layouts and associated tests," par. 65) identifying a predetermined layout weight of the computing component; ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65) calculating a computing component score for the computing component for the particular layout based on ii) the predetermined layout weight of the computing component ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65).
Vega Martίnez et al. do not explicitly teach all of approximating a physical size of the computing component; determining a proximity of the component to each other computing component; calculating a computing component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; and determining a layout score of the particular layout based on the computing component score of each of the computing components.
However, Zhu et al. teach approximating a physical size of the computing component; ("The size parameter refers to the component size," par. 42) determining a proximity of the component to each other computing component; ("The group scheme parameter determines whether certain components are grouped together to obtain better placement results," par. 43) calculating a computing component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining a layout score of the particular layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34) based on the computing component score of each of the computing components ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores," par. 42).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
Claim 20
Regarding claim 20, Vega Martίnez et al. and Zhu et al. teach the non-transitory computer-readable medium of claim 19 as noted above.
Vega Martίnez et al. teach calculating an updated computing component score for the computing component for the permutated layout based ii) the predetermined layout weight of the computing component ("The controller may compare the with a list of predetermined layouts and computing a similarity score," par. 65).
Vega Martίnez et al. do not explicitly teach all of identifying, from a data store, physical constraints associated with the computing components of the particular computing product; iteratively permutating, based on the physical constraints associated with the computing components of the particular computing product, the particular layout to define a plurality of permutated layouts of the particular computing product; for each of the permutated layouts: analyzing the permutated layout, including, for each computing component: determining an updated proximity of the computing component to each other computing component; calculating an updated computing component score for the computing component for the permutated layout based on i) the physical size of the computing component and iii) the updated proximity of the computing component to each other computing component; and determining an updated layout score of the permutated layout based on the updated computing component score of each of the computing components.
However, Zhu et al. teach identifying, from a data store, physical constraints associated with the computing components of the particular computing product; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area," par. 42) iteratively permutating, based on the physical constraints associated with the computing components of the particular computing product, the particular layout to define a plurality of permutated layouts of the particular computing product; ("Block 75 conducts the one or more placements of the subcircuit in the bounded area with the received one or more parameters to obtain one or more parameterized placements.," par. 40) for each of the permutated layouts: analyzing the permutated layout, including, for each computing component: ("Block 77 conducts score collections for the parameterized placements. In one example, the score collections are parameterized score collections," par. 40) determining an updated proximity of the computing component to each other computing component; ("The local fine tune parameter fine tunes the locations of each component to obtain better placement results," par. 43) calculating an updated computing component score for the computing component for the permutated layout based on i) the physical size of the computing component and iii) the updated proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining an updated layout score of the permutated layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34 wherein placement is the layout) based on the updated computing component score of each of the computing components ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores," par. 42).
Vega Martίnez et al. and Zhu et al. are combined as per claim 1.
2nd Claim Rejections - 35 USC § 103
Claims 5, 6, 14, and 15 are rejected under 35 U.S.C. 103 as obvious over US Patent Publication 2025 0391012 A1, (Vega Martίnez et al.) and US Patent Publication 2023 0385507 A1, (Zhu et al.) in view of US Patent Publication 2021 0089364 A1, (Blankenburg et al.).
Claim 5
Regarding claim 5, Vega Martίnez et al. and Zhu et al. teach the computer-implemented method of claim 1 as noted above.
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of wherein the predetermined layout weight is a thermal weight of the computing component.
However, Blankenburg et al. teach wherein the predetermined layout weight is a thermal weight of the computing component ("These thresholds can be used to bin or sort each computing module according to predetermined power consumption ranges (such as indicated for the ‘bin’ column that corresponds to normalized high, medium, and low TDP metrics)," par. 39).
Therefore, taking the teachings of Vega Martίnez et al., Zhu et al., and Blankenburg et al. as a whole, it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention of the instant application to modify electronic component detection method as taught by Vega Martίnez et al. and the parameter scoring and global placement model as taught by Zhu et al. to use computing module power consumption characterization as taught by Blankenburg et al. The suggestion/motivation for doing so would have been that, “Since power efficiency of each computing module can vary according to manufacturing, assembly, and component selections, this characterization process can lead to more effective and accurate power limits for each computing module” as noted by the Blankenburg et al. disclosure in paragraph [0039], which also motivates combination because the combination would predictably have a power efficiency as there is a reasonable expectation that incorporating specific, measured power characterization data into the modeling process would improve the accuracy of the power limits; and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
Claim 6
Regarding claim 6, Vega Martίnez et al., Zhu et al., and Blankenburg et al. teach the computer-implemented method of claim 5 as noted above.
Zhu et al. teach for each computing component of the particular layout: calculating a thermal component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; and determining a thermal layout score of the particular layout.
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of ii) the thermal weight of the computing component and the thermal component score of each of the computing components.
However, Blankenburg et al. teach ii) the thermal weight of the computing component and the thermal component score of each of the computing components ("These thresholds can be used to bin or sort each computing module according to predetermined power consumption ranges (such as indicated for the ‘bin’ column that corresponds to normalized high, medium, and low TDP metrics)," par. 39).
Vega Martίnez et al., Zhu et al., and Blankenburg et al. are combined as per claim 5.
Claim 14
Regarding claim 14, Vega Martίnez et al. and Zhu et al. teach the information handling system of claim 10 as noted above.
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of ("These thresholds can be used to bin or sort each computing module according to predetermined power consumption ranges (such as indicated for the ‘bin’ column that corresponds to normalized high, medium, and low TDP metrics)," par. 39)
However, Blankenburg et al. teach ("These thresholds can be used to bin or sort each computing module according to predetermined power consumption ranges (such as indicated for the ‘bin’ column that corresponds to normalized high, medium, and low TDP metrics)," par. 39)
Vega Martίnez et al., Zhu et al., and Blankenburg et al. are combined as per claim 5.
Claim 15
Regarding claim 15, Vega Martίnez et al., Zhu et al., and Blankenburg et al. teach the information handling system of claim 14 as noted above.
Zhu et al. teach for each computing component of the particular layout: calculating a thermal component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; and determining a thermal layout score of the particular layout.
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of ii) the thermal weight of the computing component and the thermal component score of each of the computing components.
However, Blankenburg et al. teach ii) the thermal weight of the computing component and the thermal component score of each of the computing components ("These thresholds can be used to bin or sort each computing module according to predetermined power consumption ranges (such as indicated for the ‘bin’ column that corresponds to normalized high, medium, and low TDP metrics)," par. 39).
Vega Martίnez et al., Zhu et al., and Blankenburg et al. are combined as per claim 5.
3rd Claim Rejections - 35 USC § 103
Claims 7, 8, 16, and 17 are rejected under 35 U.S.C. 103 as obvious over US Patent Publication 2025 0391012 A1, (Vega Martίnez et al.) and US Patent Publication 2023 0385507 A1, (Zhu et al.) in view of US Patent Publication 2012 0281443 A1, (Wolf et al.).
Claim 7
Regarding claim 7, Vega Martίnez et al. and Zhu et al. teach the computer-implemented method of claim 1 as noted above.
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of wherein the predetermined layout weight is a signal integrity (SI) weight of the computing component.
However, Wolf et al. teach wherein the predetermined layout weight is a signal integrity (SI) weight of the computing component ("the comparator provides in one embodiment a signal signaling whether a difference between the two electric potentials exceeds a predetermined threshold value. This threshold value is suitably predetermined in such a way that it is in only exceeded with a failure of one of the capacitors," par. 28).
Therefore, taking the teachings of Vega Martίnez et al., Zhu et al., and Wolf et al. as a whole, it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date of the claimed invention of the instant application to modify electronic component detection method as taught by Vega Martίnez et al. and the parameter scoring and global placement model as taught by Zhu et al. to use computing module electric signal monitoring as taught by Wolf et al. The suggestion/motivation for doing so would have been that, “the reduced current load to the plurality of capacitors reduces the stress to the remaining capacitors, i.e. to those capacitors not having lost their integrity which now have to bear the entire voltage drop over the plurality of capacitors” as noted by the Wolf et al. disclosure in paragraph [0021], which also motivates combination because the combination would predictably have a higher efficiency as there is a reasonable expectation that computing components that have lost their integrity will more likely be detected; and/or because doing so merely combines prior art elements according to known methods to yield predictable results.
Claim 8
Regarding claim 8, Vega Martίnez et al., Zhu et al., and Wolf et al. teach the computer-implemented method of claim 7 as noted above.
Zhu et al. teach for each computing component of the particular layout: calculating an SI component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining an SI layout score of the particular layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34 wherein placement is the layout).
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of ii) the SI weight of the computing component and the SI component score of each of the computing components.
However, Wolf et al. teach ii) the SI weight of the computing component and the SI component score of each of the computing components ("the comparator provides in one embodiment a signal signaling whether a difference between the two electric potentials exceeds a predetermined threshold value. This threshold value is suitably predetermined in such a way that it is in only exceeded with a failure of one of the capacitors," par. 28).
Vega Martίnez et al., Zhu et al., and Wolf et al. are combined as per claim 7.
Claim 16
Regarding claim 16, Vega Martίnez et al. and Zhu et al. teach the information handling system of claim 10 as noted above.
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of wherein the predetermined layout weight is a signal integrity (SI) weight of the computing component.
However, Wolf et al. teach wherein the predetermined layout weight is a signal integrity (SI) weight of the computing component ("the comparator provides in one embodiment a signal signaling whether a difference between the two electric potentials exceeds a predetermined threshold value. This threshold value is suitably predetermined in such a way that it is in only exceeded with a failure of one of the capacitors," par. 28).
Vega Martίnez et al., Zhu et al., and Wolf et al. are combined as per claim 7.
Claim 17
Regarding claim 17, Vega Martίnez et al., Zhu et al., and Wolf et al. teach the information handling system of claim 16 as noted above.
Zhu et al. teach for each computing component of the particular layout: calculating an SI component score for the computing component for the particular layout based on i) the physical size of the computing component and iii) the proximity of the computing component to each other computing component; ("block 74 receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area and block 76 aggregates the parameter results and scores … the aggregated parameter results may include, for example, a circuit rotation parameter, a recenter procedure parameter, a complexity order parameter, a size parameter, a pin location parameter, a group scheme parameter," par. 42) and determining an SI layout score of the particular layout ("Build a model to score the placement more in line with user preferences compared to the heuristic-based scoring, ignoring user preference/differences," par. 34 wherein placement is the layout).
Vega Martίnez et al. and Zhu et al. do not explicitly teach all of ii) the SI weight of the computing component and the SI component score of each of the computing components.
However, Wolf et al. teach ii) the SI weight of the computing component and the SI component score of each of the computing components ("the comparator provides in one embodiment a signal signaling whether a difference between the two electric potentials exceeds a predetermined threshold value. This threshold value is suitably predetermined in such a way that it is in only exceeded with a failure of one of the capacitors," par. 28).
Vega Martίnez et al., Zhu et al., and Wolf et al. are combined as per claim 7.
Reference Cited
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
US Patent Publication 2017 0242953 A1 to Pikus discloses determining patterning scores for patterning clusters in circuit layout design data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KARSTEN F LANTZ whose telephone number is (571) 272-4564. The examiner can normally be reached Monday-Friday 8:00-4:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Jennifer Mehmood can be reached on 571-272-2976. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Karsten F. Lantz/Examiner, Art Unit 2664
Date: 2/26/2026
/JENNIFER MEHMOOD/Supervisory Patent Examiner, Art Unit 2664