CTNF 18/647,354 CTNF 101710 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-08 AIA Restriction to one of the following inventions is required under 35 U.S.C. 121: I. Claim s 1-14 , drawn to a semiconductor memory device , classified in H10B 43/10 . II. Claim s 15-20 , drawn to a process of manufacturing a semiconductor memory device , classified in H10W 20/01 . 08-13 AIA The inventions are independent or distinct, each from the other because: 08-18 AIA Inventions II and I are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the product can be made through a different process, namely one in which the CMOS device is directly fabricated over the memory device, rather than fabricated separately and bonded to the memory device . Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: The inventions have acquired a separate status in the art due to their recognized divergent subject matter; The inventions each require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); The prior art applicable to one invention may not be applicable to another invention . 18-22 AIA Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention . The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. 08-21-04 AIA The examiner has required restriction between product or apparatus claims and process claims. Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined. In the event of rejoinder, the requirement for restriction between the product/apparatus claims and the rejoined process claims will be withdrawn, and the rejoined process claims will be fully examined for patentability in accordance with 37 CFR 1.104. Thus, to be allowable, the rejoined claims must meet all criteria for patentability including the requirements of 35 U.S.C. 101, 102, 103 and 112. Until all claims to the elected product/apparatus are found allowable, an otherwise proper restriction requirement between product/apparatus claims and process claims may be maintained. Withdrawn process claims that are not commensurate in scope with an allowable product/apparatus claim will not be rejoined. See MPEP § 821.04. Additionally, in order for rejoinder to occur, applicant is advised that the process claims should be amended during prosecution to require the limitations of the product/apparatus claims. Failure to do so may result in no rejoinder. Further, note that the prohibition against double patenting rejections of 35 U.S.C. 121 does not apply where the restriction requirement is withdrawn by the examiner before the patent issues. See MPEP § 804.01. 08-23 AIA During a telephone conversation with Joshua Nelson on May 27, 2026 , a provisional election was made without traverse to prosecute the invention of the semiconductor memory device , claim s 1-14 . Affirmation of this election must be made by applicant in replying to this Office action. Claim s 15-20 withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention. Specification The abstract of the disclosure is objected to because "a substrate". A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). 07-29 AIA The disclosure is objected to because of the following informalities: In paragraph [0014], “utilizes” should be “utilize”. In paragraph [0017], “bit lines 122” was likely meant to be “bit lines 112”. In paragraph [0021], “contracts 212” should be “contacts 212” . Appropriate correction is required. Claim Objections 07-29-01 AIA Claim s 4-5 and 12-14 are objected to because of the following informalities: In claim 4, line 2, “at edge region” should read “at an edge region”. In claim 5, line 5, “at edge region” should read “at an edge region”. In claim 12, line 3, “at edge region” should read “at an edge region”. In claim 13, line 4, “at edge region” should read “at an edge region”. Claim 13 recites the limitation, “wherein the group of the one or more HV diodes are surrounded by a corresponding highly doped region”, which is redundant, as claim 11 recites substantially the same limitation. In claim 14, line 2, “diode” should be “diodes” . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 5, 8, 10, and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation, “ the one corresponding HV diode having a dimension, in a horizontal plane, similar to the each of the one or more memory planes ” (emphasis added by the examiner). It is unclear which dimensions of the HV diode or the memory plane are being referred to, or what is meant by “similar” (i.e., within what percentage) in this context. Claim 8 recites the limitation, “ a backside surface ”. However, claim 1, which claim 8 is dependent on, already recites “ a backside surface ”, rendering the limitation redundant and introducing uncertainty over whether the backside surface recited in claim 8 is the same as that recited in claim 1 or a different backside surface. Claim 10 recites the limitation, “ the transitional regions ”. There is insufficient antecedent basis for this limitation. Claim 14 recites the limitation, “ wherein each of the plurality of highly doped regions and corresponding HV diode are separated by a threshold distance of 1um to 10um ”. However, claim 11, which claim 14 is dependent on, recites the limitation, “ and a plurality of highly doped regions that are disposed in the substrate, each surrounding one or more corresponding HV diodes ”. These limitations appear to be contradictory, as it is unclear how the highly doped regions can surround the HV diodes and simultaneously be spaced apart from them. Claim 18 recites the limitation, “ a second type dopant material ”. However, claim 15, which claim 18 is dependent on, already recites “ a second type dopant material ”, rendering the limitation redundant and introducing uncertainty over whether the second type dopant material recited in claim 18 is the same as that recited in claim 15 or a different second type dopant material. Claims 19 and 20 are dependent on claim 18, and thus inherit the deficiencies of the parent claim. For examination purposes, the following will be assumed: Any linear dimension in a horizontal plane of the HV diode in claim 5 may be similar to any linear dimension of the corresponding memory plane in a horizontal plane. “Similar” in claim 5 means that the dimensions are within 10% of each other. The backside surface recited in claim 8 is the same as the one recited in claim 1. Claim 10 was meant to depend on claim 9, which recites transitional regions. The separation of the highly doped regions and the HV diodes means that the HV diodes are contained in the interior of an annular highly doped region (or other region contained between two closed curves), and that a distance from an HV diode to the interior boundary of the HV diodes is between 1 μ m and 10 μ m. The second type dopant material recited in claim 18 is the same as that recited in claim 15. These rejections may be overcome by: Clarifying which dimensions the limitations of claim 5 apply to and what is meant by “similar”. Rewrite claim 8 to either recite “the backside surface” or introduce “a second backside surface”. Rewrite claim 10 to depend on claim 9 or amend one of claim 1 or claim 10 to recite transitional regions. Clarify how the HV diodes of claim 14 are separated from the highly doped region while at the same time being separated from it. Rewrite claim 18 to either recite “the second type dopant material” or, e.g., “a second dopant material of the second type”. PNG media_image1.png 538 471 media_image1.png Greyscale Fig. 4B of Kim, reproduced with annotations added by the examiner. PNG media_image2.png 618 780 media_image2.png Greyscale Fig. 8 of Itai, reproduced with annotations added by the examiner. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-2, 7, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et. al. , Pub. No. US 2019/0139980, hereafter referred to as Kim, in view of Itai et. al. , Pub. No. US 2022/0005767, hereafter referred to as Itai . Regarding claim 1 , Kim teaches “ A semiconductor device ” (Kim [0002]), “ comprising: a substrate ” (Kim [0032]; Fig. 4B, reproduced above with annotations added by the examiner, substrate 100); “ a memory array disposed on the substrate ” (Kim [0033]; Fig. 4B, cell array region CAR), “ the memory array including: one or more memory planes ” (Kim [0031] and [0040]; Fig. 4B, stack structures ST), “ and a plurality of source region contact (SRC) nodes ” (Kim [0031]; Fig. 4B, common source plugs 178) “ that are disposed on a backside surface of corresponding one of the one or more memory planes and above the substrate ” (Kim [0032] and [0040]; Fig. 4B, note the relative locations of the common source plugs 178 and the substrate 100); “ a plurality of high-voltage (HV) diodes ” (Kim [0036] and [0039]; Fig. 4B, common sources 168; note that, in combination with the pocket well 104, the common source forms a diode) “ that are disposed in the substrate ” (Kim [0036]; Fig. 4B; note that the pocket well 104 is just a doped region of the substrate) “ and that are connected to corresponding SRC nodes ” (Fig. 4B; note that the common sources 168 contact the common source plugs 178), and “ the HV diodes including a first type dopant material ” (Kim [0036]: “The common source 168 may have the second conductivity (e.g., N-type conductivity).”), but does not teach “ a plurality of highly doped regions that are disposed in the substrate and that include a second type dopant material, each of the plurality of highly-doped regions including a plurality of local maximum doping regions that are vertically aligned under a frontside surface of the substrate. ” Itai, on the other hand, does teach “ a plurality of highly doped regions that are disposed in the substrate ” (Itai [0082]; Fig. 8, reproduced above with annotations added by the examiner, note that the p-type well region 100P 2 and the impurity region 100p 2 , collectively forming a guard ring region R GR3 , are disposed in the substrate 100) “ and that include a second type dopant material ” (Itai [0082]: “The guard ring region R GR3 is disposed in a P-type well region 100P 2 … In the guard ring region R GR3 , an impurity region 100p 2 containing P-type impurities, such as boron (B), is disposed in the surface of the semiconductor substrate 100.”), “ each of the plurality of highly-doped regions including a plurality of local maximum doping regions ” (Itai [0082]; Fig. 8, p-type well region 100P 2 , the impurity region 100p 2 ; note that it is assumed that a local maximum doping region can be any region with a higher concentration of impurities than its surroundings) “ that are vertically aligned under a frontside surface of the substrate ” (Itai Fig. 8; note the relative placement of the p-type well region 100P 2 and the impurity region 100p 2 ). The guard ring structures of Itai can be incorporated into the device of Kim as similar guard ring structures surrounding the memory device of Kim. It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include guard rings in the device of Kim because such a structure would provide protection against electrostatic discharge (ESD) and it would have been a simple combination of elements of the respective disclosures. Regarding claim 2 , the combined device of Kim and Itai described in the discussion of claim 1 further teaches “ The semiconductor device of claim 1, wherein the plurality of highly doped regions have a ring shape profile in a horizontal plane ” (Itai [0082]: “The guard ring region R GR3 is disposed in a P-type well region 100P 2 disposed separately from the P-type well region 100P 1 , and formed to surround the insulating region 100I 2 in the surface of the semiconductor substrate 100.”) “ and surrounds corresponding one or more of the plurality of HV diodes ” (Itai [0082]; note that the guard ring region R GR3 surrounds the common sources 168 of Kim in the combined device). Regarding claim 7 , the combined device of Kim and Itai described in the discussion of claim 1 further teaches “ The semiconductor device of claim 1, wherein the first type dopant material is a n-type semiconductor material ” (Kim [0039]), “ and the second type dopant material is a p-type semiconductor material ” (Itai [0082]). Regarding claim 11 , Kim teaches “ A semiconductor device ” (Kim [0002]), “ comprising: a substrate ” (Kim [0032]; Fig. 4B, substrate 100); “ a plurality of memory planes that are disposed on the substrate ” (Kim [0031] and [0040]; Fig. 4B, stack structures ST), “ each one of the plurality of memory planes being connected to one or more high-voltage (HV) diodes ” (Kim [0036], [0039], [0040]; Fig. 4B, note that the stack structures ST are connected to the common sources 168 through the common source plugs 178) “ that are disposed in the substrate ” (Kim [0036]; Fig. 4B; note that the pocket well 104 is just a doped region of the substrate), but does not teach “ a plurality of highly doped regions that are disposed in the substrate, each surrounding one or more corresponding HV diodes, each of the plurality of highly doped regions including a plurality of local maximum doping regions that are vertically aligned in the substrate ”. Itai, on the other hand, does teach “ a plurality of highly doped regions that are disposed in the substrate ” (Itai [0082]; Fig. 8, note that the p-type well region 100P 2 and the impurity region 100p 2 , collectively forming a guard ring region R GR3 , are disposed in the substrate 100), “ each of the plurality of highly doped regions including a plurality of local maximum doping regions that are vertically aligned in the substrate ” (Itai [0082]; Fig. 8, p-type well region 100P 2 , the impurity region 100p 2 ; note that it is assumed that a local maximum doping region can be any region with a higher concentration of impurities than its surroundings). The guard ring structures of Itai can be incorporated into the device of Kim as similar guard ring structures surrounding the memory device of Kim. The combined device teaches “ each surrounding one or more corresponding HV diodes ” (Itai [0082]; note that the guard ring region R GR3 surrounds the common sources 168 of Kim in the combined device). It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include guard rings in the device of Kim because such a structure would provide protection against electrostatic discharge (ESD) and it would have been a simple combination of elements of the respective disclosures . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3-4, 6, 9, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 07-43-01 Claims 5, 8, and would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The cited art, whether considered individually or in combination, especially when all limitations are considered within the specific claimed combination, fails to disclose or suggest the claim limitations of: Claim 3 , which recites the limitation, “ wherein each of the one or more memory planes is connected to a group of the plurality of HV diodes, the group of the plurality of HV diodes being surrounded by a corresponding highly doped region. ” Claim 4 is dependent on claim 3, and thus contains the same allowable material. Claim 5 , which recites the limitation, “ wherein each of the one or more memory planes is exclusively connected to one corresponding HV diode, the one corresponding HV diode having a dimension, in a horizontal plane, similar to the each of the one or more memory planes, and wherein the plurality of highly doped regions are disposed among the one or more memory planes and at edge region of the substrate. ” Claim 6 , which recites the limitation, “ wherein each of the plurality of HV diodes includes a heavily doped region and a lightly doped region, wherein the heavily doped region is embedded within the lightly doped region. ” Claim 8 , which recites the limitation, “ wherein doping levels of the plurality of local maximum doping regions are gradually reduced along a direction from the frontside surface to a backside surface of the substrate. ” Claim 9 , which recites the limitation, “ further include transitional regions including the second type dopant material, wherein the plurality of local maximum doping regions are discrete, and the transitional regions are disposed within the substrate and among the vertically aligned plurality of local maximum doping regions. ” Claim 10 , which recites the limitation, “ wherein a doping level of each of the transitional regions is lower than adjacent local maximum doping regions. ” Claim 12 , which recites the limitation, “ wherein each one of the plurality of memory planes is exclusively connected to a corresponding HV diode, and wherein the plurality of highly doped regions are disposed among the plurality of memory planes and at edge region of the substrate. ” Claim 13 , which recites the limitation, “ wherein each one of the plurality of memory planes is connected to a group of the one or more HV diodes, wherein the group of the one or more HV diodes are surrounded by a corresponding highly doped region, and wherein the plurality of highly doped regions are disposed at edge region of the substrate. ” Claim 14 is dependent on claim 13, and thus contains the same allowable material . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT EMIL THROCKMORTON whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 12 PM and 1 PM - 5:30 PM ET Monday-Thursday, 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN H LOKE can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.E.T./ Examiner, Art Unit 2818 /STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818 Application/Control Number: 18/647,354 Page 2 Art Unit: 2818 Application/Control Number: 18/647,354 Page 3 Art Unit: 2818 Application/Control Number: 18/647,354 Page 4 Art Unit: 2818 Application/Control Number: 18/647,354 Page 5 Art Unit: 2818 Application/Control Number: 18/647,354 Page 6 Art Unit: 2818 Application/Control Number: 18/647,354 Page 7 Art Unit: 2818 Application/Control Number: 18/647,354 Page 8 Art Unit: 2818 Application/Control Number: 18/647,354 Page 9 Art Unit: 2818 Application/Control Number: 18/647,354 Page 10 Art Unit: 2818 Application/Control Number: 18/647,354 Page 11 Art Unit: 2818 Application/Control Number: 18/647,354 Page 12 Art Unit: 2818 Application/Control Number: 18/647,354 Page 13 Art Unit: 2818 Application/Control Number: 18/647,354 Page 14 Art Unit: 2818 Application/Control Number: 18/647,354 Page 15 Art Unit: 2818
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