Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 4-5 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/20/2026 .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3, 10, 12-14 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He et al. (CN 112042117 A and He hereinafter.).
Regarding claim 1, He discloses a circuit comprising: an integrator circuit [fig. 13] including: an operational amplifier [INT1] having an input terminal and an output terminal; a trimmable component [C1calm] having a first terminal, a second terminal, and a control terminal [C1calm controlled via 1302], the first terminal of the trimmable component coupled to the input terminal [C1calm in feedback loop with INT1], and the second terminal of the trimmable component coupled to the output terminal [C1calm in feedback loop with INT1]; and a calibration control circuit [1302] having a first terminal and a second terminal, the first terminal of the calibration control circuit coupled to the output terminal [pg. 15], and the second terminal of the calibration control circuit coupled to the control terminal of the trimmable component [pg. 15].
Regarding claim 2, He discloses further wherein the integrator circuit includes a calibration ramp circuit [4 adjustable resistors enclosed in dashed lines] having a first terminal and a second terminal, the second terminal of the calibration ramp circuit coupled to the input terminal of the operational amplifier [as shown in fig. 13].
Regarding claim 3, He discloses further wherein the input terminal is an inverting terminal [differential input of INT1] and the trimmable component is a capacitor [as shown].
Regarding claim 10, He discloses an integrator circuit [fig. 13] comprising: an operational amplifier [INT1] having an input terminal [as shown] and an output terminal [as shown]; a trimmable capacitor [C1calm] in a feedback loop between the output terminal and the input terminal [as shown], the trimmable capacitor having a control terminal [C1calm controlled via 1302]; and a calibration control circuit [1302] having a first terminal and a second terminal, the first terminal of the calibration control circuit coupled to the output terminal [pg. 15], and the second terminal of the calibration control circuit coupled to the control terminal of the trimmable capacitor [pg. 15], the calibration control circuit configured to: obtain a ramp time [fig. 15 and pg. 15-17]; compare the ramp time to a target time constant [RC time] to obtain a comparison result [fig. 15 and pg. 15-17]; and adjust a control signal provided to the control terminal of the trimmable capacitor responsive to the comparison result [fig. 15 and pg. 15-17].
Regarding claim 12, He discloses further wherein the calibration control circuit is configured to: adjust the control signal to increase capacitance of the trimmable capacitor responsive to the comparison result indicating the ramp time is less than the target time constant [pg. 15-17]; and adjust the control signal to decrease capacitance of the trimmable capacitor responsive to the comparison result indicating the ramp time is more than the target time constant [pg. 15-17].
Regarding claim 13, He discloses further wherein the calibration control circuit is configured to obtain the target time constant from memory [He, digital logic controller].
Regarding claim 14, He discloses an apparatus comprising: an on-chip integrator circuit [fig. 13] including: an operational amplifier [INT1] having an input terminal and an output terminal [as shown]; a trimmable component [C1calm] in a feedback loop between the output terminal and the input terminal [a shown], the trimmable component having a control terminal [controllable via 1302]; and a calibration control circuit having a first terminal and a second terminal [pg. 15], the first terminal of the calibration control circuit coupled to the output terminal, and the second terminal of the calibration control circuit coupled to the control terminal of the trimmable component [pg. 15], the calibration control circuit configured to: determine a target value for the trimmable component responsive to a target time constant and test results [fig. 15 and pg. 15-17]; and adjust a control signal provided to the control terminal of the trimmable component responsive to the determined target value [fig. 15 and pg. 15-17].
Regarding claim 18, He discloses further wherein the on-chip integrator circuit is part of a low-pass filter circuit or high-pass filter circuit [pg. 12-13].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over He in view of Fu et al. (CN 108111146 A and Fu hereinafter.).
Regarding claim 6, He discloses all the features regarding claim 1 as indicated above. He does not explicitly disclose wherein the calibration control circuit includes a timer and a comparator, and the timer is configured to track an amount of clock cycles from a trigger until the comparator indicates a ramp voltage reaches a threshold.
However, Fu discloses [fig. 1 and 2] wherein the calibration control circuit includes a timer [pg. 6, charging time T] and a comparator [CMP], and the timer is configured to track an amount of clock cycles from a trigger until the comparator indicates a ramp voltage reaches a threshold [fig. 5 and pg. 6]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by He to include calibration control circuit includes a timer and a comparator, and the timer is configured to track an amount of clock cycles from a trigger until the comparator indicates a ramp voltage reaches a threshold as taught by Fu to improve calibration performance in an integrating circuit
Regarding claim 7, He in view of Fu discloses further wherein the calibration control circuit is configured to compare the amount of clock cycles to a target amount of clock cycles for a predetermined time constant [Fu, pg. 6].
Regarding claim 8, He in view of Fu discloses further wherein the comparator is a first comparator [as shown], the calibration control circuit includes a second comparator [within digital logic controller ], and the timer is configured to track the amount of clock cycles from the first comparator indicating the ramp voltage [He, fig. 1 and 5, pg. 5-6 regarding Vo reaching Vref and err signal] reaches a first threshold until the second comparator indicates the ramp voltage reach a second threshold [He, pg. 5-6].
Regarding claim 9, He in view of Fu discloses further wherein the calibration control circuit includes storage coupled to the timer [He, digital logic performing mathematical operations], the storage configured to store a target time constant [He, pg. 15] or a related number of clock cycles [He, pg. 15].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of Fu further in view of Ying et al. (CN 116488615 and Ying hereinafter.).
Regarding claim 11, He in view of Fu discloses all the features regarding claim 10 as indicated above. He in view of Fu does not explicitly disclose wherein the calibration control circuit is configured to: measure an up ramp time; measure a down ramp time; and combine the up ramp time and the down ramp time to obtain the ramp time.
However, Ying discloses [fig. 2] wherein the calibration control circuit [300] is configured to: measure an up ramp time [pg. 12-13]; measure a down ramp time [pg. 12-13]; and combine the up ramp time and the down ramp time to obtain the ramp time [pg. 12-13. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by He in view of Fu. to include the calibration control circuit is configured to: measure an up ramp time; measure a down ramp time; and combine the up ramp time and the down ramp time to obtain the ramp time as taught by Ying to improve frequency adjusting performance of a calibration circuit.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over He in view of Ying.
Regarding claim 15, He discloses all the features regarding claim 14 as indicated above. He does not explicitly disclose wherein the calibration control circuit is configured perform the test by: measuring an up ramp time; measuring a down ramp time; and combining the up ramp time and the down ramp time to obtain the ramp time; and comparing the ramp time to the target time constant to obtain the test results.
However, Ying discloses [fig. 2] wherein the calibration control circuit [300] is configured perform the test by: measuring an up ramp time [pg. 12-13]; measuring a down ramp time [pg. 12-13]; and combining the up ramp time and the down ramp time to obtain the ramp time [pg. 12-13]; and comparing the ramp time to the target time constant to obtain the test results [pg. 12-13]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by He in view of Fu. to include the calibration control circuit is configured perform the test by: measuring an up ramp time; measuring a down ramp time; and combining the up ramp time and the down ramp time to obtain the ramp time; and comparing the ramp time to the target time constant to obtain the test results as taught by Ying
Regarding claim 16, He in view of Ying discloses further wherein the trimmable component [Ying, 121] is a trimmable capacitor, and the calibration control circuit is configured to: adjust the control signal to increase capacitance of the trimmable capacitor responsive to the test results indicating the ramp time is less than the target time constant [Ying, pg. 12-13]; and adjust the control signal to decrease capacitance of the trimmable capacitor responsive to the test results indicating the ramp time is more than the target time constant [Ying, pg. 12-13].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of Liang et al. (US 20200366209 A1 and Liang hereinafter.).
Regarding claim 17, He discloses all the features regarding claim 14 as indicated above. He does not explicitly disclose wherein the on-chip integrator circuit is part of a resonant converter controller.
However, Liang discloses wherein the on-chip integrator circuit is part of a resonant converter controller [para. 8]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by He to include the on-chip integrator circuit is part of a resonant converter controller as taught by Liang to improve signal robustness of an integrating circuit.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of Huynh et al. (US 20200158770 A1 and Huynh hereinafter.).
Regarding claim 19, He discloses all the features regarding claim 14 as indicated above. He does not explicitly disclose wherein the on-chip integrator circuit is part of a phase-shift oscillator circuit.
However, Huynh discloses wherein the on-chip integrator circuit is part of a phase-shift oscillator circuit [para. 132]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by He to include the on-chip integrator circuit is part of a phase-shift oscillator circuit as taught by Huynh to improve power requirements of an integrating circuit.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of Lin et al. (US 20130181760 A1 and Lin hereinafter.).
Regarding claim 20, He discloses all the features regarding claim 14 as indicated above. He does not explicitly disclose wherein the on-chip integrator circuit is part of a relaxation oscillator circuit.
However, Lin discloses wherein the on-chip integrator circuit is part of a relaxation oscillator circuit [fig. 1, para. 52]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by He to include the on-chip integrator circuit is part of a relaxation oscillator circuit as taught by Lin to improve power consumption of an integrating circuit.
Conclusion
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/JAMES G YEAMAN/Examiner, Art Unit 2842