DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bailey (US20190205218), in view of Costin (US20220057798).
Claims 1, 9 and 15, BAILEY teaches a system for computing asymmetric computing redundancy, the system comprising: a plurality of computing systems of an autonomy system, wherein each of the plurality of computing systems comprises at least one memory device and at least one processor: (BAILEY, paras [0015]–[0019] [0056] diagrams, disclose “multiple processors operating in parallel within a computing system,” wherein “each processor includes processing logic and associated memory including cache and local memory.” each having at least one processor and at least one memory device, within an autonomous or high-reliability computing architecture);
the processor configured to: write state data to a state memory device (BAILEY, paras [0020]–[0024], [0036], disclose that “runtime state information, including register state, cache contents, and execution context, may be stored in memory to preserve the operational state of a processor.” This explicitly teaches writing state data to a memory device corresponding to a state memory device);
Receive data descriptive of the plurality of computing systems from the autonomy system; and process the data from the autonomy system; execute the autonomy system; (BAILEY, paras [0033]–[0036], disclose that monitoring circuitry “receives operational data and runtime information from multiple processors” and that the processors “execute program instructions corresponding to system workloads.” The receipt and processing of operational data and execution of system workloads correspond to receiving, processing, and executing an autonomy system);
An auxiliary computing system configured to: detect a condition within a computing system of the plurality of computing systems (BAILEY, paras [0032]–[0035], disclose that “monitoring circuitry detects runtime state errors, processor faults, or abnormal operating conditions associated with one or more processors.” The monitoring circuitry functions as an auxiliary computing system that detects a condition within one of the computing systems);
Write the state data from the state memory device to the auxiliary computing system (BAILEY, paras [0037]–[0038], disclose that “state reload circuitry retrieves runtime state information from memory and loads the retrieved runtime state into another processor.” This teaches transferring state data from a state memory device to another computing system, satisfying this limitation);
And reconnect the autonomy system to the auxiliary computing system; BAILEY does not explicitly disclose reconnecting the autonomy system or sensor inputs to the auxiliary computing system, While BAILEY teaches loading runtime state into another processor, it does not expressly describe rerouting system inputs or reconnecting the autonomy system; COSTIN, paras [0022]–[0028], disclose that “upon detection of a controller failure, sensor data streams may be redirected to a secondary controller to allow continued vehicle operation.” Further, para [0043] discloses that “the backup controller receives sensor data and executes vehicle control functions.”, thus, It would have been obvious to one of ordinary skill in the art to modify the system of BAILEY to reconnect the autonomy system to the auxiliary computing system as taught by COSTIN in order to enable continued autonomous operation following a detected fault, thereby improving system reliability and fault tolerance.
Claims 2 and 10, wherein the auxiliary computing system is a monitor module for the autonomy system, is taught by BAILEY, paras [0029]–[0033], which explicitly disclose monitoring circuitry configured to observe processor operation and detect fault conditions.
Claims 3 and 11, further comprising connecting the auxiliary computing system to a plurality of sensors of the autonomy system, is not explicitly taught by the primary reference. However, COSTIN, paras [0013]–[0021] and [0022]–[0030], disclose connecting a backup controller to vehicle sensors and routing sensor data streams to that controller upon failure. It would have been obvious to incorporate such sensor connectivity into the auxiliary computing system of the BAILEY to allow continued autonomous operation.
Claims 4, 12 and 18, wherein the condition comprises a processor malfunction, an auxiliary computing failure, or a data corruption, is taught by BAILEY, paras [0029]–[0035], which disclose detecting processor faults, runtime errors, and corrupted runtime state data.
Claims 5, 13 and 16, wherein the auxiliary computing system is further configured to execute program data from a program memory device, is taught by BAILEY, paras [0037]–[0041], which disclose that the processor receiving the reloaded runtime state resumes execution of program instructions.
Claims 6 and 14, wherein the program memory device and the state memory device are compartmentalized from each other, is taught by BAILEY, paras [0020]–[0024], [0036], which distinguish executable program memory from runtime state and cache memory.
Claims 7 and 8, wherein the plurality of computing systems are an FPGA or a microcontroller, (para 0042) [0032], BAILEY discloses processors and computing devices..
Claim 17, Bailey teaches initiating a redundancy procedure upon detection of a fault condition (Bailey, paras [0033]–[0036]).
Claim 19, Bailey and Costin together teach continued autonomous execution after a fault without restarting the system, which inherently prevents triggering a minimum risk maneuver that would otherwise be performed in response to a detected failure (Bailey, paras [0045]–[0053]; Costin, paras [0031]–[0040]).
Claim 20, Bailey teaches monitoring circuitry that detects fault conditions independently of the processor experiencing the fault, making detection of the condition on the first processor by a second processor or monitor an obvious aspect of the disclosed fault-tolerant architecture (Bailey, paras [0029]–[0033]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD AHMED whose telephone number is (571)270-1315. The examiner can normally be reached M-F 9:00-8:30 PM PST with IFP.
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MASUD . AHMED
Primary Examiner
Art Unit 3657A
/MASUD AHMED/Primary Examiner, Art Unit 3657