DETAILED ACTION
Remarks
Applicant presents a communication filed 9 June 2026 responsive to the 11 March 2026 non-final Office action (the “Previous Action”).
With the communication:
claims 1, 6, 10, 12 and 16 are amended;
claim 14 is cancelled; and
new claim 21 is added.
Claims 1-13 and 15-21 are pending. Claims 1, 12 and 16 are the independent claims.
Any unpersuasive arguments are addressed in the “Response to Arguments” section below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant argues with respect to claim 1 that the combination does not teach or suggest instantiation or execution of the firmware update instructions from the memory circuitry. (Remarks, p. 8 par. 3). Applicant first reasons that in the specification, firmware activation instructions are copied to volatile memory because they cannot be executed from the inactive flash bank. (Remark, p. 9 par. 1). Applicant then reasons that Reed does not teach or suggest implementing the first firmware image in the first portion of storage, copying the firmware update instructions of the second firmware image to the memory circuitry, and instantiating or executing the firmware update instructions from the memory circuitry. (Remarks, p. 9 par. 1). And Applicant lastly reasons that Reed is focused on software, which Applicant argues is different from firmware. (Remarks, p. 9 par. 1).
Examiner respectfully disagrees.
As to executing instructions from the inactive bank, examiner respectfully submits that the rejection does not include execution of instructions while in an inactive flash bank and that the claim does not refer to any inability to execute instructions in an inactive flash back. Limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). It is also not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. M.P.E.P. § 2144(IV).
As to whether Reed teaches “implementing the first firmware image in the first portion of storage, copying the firmware update instructions of the second firmware image to the memory circuitry, and instantiating or executing the firmware update instructions from the memory circuitry”, examiner respectfully points out that Reed was not cited as teaching all of these elements. They were asserted to have been obvious over the combination both Chindambaram and Reed. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
And as to software being different from firmware, Reed was only cited as teaching “instructions”, not firmware. Examiner also respectfully submits that firmware is in fact a type of software. For example, Chindambaram and Rao refers to their “Live Firmware Update” system as providing “software upgrades.” (See Chindambaram, title and p. 4 Sec. 4.3.2 par. 2).
These arguments are accordingly unpersuasive.
Applicant argues that various limitations of claims 12 and 16 are also not taught by the prior art either. Examiner respectfully disagrees for the reasons set forth in the rejections below. Applicant provides only conclusions to the contrary.
Applicant’s arguments with respect to the dependent claims by virtue of their dependence from claims 1, 12 or 16 are unpersuasive for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 12-13 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram et al. “Live Firmware Update Without Device Reset on C2000TM MCUs” (art made of record – hereinafter Chidambaram) in further view of Reed et al. (US 2023/0350661) (art made of record – hereinafter Reed).
As to claim 1, Chidambaram discloses an apparatus comprising:
a first portion of storage having a first firmware image, the first firmware image including first instructions; (e.g., Chidambaram, p. 3 Fig. 4-1 and associated text [see figure, which shows “Flash Bank 0” and “Flash Bank 1”, each with an application]; p. 2 Sec. 4.1 par. 1: Flash banks are programmed with application firmware; p. 6 item 5: an application image)
a second portion of storage having a second firmware image, (e.g., Chidambaram, p. 3 Fig. 4-1 and associated text [see figure, which shows “Flash Bank 0” and “Flash Bank 1”, the contents, each with an application]; p. 2 Sec. 4.1 par. 1: Flash banks are programmed with application firmware; p. 6 item 5 an application image) the second firmware image including firmware update instructions; (e.g., Chidambaram, p. 7 Fig. 4-4 and associated text, p. 6 Sec. 4.5 item 5: the LFU bootloader receives an application image [second firmware image] and programs it into the Inactive Flash bank; p. 6 Sec. 4.5 item 6: the custom bootloader branches to the LFU entry point (C_int_LFU) of [included in, see figure] the new application image. The function at the LFU entry point [firmware update instructions, or at least a portion of them, along with any other instructions in the new application image used to initialize the update] does the following:)
memory circuitry; (e.g., Chidambaram, p. 3 Sec. 4.2 par. 1: keeping variables in RAM [memory circuitry]) and
programmable circuitry configured to at least one of instantiate or execute the first instructions of the first portion of storage (e.g., Chidambaram, p. 2 Sec. 3 last bullet: dual flash banks allow application firmware resident on one Flash bank [first instructions] to execute [necessarily by a processor (programmable circuitry)] while the other Flash bank is being updated) to:
implement the first firmware image in the first portion of storage; (see immediately above, if the code of the application firmware is executed, its functionality is implemented)
the firmware update instructions of the second firmware image (see above) and
the firmware update instructions (see above).
Chidambaram does not explicitly disclose to copy the firmware update instructions of the second firmware image to the memory circuitry and instantiate or execute the firmware update instructions from the memory circuitry.
However, in an analogous art, Reed discloses to:
copy the instructions to the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times) and
to instantiate or execute the instructions from the memory circuitry (see immediately above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the firmware update instructions of the second firmware image and memory circuitry taught by Chidambaram, such that the instructions are copied to the memory circuitry and instantiated or executed from the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing the instructions faster. (See Reed, par. [0059]).
As to claim 2, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above) Chidambaram further discloses:
wherein the first portion of storage includes a first portion of flash memory, (e.g., (e.g., Chidambaram, p. 3 Fig. 4-1 and associated text [see figure, which shows “Flash Bank 0” and “Flash Bank 1”, each with an application]) and
wherein the second portion of storage includes a second portion of flash memory (see immediately above).
As to claim 3, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above), Chidambaram further discloses:
wherein the memory circuitry includes random-access memory circuitry (e.g., Chidambaram, p. 3 Sec. 4.2 par. 1: keeping variables in RAM [random access memory circuitry]).
As to claim 4, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above),
Chidambaram further discloses:
wherein the programmable circuitry is further configured to at least one of instantiate or execute the firmware update instructions (e.g., Chidambaram, p. 3 Fig. 4-1, p. 7 Fig. 4-4 and associated text and item 9: once the optimal LFU switchover point is identified, the LFU steps “(ActivateApp)” occur [ActivateApp being another portion of the firmware update instructions. Instructions are necessarily executed by a processor (programmable circuitry)]) to initialize an interrupt vector table of one or more interrupt service routines of the second firmware image (e.g., Chidambaram, p. 7 item 9, the LFU switchover steps (ActivateApp) occur. First global interrupts are disabled. Hardware interrupt vector table swapping and RAM block swapping are executed [a interrupt vector table is by definition an association between interrupt service routines and interrupts]).
Chidambaram does not explicitly disclose firmware update instructions of the memory circuitry.
However, in an analogous art, Reed discloses:
instructions of the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the firmware update instructions and memory circuitry of Chidambaram, such that the instructions are copied to the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 5, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above), Chidambaram further discloses:
wherein the programmable circuitry is further configured to at least one of instantiate or execute the firmware update instructions to initialize variables of the second firmware image (e.g., Chidambaram p. 7 Fig. 4-4 and associated text, p. 6 item 6a: The compiler’s LFU initialization routine [part of the firmware update instructions] is invoked [executed by a programmable circuitry]. This initializes any variables that have been indicated as needing initialization; p. 2 Sec. 1 bullet 1: a Compiler LFU initialization routine that initializes variables in the new firmware)
Chidambaram does not explicitly disclose firmware update instructions of the memory circuitry.
However, in an analogous art, Reed discloses:
instructions of the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the firmware update instructions and memory circuitry of Chidambaram, such that the instructions are copied to the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 6, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above), Chidambaram further discloses:
wherein the second firmware image is inactive while the programmable circuitry beings to at least one of instantiate or execute the firmware update instructions (e.g., Chidambaram, p. 7 Figure 4-4, p. 3 par. 2: activating the new firmware [new firmware image] involves branching to the LFU entry point of the new firmware, executing the compiler’s LFU initialization routine, arriving inside the main() of the new image, and performing additional initialization. This is where interrupts are briefly disabled and initialization that needs interrupts to be disabled is performed, before interrupts are re-enabled [routines or instructions that perform all these steps being firmware update instructions. See e.g., the compiler initialization routine _TI_auto_init_warm and ActivateApp Figure 4-4 at p.7, and associated text]; p. 7 item 9: global interrupts are re-enabled. Now, ISRs and background task functions of the new firmware begin executing [i.e., second firmware is activated at this point after the preceding enabling, disabling and initialization], representing completion of the LFU switchover) to:
disable interrupts; (e.g., Chidambaram, p. 7 item 9: LFU switchover steps (ActivateApp) [update instructions, see Figure 4-4] occur. First, global interrupts are disabled)
initialize a data stack of the second firmware image; (e.g., Chidambaram, p. 7 item 9: First, global interrupts are disabled. Then the stack pointer is re-initialized [of the second image because this is part of switchover to that image])
enable interrupts; (e.g., Chidambaram, p. 7 item 9: then the stack pointer is re-initialized and global interrupts are re-enabled) and
execute instructions of the second firmware image (see above, the LFU entry point [C_int_LFU] and ActivateApp that perform the initialization are all part of the second firmware image. In addition, the initialization is also performed “to” execute instructions of the new firmware image in the sense that the initialization is performed so the system can begin using the instructions of the new image instead of the old one )
Chidambaram does not explicitly disclose firmware update instructions from the memory circuitry.
However, in an analogous art, Reed discloses:
instructions from the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). The electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the firmware update instructions and memory circuitry of Chidambaram, such that the instructions are copied to the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 7, Chidambaram/Reed discloses the apparatus of claim 6 (see rejection of claim 6 above), Chidambaram further discloses:
wherein the programmable circuitry is further configured to at least one of instantiate or execute the firmware update instructions (e.g., Chidambaram, p. 3 Fig. 4-1, p. 7 Fig. 4-4 and associated text and item 9: once the optimal LFU switchover point is identified, the LFU steps “(ActivateApp)” occur [and see figure “ActivateApp” is part of the Application instructions in Flash Bank 1, meaning its steps executed by a programmable circuitry]) to:
initialize the data stack of the second firmware image after disabling the interrupts; (e.g., Chidambaram, p. 7 item 9: LFU switchover steps (ActivateApp) occur. First, global interrupts are disabled. Then the stack pointer is re-initialized [of the second image because this is part of switchover to that image])
enable the interrupts after initializing the data stack of the second firmware image; (e.g., Chidambaram, p. 7 item 9: then the stack-pointer is re-initialized and global interrupts are re-enabled) and
execute instructions of the second firmware image after enabling the interrupts (e.g., Chidambaram, p. 7 item 9: global interrupts are re-enabled. Now, ISRs and background task functions of the new firmware [second software image] begin executing).
Chidambaram does not explicitly disclose firmware update instructions of the memory circuitry.
However, in an analogous art, Reed discloses:
instructions of the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the firmware update instructions and memory circuitry of Chidambaram, such that the instructions are copied to the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 12, it is a method claim whose limitations are substantially the same as those of claim 1. Those limitations are taught by or obvious in view of the prior art as set forth above with respect to that claim. Further limitations, disclosed by Chidambaram, include:
the firmware update instructions to initialize the second firmware image (e.g., Chidambaram p. 7 Fig. 4-4 and associated text, p. 6 Sec. 4.5 item 5: the LFU bootloader receives an application image and programs it into the Inactive Flash bank [initializing the firmware update instructions]; p. 6 item 6a: The compiler’s LFU initialization routine [also firmware update instructions] is invoked [executed by a processor (programmable circuitry)]. This initializes any variables that have been indicated as needing initialization; p. 2 Sec. 1 bullet 1: a Compiler LFU initialization routine that initializes variables in the new firmware).
As to claim 13, Chidambaram/Reed discloses the method of claim 12 (see rejection of claim 12 above), Chidambaram further discloses further comprising initializing the second firmware image by at least one of:
initializing variables of the second firmware image; (e.g., Chidambaram p. 7 Fig. 4-4 and associated text, p. 6 item 6a: The compiler’s LFU initialization routine [part of the firmware update instructions] is invoked [executed by a processor (programmable circuitry)]. This initializes any variables that have been indicated as needing initialization; p. 2 Sec. 1 bullet 1: a Compiler LFU initialization routine that initializes variables in the new firmware) or
initializing an interrupt vector table of one or more interrupt service routines of the second firmware image.
As to claim 16, it is a method claim whose limitations are substantially the same as those of claim 1 and rejected for the same reasons. Further limitations, disclosed by Chidambaram, include:
programming circuitry configured to at least one of instantiate or execute the first instructions of the first portion of storage (see below) to:
implement the firmware update instructions (e.g., Chidambaram, p. 7 Figure 4-4, p. 3 par. 2: activating the new firmware [new firmware image] involves branching to the LFU entry point of the new firmware, executing the compiler’s LFU initialization routine, arriving inside the main() of the new image, and performing additional initialization. This is where interrupts are briefly disabled and initialization that needs interrupts to be disabled is performed, before interrupts are re-enabled [the routines or instructions that perform all these steps, or any portion of them are firmware update instructions. See e.g., the compiler initialization routine _TI_auto_init_warm and ActivateApp Figure 4-4 at p.7, and associated text])
after implementing the firmware update instructions, disable the implementation of the first firmware image (e.g., Chidambaram p. 6 item 6 “Execute Compiler LFU Initialization routine…”: the compiler’s initialization routine (__TI_auto_init_Warm) is invoked. This initializes any variables that have been indicated as needing initialization; p. 7 item 9: old Control loop ISRs are still executing. Once the optimal switchover point is identified, the LFU switchover steps (ActivateApp) occur. First, global interrupts are disabled. Hardware Interrupt vector table swapping and RAM block swapping are executed [disabling interrupts, and swapping being disabling the first image]. Then the stack pointer is re-initialized. Now, ISRs and background task functions of the new firmware begin executing)
after disabling the implementation of the first firmware image, implement the second firmware image in the second portion of storage (e.g., Chidambaram (e.g., Chidambaram p. 7 item 9: now ISRs and background task functions of the new firmware begin executing [implementing])
Chidambaram does not explicitly disclose firmware update instructions in the memory circuitry; or the firmware update instructions from the memory circuitry.
However, in analogous art, Reed discloses:
instructions in the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times) and
instructions from the memory circuitry (see immediately above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the update instructions and memory circuitry of Chidambaram, such that the instructions are copied to the memory circuitry before being executed, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 17, it is an apparatus claim including the limitations of both claim 2 and claim 3. Those limitations are taught by or obvious in view of the prior art for the reasons set forth above with respect to those claims.
As to claim 18, it is an apparatus claim including the limitations of both claim 4 and claim 5. Those limitations are taught by or obvious in view of the prior art for the reasons set forth above with respect to those claims.
As to claim 19, it is an apparatus claim including the limitations of both claim 6 and claim 7. Those limitations are taught by or obvious in view of the prior art for the reasons set forth above with respect to those claims
Claims 8-10, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram (“Live Firmware Update Without Device Reset on C2000TM MCUs”) in view of Reed (US 2023/0350661) in further view of Eitner et al. (US 6,070,012) (art made of record – hereinafter Eitner).
As to claim 8, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above), Chidambaram further discloses but does not explicitly disclose wherein the first firmware image further includes swap instructions and the programmable circuitry is further configured to: copy the swap instructions of the first firmware image to the memory circuitry; execute the swap instructions from the memory circuitry; and perform an A/B swap responsive to executing the swap instructions.
However, in an analogous art, Eitner discloses wherein the first firmware image further includes swap instructions (e.g., Eitner, Fig. 4 and associated text, col. 7 ll. 11-13, loadpicker logic 411 and 415 selects a valid software subsystem from flash bank A 402 or flash bank 4 404 [see figure, each bank has loadpicker logic, all logic in each bank is construed as an image]) and the programmable circuitry is further configured (see below, execution of instructions is necessarily by a processor (programmable circuitry)) to:
swap instructions of the first firmware image (see immediately above)
execute the swap instructions; (e.g., Eitner, col. 7 ll. 35-38: Load picker logic 411 in flash bank A 402 remaps the base address of the two flash banks [meaning that logic is executed]) and
perform an A/B swap responsive to executing the swap instruction (e.g., Eitner, col. 7 ll. 35-40: load picker logic 411 remaps the base address of the two flash banks. Flash bank A and flash bank B essentially swap base address mapping values and thereby become active or inactive; col. 7 ll. 57-59: if the download does occur properly then the base addresses are swapped and the active bank becomes flash bank B rather than flash bank A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first image of Chidambaram such that it includes swap instructions executed to perform an A/B swap, as taught by Eitner, as Eitner would provide the advantages of a means of inactivating the old firmware image, activating the new firmware image and a means to ensure the new firmware is properly downloaded before the swap. (See Eitner, col. 7 ll. 40-64).
Further, in analogous art, Reed discloses to:
copy the instructions to the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). The electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times)
instructions from the memory circuitry; (see immediately above)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the swap instructions of Chidambaram/Eitner, such that the instructions are copied to the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 9, Chidambaram/Reed/Eitner discloses the apparatus of claim 8 (see rejection of claim 8 above), but Chidambaram/Reed does not explicitly disclose wherein the programmable circuitry is further configured to at least one of instantiate or execute the swap instructions of the memory circuitry to: set the first portion of the storage as inactive; and set the second portion of the storage as active.
However, in an analogous art, Eitner discloses:
wherein the programmable circuitry is further configured to at least one of instantiate or execute the swap instructions (see below, since the loadpicker logic is stored in flash memory it comprises instructions and is necessarily executed by a processor to function) to:
set the first portion of the storage as inactive; (e.g., Eitner, col. 7 ll. 35-40: load picker logic 411 remaps the base address of the two flash banks. Flash bank A and flash bank B essentially swap base address mapping values and thereby become active or inactive; col. 7 ll. 57-59: if the download does occur properly then the base addresses are swapped and the active bank becomes flash bank B rather than flash bank A) and
set the second portion of the storage as active (see immediately above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first image of Chidambaram such that it includes swap instructions executed to set the first portion of the storage as inactive and set the second portion of the storage as active, as taught by Eitner, as Eitner would provide the advantages of a means of executing the new image and not the old one, and a means to ensure the new firmware is properly downloaded before the swap. (See Eitner, col. 7 ll. 40-64).
Further, in analogous art, Reed discloses:
the instructions of the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the swap instructions of Chidambaram/Eitner, such that the instructions are copied to the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 10, Chidambaram/Reed/Eitner discloses the apparatus of claim 8 (see rejection of claim 8 above), Chidambaram further discloses:
wherein the programmable circuitry is configured (see below and note that software functionality is necessarily performed by a processor (programmable circuitry)]) to:
continue implementing the first firmware image in the first portion of storage while at least one of instantiating or executing the firmware update instructions (e.g., Chidambaram, p. 6 item 6 “Execute Compiler LFU Initialization routine…”: the compiler’s initialization routine (__TI_auto_init_Warm) is invoked. This initializes any variables that have been indicated as needing initialization; p. 2 Sec. 2 bullet 1: Control ISRs of the old firmware; p. 7 item 9: old Control loop ISRs are still executing. Once the optimal switchover point is identified, the LFU switchover steps (ActivateApp) occur. First, global interrupts are disabled. Hardware Interrupt vector table swapping and RAM block swapping are executed. Then the stack pointer is re-initialized. Now, ISRs and background task functions of the new firmware begin executing [so the old firmware is now disabled]) and
swap after the at least one of instantiating or executing the firmware update instructions (e.g., Chidambaram, p. 7 item 9: global interrupts are re-enabled [executing firmware update instructions, see above]. Now [i.e., after], ISRs and background task functions of the new firmware begin executing [a swap to the new firmware]).
Chidambaram does not explicitly disclose update instructions of the memory circuitry or at least one of instantiate or execute the swap instructions of the memory circuitry.
However, in an analogous art, Eitner discloses:
at least one of instantiate or execute the swap instructions to perform the swap (e.g., Eitner, col. 7 ll. 35-40: load picker logic 411 [swap instructions] remaps the base address of the two flash banks. Flash bank A and flash bank B essentially swap base address mapping values and thereby become active or inactive; col. 7 ll. 57-59: if the download does occur properly then the base addresses are swapped and the active bank becomes flash bank B rather than flash bank A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the swap of Chidambaram such that it is performed by instantiating or executing swap instructions, as taught by Eitner, as Eitner would provide the advantages of a means of activating the new image and deactivating the old one and a means to ensure the new firmware is properly downloaded before the swap. (See Eitner, col. 7 ll. 40-64).
Further, in an analogous art, Reed discloses:
instructions of the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the swap instructions, update instructions and memory circuitry of Chidambaram/Eitner, such that these instructions are copied to the memory circuitry before being executed, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
As to claim 15, Chidambaram/Reed discloses the method of claim 12 (see rejection of claim 12 above), Chidambaram further discloses performing firmware update by implementing the firmware update instructions (see rejection of claim 12 above) but does not explicitly disclose further comprising implementing the firmware update instructions in the memory circuitry; setting the first portion of the storage as inactive after implementing the firmware update instructions; and setting the second portion of the storage as active after implementing the firmware update instructions.
However, in analogous art, Reed discloses:
implementing the instructions in the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the firmware update instructions and memory circuitry of Chidambaram, such that the instructions are implemented in the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing those instructions faster. (See Reed, par. [0059]).
Further, in an analogous art, Eitner discloses:
setting the first portion of the storage as inactive after the firmware update; (e.g., Eitner, col. 7 ll. 20-23: in FIG. 4, Base address A 418 corresponds to the active bank while Base address B 420 corresponds to the idle bank; col. 9 ll. 46-48: the bank switch command is received at step 508 after updating software; col. 8 ll. 44-46: the method switches banks by swapping address A 418 associated with flash bank A402 with the base address B420 associated with flash bank B404; col. 8 ll. 38-40: bank A and B swap base addresses and thereby become active or inactive) and
setting the second portion of the storage as active after the firmware update (see immediately above).
It would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to modify the performing of a firmware update by implementing firmware update instructions in memory circuitry taught by Chidambaram/Reed, to include setting the first portion of the storage as inactive after the firmware update and setting the second portion of the storage as active after the firmware update, as taught by Eitner, as Eitner would provide the advantages of a means to begin processing instructions from the updated firmware and a means to do so when the system is booted or reset. (See Eitner, col. 8 ll. 46-49, col. 9 ll. 46-49).
As to claim 20, Chidambaram/Reed discloses the apparatus of claim 16 (see rejection of claim 16 above), Chidambaram further discloses wherein the programmable circuitry is further configured (see below and note that software functionality is necessarily performed by a processor (programmable circuitry)]) to:
at least one of instantiate or execute the firmware update instructions (e.g., Chidambaram, p. 6 item 6 “Execute Compiler LFU Initialization routine…”: the compiler’s initialization routine (__TI_auto_init_Warm) [firmware update instructions] is invoked. This initializes any variables that have been indicated as needing initialization; p. 7 Fig. 4-4 and associated text and item 9: once the optimal LFU switchover point is identified, the LFU steps occur “(ActivateApp)” [also firmware update instructions])
swap after the at least one of instantiating or executing the firmware update instructions of the memory circuitry; (e.g., Chidambaram, p. 7 item 9: global interrupts are re-enabled. Now, ISRs and background task functions of the new firmware begin executing [a swap to the new firmware]).
Chidambaram does not explicitly disclose wherein the first firmware image further includes swap instructions and wherein the programmable circuitry is further configured to copy the swap instructions of the first firmware image to the memory circuitry; at least one of instantiate or execute the swap instructions of the memory circuitry after the at least one of instantiating or executing the firmware update instructions of the memory circuitry; and perform an A/B swap responsive to the at least one of instantiating or executing the swap instructions.
However, in an analogous art, Eitner discloses:
wherein the first firmware image further includes swap instructions (e.g., Eitner, Fig. 4 and associated text, col. 7 ll. 11-13, loadpicker logic 411 and 415 selects a valid software subsystem from flash bank A 402 or flash bank 4 404 [see figure, each bank has loadpicker logic, all logic in each bank is construed as an image])
swap instructions of the first firmware image (see immediately above)
at least one of instantiate or execute the swap instructions to perform the swap (e.g., Eitner, col. 7 ll. 35-40: load picker logic 411 [swap instructions] remaps the base address of the two flash banks. Flash bank A and flash bank B essentially swap base address mapping values and thereby become active or inactive; col. 7 ll. 57-59: if the download does occur properly then the base addresses are swapped and the active bank becomes flash bank B rather than flash bank A) and
perform an A/B swap responsive to the at least one of instantiating or executing the swap instructions (e.g., Eitner, col. 7 ll. 35-40: load picker logic 411 remaps the base address of the two flash banks. Flash bank A and flash bank B essentially swap base address mapping values and thereby become active or inactive; col. 7 ll. 57-59: if the download does occur properly then the base addresses are swapped and the active bank becomes flash bank B rather than flash bank A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first firmware image and swap after the at least one of instantiating or executing the firmware update instructions of the memory circuitry taught by Chidambaram such that the first firmware image includes swap instructions, the swap is performed by instantiating or executing the swap instructions and an A/B swap is performed responsive to instantiating or executing the swap instructions, as taught by Eitner, as Eitner would provide the advantages of a means of activating the new image and deactivating the old one and a means to ensure the new firmware is properly downloaded before the swap. (See Eitner, col. 7 ll. 40-64).
Further, in an analogous art, Reed discloses:
to copy the instructions to the memory circuitry (e.g., Reed, par. [0059]: an electronic device may include one or more storage media “(e.g., non-volatile memory such as magnetic disks, optical disks, read only memory (ROM), Flash memory, phase change memory, solid state drives (SSDs)). For instance, an electronic device may include non-volatile memory “(with slower read/write times)” and volatile memory “(e.g., dynamic random-access memory (DRAM), static random-access memory (SRAM)). the electronic device copies that part of the code [instructions] that is to be executed by the set of processors of that electronic device from the non-volatile memory into the volatile memory because volatile memory typically has faster read/write times) and
the instructions of the memory circuitry (see rejection of claim 1 above).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the firmware update instructions and swap instructions of Chidambaram/Eitner, such that these instructions are copied to the memory circuitry, as taught by Reed, as Reed would provide the advantage of a means of executing the instructions faster. (See Reed, par. [0059]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram (“Live Firmware Update Without Device Reset on C2000TM MCUs”) in view of Reed (US 2023/0350661) in further view of Huang et al. (US 2023/0185581) (art made of record – hereinafter Huang).
As to claim 11, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above), and further discloses the firmware update instructions of the memory circuitry (see rejection of claim 1 above) but does not explicitly disclose wherein the second firmware image further includes swap instructions, the programmable circuitry is further configured to: execute the swap instructions of the second portion of storage; firmware update instructions of the memory circuitry; and perform an A/B swap responsive to executing the swap instructions.
However, in an analogous art, Huang discloses:
wherein the second firmware image further includes swap instructions, (e.g., Huang, par. [0018]: different firmware versions or images are stored in separate flash memory banks; Fig. 9 and associated text, par. [0035]: (lines D.sub.2-O.sub.2) of the Boot_bank2 210, which reconfigures (step 309) the app pointer 405 to the memory address of the App_bank2 procedure 211 of the second bank) the programmable circuitry is further configured to:
execute the swap instructions of the second portion of storage after at least one or instantiating or executing the firmware update instructions (e.g., Huang, par. [0018]: instructions direct the function off the microcontroller 100; par. [0042]: using the RWW function of the controllers, the computer 1221 is able to perform live updating of the firmware in a non-active bank. A successful update can be verified and the flag parameter set to signal that bank swapping is available; par. [0036]: in response to a subsequent re-flash event, an indication in the flag parameter that the first bank is ready for control using an updated firmware image, a bank-swapping procedures as described herein is implemented to transfer control from Bank2 106 to Bank1 105; par. [0038]: code within the House-keeping o other procedures may initiate bank swapping based on criteria other than a successful updating of a firmware image) and
perform an A/B swap responsive to executing the swap instructions. (e.g., Huang, par. [0036]: in response to a subsequent re-flash event, an indication in the flag parameter that the first bank is ready for control using an updated firmware image, a bank-swapping procedures as described herein is implemented to transfer control from Bank2 106 to Bank1 105; Fig. 9 and associated text, par. [0035]: (lines D.sub.2-O.sub.2) of the Boot_bank2 210, which reconfigures (step 309) the app pointer 405 to the memory address of the App_bank2 procedure 211 of the second bank).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the second image and firmware update instructions in RAM memory of Chidambaram/Reed such that the second image that it includes swap instructions executed after the firmware update instructions to perform an A/B swap, as taught by Huang, as Huang would provide the advantages of a means of swapping control to the second bank after once it is ready to take control. or back to the first. (See Huang, par. [0037], par. [0018]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chidambaram (“Live Firmware Update Without Device Reset on C2000TM MCUs”) in view of Reed (US 2023/0350661) in further view of Goodman (US 2003/0163508) (art made of record – hereinafter Goodman).
As to claim 21, Chidambaram/Reed discloses the apparatus of claim 1 (see rejection of claim 1 above) but does not explicitly disclose wherein the second firmware image is inactive while the programmable circuitry copies the firmware update instructions to the memory circuitry.
However, in an analogous art, Goodman discloses:
wherein the second firmware image is inactive while the programmable circuitry copies the firmware update instructions to the memory circuitry (e.g., Goodman, par. [0025]: the firmware update “(i.e., incoming code image)” may be transmitted from a remote PC; par. [0029]: part of the incoming image 303 [second firmware image] is first copied loaded into the RAM 106, which enables the microprocessor 104 to execute the code update routines from the image 303. Subsequently, the code update routines are executed from the RAM 106 to rewrite the ROM 109 with the updated firmware [so the incoming image is inactive because the updated firmware is not executing yet]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Chidambaram/Reed such that the second firmware image is inactive while the programmable circuitry copies the firmware update instructions to the memory circuitry, as taught by Goodman, as Goodman would provide the advantage of a means for the system to operate normally while the update occurs. (See Goodman, par. [0006]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TODD AGUILERA/Primary Examiner, Art Unit 2192
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