DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Office Action is in response to claims filed 04/26/2024.
Claims 1-20 are pending.
Claim Objections
Claim 4 and 13 are objected to because the second limitation beginning with “routing” recites “physical medial layer transceiver.” Examiner believes “medial” is a typo and believes it should read as “physical media layer transceiver.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 recites the limitation "the Ethernet signal" in the third line of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purposes of compact prosecution, examiner interprets the QoS requirement of a type of a frame is decoded from any Ethernet signal.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, an abstract idea, and it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-7 are directed to a system and falls within the statutory class of machine. Claims 8-15 are directed to a method and falls within the statutory class of process. Claims 16-20 are directed to a system and falls within the statutory class of machine. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
Step 2A Prong 1:
Claims 1, 8, and 16: Claim 1 recites “identifying a first host system connected to a first interface port of the plurality of interface ports of the memory device, wherein the first interface port comprises a Peripheral Component Interconnect Express (PCIe) port, wherein the first host system runs a plurality of first virtual machines (VMs),” “identifying a second host system connected to a second interface port of the plurality of interface ports of the memory device, wherein the second interface port comprises an Ethernet port, wherein the second host system runs a plurality of second VMs,” “assigning a first subset of a plurality of virtual functions (VFs) associated with the memory device to the first host system,” “allocating a first range of logical block addresses (LBA) of the memory device to each VF of the first subset of virtual functions;” “assigning a second subset of the plurality of VFs associated with the memory device to the second host system,” “allocating a second range of LBAs of the memory device to each VF of the second subset of virtual functions,” “assigning a first VF of the first subset of the plurality of VFs to a first VM of the plurality of first VMs of the first host system,” and “assigning a second VF of the second subset of the plurality of VFs to a second VM of the plurality of second VMS of the second host system, wherein the first subset of the plurality of VFs corresponds to a plurality of virtual PCIe interfaces that share physical resources of the PCIe port and a second subset of the plurality of VFs corresponds to a plurality of virtual Ethernet interfaces that share physical resources of the Ethernet port” are considered a mental process. The limitations involve steps of observing, such as observing a host systems and VFs. Then, a judgement is formed based on the observation. It is understood that these limitations are to be performed within a computer environment, however, it can also entirely be performed in the mind.
Claim 8 recites similar subject matter and the limitations in claim 8 are also a mental process. The limitations are a mental process are “detecting, by a processing device, a first host system connected to a first interface port of the plurality of interface ports of the memory device, wherein the first interface port comprises a Peripheral Component Interconnect Express (PCIe) port, wherein the first host system is one of a plurality of host systems,” “detecting a second host system connected to a second interface port of the plurality of interface ports of the memory device, wherein the second interface port comprises an ethernet port, wherein the second host system is one of the plurality of host systems,” “assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using virtualization,” “allocating a first corresponding range of logical block addresses (LBA) of the memory device to each VF of the first subset of virtual functions,” “assigning a second subset of the plurality of VFs associated with the memory device to the second host system using the virtualization,” and “allocating a second corresponding range of LBAs of the memory device to each VF of the second subset of virtual functions.”
Claim 16 recites similar subject matter and the limitation in claim 16 is also a mental process. The limitation that is a mental process is “assigning a corresponding subset of a plurality of virtual functions (VFs) of the memory device to each host system of the plurality of host systems using virtualization.”
Therefore, Yes, claims 1, 8, and 16 recite a judicial exception. Step 2A Prong 2 will evaluate whether the claims integrate the judicial exception into a practical application.
Step 2A Prong 2:
Claims 1, 8, and 16: The judicial exception is not integrated into a practical application. Claims 1 and 16 recites the following additional elements – “a memory device,” “a plurality of interface ports operatively coupled with the memory device,” and “a processing device, operatively coupled with the memory device, to perform operations comprising.” These limitations are considered generic computing components used as a means to apply (MPEP § 2106.05(f)). Claim 16 additionally recites “providing access to a plurality of host systems that utilize a memory device using a plurality of interface ports of the memory device, wherein the plurality of interface ports comprise at least a Peripheral Component Interconnect Express (PCIe) port and an ethernet port, wherein each interface port of the plurality of interface ports connects to a separate host system of the plurality of host systems.” This limitation is considered field of use/technological environment (MPEP § 2106.05(h)) because it specifies the structure of the computing environment. These additional elements do not integrate the judicial exception into practical application.
Therefore, “Do the claims recite additional elements that integrate the judicial exception in a practical application?” No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluated the inquiries set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1, 8, and 16 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1, 8, and 16: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above, the additional elements only amount to generic computing used as a means to apply and field of use/technological environment. When reevaluating the additional elements, alone or in combination, no inventive concept that amounts to significantly more was found.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis with in the provided framework, claims 1, 8, and 16 do not recite eligible subject matter under 35 U.S.C. § 101.
With regard to claims 2, 9, and 18 it recites “wherein the plurality of VFs are represented by at least one of scalable input/output virtualization (S-IOV) VFs, single root input/output virtualization (SR-IOV), multi-physical function (Multi-PF) virtualization VFs, or multi-target network function virtualization (NFV) VFs.” This limitation is considered field of use/technological environment (MPEP § 2106.05(h)) because it limits how the VFs are represented in the computing environment. It does not integrate the judicial exception into a practical application, so the claims fail Step 2A Prong 2. When reevaluating the additional elements, alone or in combination, no inventive concept that amounts to significantly more was found. Therefore, the claims fail Step 2B. Therefore claims 2, 9, and 18 do not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claims 3, 10, and 19 it recites “wherein the first interface port and the second interface port are enabled by at least one of S-IOV or SR-IOV.” This limitation is considered field of use/technological environment (MPEP § 2106.05(h)) because it further limits the interface port in the computing environment. It does not integrate the judicial exception into a practical application, so the claims fail Step 2A Prong 2. When reevaluating the additional elements, alone or in combination, no inventive concept that amounts to significantly more was found. Therefore, the claims fail Step 2B. Therefore claims 3, 10, and 19 do not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claims 4 and 13 it recites “the operations further comprise: routing an Ethernet signal from the second interface port to a physical media layer transceiver of a memory sub-system controller” and “routing the ethernet signal from the physical medial layer transceiver to an ethernet media access controller of the memory sub-system controller.” These limitations are insignificant extra-solution activity of data transmission (MPEP § 2106.05(g)). The additional elements do not integrate the judicial exception into a practical application, so the claims fail Step 2A Prong 2. When reevaluating the insignificant extra-solution activities for an inventive concept that is significantly more, the claims do not add an inventive concept that is other than what is well understood, routine, and conventional in the field. MPEP § 2106.05(d)(II) lists that “Receiving or transmitting data over a network” is a well understood, routine, and conventional computer function. Routing data is a transmitting data over a network. Therefore, the claims fail Step 2B. Therefore claims 4 and 13 do not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claims 5 and 14 it recites “the processing device to further perform operations comprising: identifying, based on a header of a frame decoded from the Ethernet signal, a first type of the Ethernet frame.” Claim 14 additionally recites “identifying, based on the header in the ethernet signal, a second type of ethernet signal.” These limitations are a mental process because identifying involves observing and forming a judgement. Therefore, the claims recite a judicial exception and fail Step 2A Prong 1. The claims additionally recite “routing the first type of ethernet signal to a first offload engine running on a network adapter of an output interface” and “routing the second type of ethernet signal to a second offload engine running on the network adapter of the output interface.” These additional elements are insignificant extra-solution activity of data transmission (MPEP § 2106.05(g)). The additional elements do not integrate the judicial exception into a practical application, so the claims fail Step 2A Prong 2. When reevaluating the insignificant extra-solution activities for an inventive concept that is significantly more, the claims do not add an inventive concept that is other than what is well understood, routine, and conventional in the field. MPEP § 2106.05(d)(II) lists that “Receiving or transmitting data over a network” is a well understood, routine, and conventional computer function. Routing data is a transmitting data over a network. Therefore, the claims fail Step 2B. Therefore claims 5 and 14 do not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claims 6, it recites “the processing device to further perform operations comprising: assigning, based on a QoS (quality of service) requirement of a type of a frame decoded from the Ethernet signal, a priority level from a plurality of priority levels to the type of data.” This limitation is a mental process because assigning a priority level involves observing the QoS requirement and forming a judgement about the priority level. Therefore, claim 6 recites a judicial exception and fails Step 2A Prong 1. Claim 6 does not include any additional elements that integrate the judicial exception into a practical application, so the claims fail Step 2A Prong 2. When reevaluating the additional elements, alone or in combination, no inventive concept that amounts to significantly more was found. Therefore, claim 6 fails Step 2B. Therefore claims 6, do not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claims 7 and 15, it recites “wherein the plurality of host systems are provided access to the memory device without a separate switch or a separate bridge.” This limitation is considered field of use/technological environment (MPEP § 2106.05(h)) because it further limits the structure of the computing environment. It does not integrate the judicial exception into a practical application, so the claims fail Step 2A Prong 2. When reevaluating the additional elements, alone or in combination, no inventive concept that amounts to significantly more was found. Therefore, the claims fail Step 2B. Therefore claims 7 and 15 does not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claim 11, it recites “wherein a first subset of VFs correspond to a plurality of virtual PCIe interfaces that share physical resources of the PCIe port and a second subset of VFs correspond to a plurality of virtual ethernet interfaces that share physical resources of the ethernet port.” This limitation is field of use/technological environment (MPEP § 2106.05(h)) because it links the judicial exception to a particular technological environment. The limitation does not integrate the judicial exception into a practical application, so claim 11 fails Step 2A Prong 2. When reevaluating the field of use/technological environment, alone or in combination with other limitations, no inventive concept that amounts to significantly more was found. Therefore, claim 11 fails Step 2B. Therefore claim 11 does not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claim 12 and 20 it recites “further comprising: assigning a first VF of the first subset of the plurality of VFs to a first VM of the plurality of first VMs of the first host system” and “assigning a second VF of the second subset of the plurality of VFs to a second VM of the plurality of second VMS of the second host system.” These limitations are considered a mental process because assigning VFs involve observing and forming a judgement. Therefore, the claims recite a judicial exception and fail Step 2A Prong 1. The claims do not include any additional elements that integrate the judicial exception into a practical application, so the claims fail Step 2A Prong 2. When reevaluating the limitations, alone or in combination, no inventive concept that amounts to significantly more was found. Therefore, the claims fail Step 2B. Therefore claims 12 and 20 do not recite patent eligible subject matter under 35 U.S.C. 101.
With regard to claim 17 it recites “wherein for each host system of the plurality of host systems, the processing device to further perform operations comprising: assigning a corresponding range of logical block addresses (LBA) of the memory device to each virtual function of the corresponding subset of virtual functions assigned to the respective host system.” This limitation is a mental process because assigning a range of LBA involves observing and forming a judgement. Therefore, claim 17 recites a judicial exception and fails Step 2A Prong 1. The claims do not include any additional elements that integrate the judicial exception into a practical application, so claim 17 fails Step 2A Prong 2. When reevaluating the additional elements, alone or in combination, no inventive concept that amounts to significantly more was found. Therefore, claim 17 fails Step 2B. Therefore claim 17 does not recite patent eligible subject matter under 35 U.S.C. 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maroney et al. Pat. No. US 20200192848 A1 (hereafter Maroney) in view of Berman et al. Pat. No. US 20220150164 A2 (hereafter Berman).
With regard to claim 1, Maroney teaches a system comprising (¶ [0020] states “FIG. 1 illustrates an example computing system 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure.”):
a memory device (¶ [0020] states “The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.”);
a plurality of interface ports operatively coupled with the memory device (¶ [0014] states “The multiple interface ports of the memory sub-system can be accessed concurrently with each other, such that the multiple host systems can access the memory sub-system at the same time.” See FIG. 1 Multiple SR-IOV Ports Component 113 and FIG. 2 Port 250A-D);
and a processing device, operatively coupled with the memory device, to perform operations comprising (¶ [0031] states “The memory sub-system controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119.”):
identifying a first host system connected to a first interface port of the plurality of interface ports of the memory device, wherein the first interface port comprises a Peripheral Component Interconnect Express (PCIe) port, wherein the first host system runs a plurality of first virtual machines (VMs) (¶ [0051] states “At operation 410, the processing logic detects a first host system that is one of the multiple host systems that can be connected to a memory device. The first host system is connected to a first interface port of multiple interface ports of the memory device. In one implementation, each of the multiple interface ports can be a Peripheral Component Interconnect Express (PCIe) port.” ¶ [0012] states “Multiple hosts (e.g., different system on a chip (SOC) devices) with multiple virtual machines can interact with the memory sub-system.”);
identifying a second host system connected to a second interface port of the plurality of interface ports of the memory device, wherein the second interface port comprises an Ethernet port, wherein the second host system runs a plurality of second VMs (¶ [0053] states “At operation 420, the processing logic detects a second host system that is one of the multiple host systems that can be connected to a memory device. The second host system is connected to a second interface port of multiple interface ports of the memory device, the second interface port is different than the first interface port of the memory device.” ¶ [0012] states “Multiple hosts (e.g., different system on a chip (SOC) devices) with multiple virtual machines can interact with the memory sub-system.” ¶ [0053] states “the second interface port is different than the first interface port of the memory device”);
assigning a first subset of a plurality of virtual functions (VFs) associated with the memory device to the first host system (¶ [0054] states “At operation 430, the processing logic assigns a first subset of a the total virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV).”);
allocating a first range of logical block addresses (LBA) of the memory device to each VF of the first subset of virtual functions (¶ [0055] states “At operation 440, the processing logic allocates a first corresponding range of logical block addresses (LBA) of the memory device to each VF of the first subset of virtual functions assigned to the first host system.”);
assigning a second subset of the plurality of VFs associated with the memory device to the second host system (¶ [0058] states “At operation 450, the processing logic assigns a second subset of the total VFs associated with the memory device to the second host system using root input/output virtualization (SR-IOV).”);
allocating a second range of LBAs of the memory device to each VF of the second subset of virtual functions (¶ [0059] states “At operation 460, the processing logic allocates a second corresponding range of logical block addresses (LBA) of the memory device to each VF of the second subset of virtual functions assigned to the second host system.”);
assigning a first VF of the first subset of the plurality of VFs to a first VM of the plurality of first VMs of the first host system (¶ [0063] states “at operation 540, the processing logic assigns a first VF of the multiple virtual functions of the PCIe port to the first VM of the host SOC”);
and assigning a second VF of the second subset of the plurality of VFs to a second VM of the plurality of second VMS of the second host system (¶ [0063] states “at operation 550, the processing logic assigns a second VF of the multiple virtual functions of the PCIe port to the second VM of the host SOC.”),
wherein the first subset of the plurality of VFs corresponds to a plurality of virtual PCIe interfaces that share physical resources of the PCIe port (¶ [0054] states “the first subset of VFs corresponds to a group of virtual PCIe interfaces that share physical resources of each interface port”)
and a second subset of the plurality of VFs corresponds to a plurality of virtual Ethernet interfaces that share physical resources of the Ethernet port (¶ [0058] states “At operation 450, the processing logic assigns a second subset of the total VFs associated with the memory device to the second host system using root input/output virtualization (SR-IOV). In implementations, the first subset of VFs corresponds to a group of virtual PCIe interfaces that share physical resources of each interface port.” Examiner’s Note: it is understood that the underlined portion is a typo and should read “second subset of VFs” because ¶ [0058] and FIG. 4 block 450 is with regards to the “second subset of VFs” and “the first subset of VFs corresponds to a group of virtual PCIe interfaces” was already explained in ¶ [0054]).
Although Maroney ¶ [0053] teaches that “the second interface port is different than the first interface port of the memory device,” Maroney does not explicitly teach the second interface port comprising an Ethernet port and virtual Ethernet interfaces.
However, in an analogous art, Berman teaches identifying a second host system connected to a second interface port of the plurality of interface ports of the memory device, wherein the second interface port comprises an Ethernet port, wherein the second host system runs a plurality of second VMs (¶ [0027] states “Another example would be the transferring of data to and from a GPU 24 2 to high speed Ethernet ports 1 9 10 to reach other devices.” See FIG. 1).
and a second subset of the plurality of VFs corresponds to a plurality of virtual Ethernet interfaces that share physical resources of the Ethernet port (¶ [0027] states “Another example would be the transferring of data to and from a GPU 24 2 to high speed Ethernet ports 1 9 10 to reach other devices.” See FIG. 1. ¶ [0028] states “The MPSC SOC 50 is providing network connectivity with an Nvidia GPU complex via a NVLink™ interface 51, and can provide, for example, connectivity to an Ethernet interface 55 running a NVMf protocol.” See FIG. 2).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date to combine the ethernet ports and ethernet interface of Berman with the interface ports and memory subsystem of Maroney. As a result, the interface ports of Maroney include PCIe ports and ethernet ports. A person having ordinary skill in the art would have been motivated to make this combination because it “allows the combining of very high speed protocols and the speed up of the transfer of data between the protocols” (¶ [0027]).
With regard to claim 2, Maroney and Berman teach the system of claim 1. Maroney additionally teaches wherein the plurality of VFs are represented by at least one of
scalable input/output virtualization (S-IOV) VFs (),
single root input/output virtualization (SR-IOV) (¶ [0014] states “Each of the multiple interface ports supports single root virtualization. For example, multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”),
multi-physical function (Multi-PF) virtualization VFs,
or multi-target network function virtualization (NFV) VFs.
With regard to claim 3, Maroney and Berman teach the system of claim 2. Maroney additionally teaches wherein the first interface port and the second interface port are enabled by at least one of S-IOV or SR-IOV (¶ [0014] states “Each of the multiple interface ports supports single root virtualization. For example, multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”).
With regard to claim 4, Maroney and Berman teach the system of claim 1. Berman additionally teaches the operations further comprise: routing an Ethernet signal from the second interface port to a physical media layer transceiver of a memory sub-system controller (¶ [0045] states “The Transport 717, MAC 718 and PHY 719 all work together to provide the necessary connectivity to another Ethernet device (i.e. configuration of the number of interfaces used for the connection, speed of the interface, the particular Transport which may comprise one or more of the following: RDMA, RoCEv2, UDP, TCP, etc).” See FIG. 7. Examiner’s Note: the second interface port connects to the PHY 719. The physical media layer transceiver is within the PHY);
and routing the ethernet signal from the physical medial layer transceiver to an ethernet media access controller of the memory sub-system controller (¶ [0045] states “The Transport 717, MAC 718 and PHY 719 all work together to provide the necessary connectivity to another Ethernet device (i.e. configuration of the number of interfaces used for the connection, speed of the interface, the particular Transport which may comprise one or more of the following: RDMA, RoCEv2, UDP, TCP, etc).” See FIG. 7 733. Examiner’s Note: FIG. 7 wire 733 connects PHY to MAC 718. Therefore, the ethernet signal is routed from the physical media layer transceiver in the PHY to the MAC).
With regard to claim 7, Maroney and Berman teach the system of claim 1. Maroney additionally teaches wherein the plurality of host systems are provided access to the memory device without a separate switch or a separate bridge (¶ [0014] states “multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”).
With regard to claim 8, Maroney teaches a method comprising (¶ [0050] states “FIG. 4 is a flow diagram of an example method of managing multiple SR-IOV enabled interface ports of a memory sub-system, in accordance with some embodiments of the present disclosure.”):
detecting, by a processing device, a first host system connected to a first interface port of the plurality of interface ports of the memory device, wherein the first interface port comprises a Peripheral Component Interconnect Express (PCIe) port, wherein the first host system is one of a plurality of host systems (¶ [0051] states “At operation 410, the processing logic detects a first host system that is one of the multiple host systems that can be connected to a memory device. The first host system is connected to a first interface port of multiple interface ports of the memory device. In one implementation, each of the multiple interface ports can be a Peripheral Component Interconnect Express (PCIe) port.” ¶ [0012] states “Multiple hosts (e.g., different system on a chip (SOC) devices) with multiple virtual machines can interact with the memory sub-system.”);
detecting a second host system connected to a second interface port of the plurality of interface ports of the memory device, wherein the second interface port comprises an ethernet port, wherein the second host system is one of the plurality of host systems (¶ [0053] states “At operation 420, the processing logic detects a second host system that is one of the multiple host systems that can be connected to a memory device. The second host system is connected to a second interface port of multiple interface ports of the memory device, the second interface port is different than the first interface port of the memory device.” ¶ [0012] states “Multiple hosts (e.g., different system on a chip (SOC) devices) with multiple virtual machines can interact with the memory sub-system.”);
assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using virtualization (¶ [0054] states “the processing logic assigns a first subset of a the total virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV).”);
allocating a first corresponding range of logical block addresses (LBA) of the memory device to each VF of the first subset of virtual functions (¶ [0055] states “At operation 440, the processing logic allocates a first corresponding range of logical block addresses (LBA) of the memory device to each VF of the first subset of virtual functions assigned to the first host system.”);
assigning a second subset of the plurality of VFs associated with the memory device to the second host system using the virtualization (¶ [0058] states “At operation 450, the processing logic assigns a second subset of the total VFs associated with the memory device to the second host system using root input/output virtualization (SR-IOV).”);
and allocating a second corresponding range of LBAs of the memory device to each VF of the second subset of virtual functions (¶ [0059] states “At operation 460, the processing logic allocates a second corresponding range of logical block addresses (LBA) of the memory device to each VF of the second subset of virtual functions assigned to the second host system.”).
Although Maroney ¶ [0053] teaches that “the second interface port is different than the first interface port of the memory device,” Maroney does not explicitly teach the second interface port comprising an Ethernet port.
However, in an analogous art, Berman teaches detecting a second host system connected to a second interface port of the plurality of interface ports of the memory device, wherein the second interface port comprises an ethernet port, wherein the second host system is one of the plurality of host systems (¶ [0027] states “Another example would be the transferring of data to and from a GPU 24 2 to high speed Ethernet ports 1 9 10 to reach other devices.” See FIG. 1).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date to combine the ethernet ports of Berman with the interface ports and memory subsystem of Maroney. As a result, the interface ports of Maroney include PCIe ports and ethernet ports. A person having ordinary skill in the art would have been motivated to make this combination because it “allows the combining of very high speed protocols and the speed up of the transfer of data between the protocols” (¶ [0027]).
With regard to claim 9, Maroney and Berman teach the method of claim 8. Maroney additionally teaches wherein the plurality of VFs are represented by at least one of
scalable input/output virtualization (S-IOV),
single root input/output virtualization (SR-IOV) (¶ [0014] states “Each of the multiple interface ports supports single root virtualization. For example, multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”),
multi-physical function (Multi-PF) virtualization,
or multi-target network function virtualization (NFV).
With regard to claim 10, Maroney and Berman teach the method of claim 9. Maroney additionally teaches wherein the first interface port and the second interface port are S-IOV enabled or SR-IOV enabled (¶ [0014] states “Each of the multiple interface ports supports single root virtualization. For example, multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”).
With regard to claim 11, Maroney and Berman teach the method of claim 8. Maroney additionally teaches wherein a first subset of VFs correspond to a plurality of virtual PCIe interfaces that share physical resources of the PCIe port (¶ [0054] states “the first subset of VFs corresponds to a group of virtual PCIe interfaces that share physical resources of each interface port.” ¶ [0014] states “An interface port can be a PCIe port or a physical port.”)
and a second subset of VFs correspond to a plurality of virtual ethernet interfaces that share physical resources of the ethernet port (¶ [0058] states “At operation 450, the processing logic assigns a second subset of the total VFs associated with the memory device to the second host system using root input/output virtualization (SR-IOV). In implementations, the first subset of VFs corresponds to a group of virtual PCIe interfaces that share physical resources of each interface port.” Examiner’s Note: it is understood that the underlined portion is a typo and should read “second subset of VFs” because ¶ [0058] and FIG. 4 block 450 is with regards to the “second subset of VFs” and “the first subset of VFs corresponds to a group of virtual PCIe interfaces” was already explained in ¶ [0054]).
Berman additionally teaches and a second subset of VFs correspond to a plurality of virtual ethernet interfaces that share physical resources of the ethernet port (¶ [0027] states “Another example would be the transferring of data to and from a GPU 24 2 to high speed Ethernet ports 1 9 10 to reach other devices.” See FIG. 1. ¶ [0028] states “The MPSC SOC 50 is providing network connectivity with an Nvidia GPU complex via a NVLink™ interface 51, and can provide, for example, connectivity to an Ethernet interface 55 running a NVMf protocol.” See FIG. 2).
With regard to claim 12, Maroney and Berman teach the method of claim 8. Maroney additionally teaches further comprising: assigning a first VF of the first subset of the plurality of VFs to a first VM of the plurality of first VMs of the first host system (¶ [0063] states “at operation 540, the processing logic assigns a first VF of the multiple virtual functions of the PCIe port to the first VM of the host SOC”);
and assigning a second VF of the second subset of the plurality of VFs to a second VM of the plurality of second VMS of the second host system (¶ [0063] states “at operation 550, the processing logic assigns a second VF of the multiple virtual functions of the PCIe port to the second VM of the host SOC.”).
With regard to claim 13, Maroney and Berman teach the method of claim 8. Berman additionally teaches further comprising: routing an ethernet signal from the second interface port to a physical media layer transceiver of a memory sub-system controller (¶ [0045] states “The Transport 717, MAC 718 and PHY 719 all work together to provide the necessary connectivity to another Ethernet device (i.e. configuration of the number of interfaces used for the connection, speed of the interface, the particular Transport which may comprise one or more of the following: RDMA, RoCEv2, UDP, TCP, etc).” See FIG. 7. Examiner’s Note: the second interface port connects to the PHY 719. The physical media layer transceiver is within the PHY);
and routing the ethernet signal from the physical medial layer transceiver to an ethernet media access controller of the memory sub-system controller (¶ [0045] states “The Transport 717, MAC 718 and PHY 719 all work together to provide the necessary connectivity to another Ethernet device (i.e. configuration of the number of interfaces used for the connection, speed of the interface, the particular Transport which may comprise one or more of the following: RDMA, RoCEv2, UDP, TCP, etc).” See FIG. 7 733. Examiner’s Note: FIG. 7 wire 733 connects PHY to MAC 718. Therefore, the ethernet signal is routed from the physical media layer transceiver in the PHY to the MAC).
With regard to claim 15, Maroney and Berman teach the method of claim 8. Maroney additionally teaches wherein the plurality of host systems are provided access to the memory device without a separate switch or a separate bridge (¶ [0014] states “multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”).
With regard to claim 16, Maroney teaches a system comprising (¶ [0020] states “FIG. 1 illustrates an example computing system 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure.”):
a memory device (¶ [0020] states “The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.”);
a plurality of interface ports operatively coupled with the memory device (¶ [0014] states “The multiple interface ports of the memory sub-system can be accessed concurrently with each other, such that the multiple host systems can access the memory sub-system at the same time.” See FIG. 1 Multiple SR-IOV Ports Component 113 and FIG. 2 Port 250A-D);
and a processing device, operatively coupled with the memory device, to perform operations comprising (¶ [0031] states “The memory sub-system controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119.”):
providing access to a plurality of host systems that utilize a memory device using a plurality of interface ports of the memory device (¶ [0014] states “Aspects of the present disclosure address the above and other deficiencies by introducing multiple interface ports in a memory sub-system, such that the memory sub-system can be shared for storage by multiple host systems.”),
wherein the plurality of interface ports comprise at least a Peripheral Component Interconnect Express (PCIe) port and an ethernet port (¶ [0014] states “An interface port can be a PCIe port or a physical port.” ¶ [0053] states “the second interface port is different than the first interface port of the memory device.”),
wherein each interface port of the plurality of interface ports connects to a separate host system of the plurality of host systems (¶ [0041] states “a PCIe interface can be utilized between each host system and interface port so that each host system 210-240 is coupled with a different interface port 250A-D of the memory sub-system 110.” See FIG. 2. Examiner’s Note: FIG. 2 shows different Host Systems 210-240 connecting to different interface ports 250A-D);
and assigning a corresponding subset of a plurality of virtual functions (VFs) of the memory device to each host system of the plurality of host systems using virtualization (¶ [0054] states “the processing logic assigns a first subset of a the total virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV).”).
Although Maroney ¶ [0053] teaches that “the second interface port is different than the first interface port of the memory device,” Maroney does not explicitly teach the second interface port comprising an Ethernet port and virtual Ethernet interfaces.
However, in an analogous art, Berman teaches wherein the plurality of interface ports comprise at least a Peripheral Component Interconnect Express (PCIe) port and an ethernet port (¶ [0027] states “Another example would be the transferring of data to and from a GPU 24 2 to high speed Ethernet ports 1 9 10 to reach other devices.” See FIG. 1).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date to combine the ethernet ports and ethernet interface of Berman with the interface ports and memory subsystem of Maroney. As a result, the interface ports of Maroney include PCIe ports and ethernet ports. A person having ordinary skill in the art would have been motivated to make this combination because it “allows the combining of very high speed protocols and the speed up of the transfer of data between the protocols” (¶ [0027]).
With regard to claim 17, Maroney and Berman teach the system of claim 16. Maroney additionally teaches wherein for each host system of the plurality of host systems, the processing device to further perform operations comprising: assigning a corresponding range of logical block addresses (LBA) of the memory device to each virtual function of the corresponding subset of virtual functions assigned to the respective host system (¶ [0039] states “In some implementations, memory sub-system controller 115 can determine that a group of virtual functions are assigned to an interface port with a particular LBA range for each virtual function” and “In some embodiments, different LBA ranges (e.g., different amount of logical block addresses that are mapped to a corresponding different amount of physical block addresses) can be assigned to different virtual functions.” ¶ [0043] states “each VF 251A-L of memory sub-system 110 can be allocated a corresponding range of LBA of memory devices 130-140”).
With regard to claim 18, Maroney and Berman teach the system of claim 16. Maroney additionally teaches wherein the virtualization comprises at least one of
scalable input/output virtualization (S-IOV),
single root input/output virtualization (SR-IOV) (¶ [0014] states “Each of the multiple interface ports supports single root virtualization. For example, multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”),
multi-physical function (Multi-PF) virtualization,
or multi-target network function virtualization (NFV).
With regard to claim 19, Maroney and Berman teach the system of claim 18. Maroney additionally teaches wherein the PCIe port and the ethernet port are S-IOV or SR-IOV enabled (¶ [0014] states “Each of the multiple interface ports supports single root virtualization. For example, multiple single root input/output virtualization (SR-IOV) enabled interface ports can be provided by the memory sub-system to enable access to multiple host systems without a need for a separate switch.”).
Berman additionally teaches wherein the PCIe port and the ethernet port are S-IOV or SR-IOV enabled (¶ [0027] states “Another example would be the transferring of data to and from a GPU 24 2 to high speed Ethernet ports 1 9 10 to reach other devices.” See FIG. 1).
With regard to claim 20, Maroney and Berman teach the system of claim 16. Maroney additionally teaches the processing device to further perform operations comprising: assigning a first VF of the first subset of the plurality of VFs to a first VM of the plurality of first VMs of the first host system (¶ [0063] states “at operation 540, the processing logic assigns a first VF of the multiple virtual functions of the PCIe port to the first VM of the host SOC”);
and assigning a second VF of the second subset of the plurality of VFs to a second VM of the plurality of second VMS of the second host system (¶ [0063] states “at operation 550, the processing logic assigns a second VF of the multiple virtual functions of the PCIe port to the second VM of the host SOC.”).
Claim(s) 5-6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maroney in view of Berman and further in view of Ong et al. Pat. No. US 20230096468 A1 (hereafter Ong).
With regard to claim 5, Maroney and Berman teach the system of claim 4. Berman additionally teaches routing the first type of ethernet signal to a first offload engine running on a network adapter of an output interface (¶ [0043] states “The Offload engines 715 are used to provide hardware assist on the data coming into and out of the MPSC.” See FIG. 7. Examiner’s Note: the ethernet controller 704 is a network adapter of an output interface).
Maroney and Berman do not explicitly teach identifying a first type of ethernet frame.
However, in an analogous art, Ong teaches the processing device to further perform operations comprising: identifying, based on a header of a frame decoded from the Ethernet signal, a first type of the Ethernet frame (¶ [0061] states “The frame of each packet includes … a length/type field (e.g., 2 octets)” and “The length/type field indicates either the number of MAC client data octets contained in the subsequent MAC client data field of the basic frame (e.g., a “length interpretation”) or the Ethertype of the MAC client protocol (e.g., a “type interpretation”).” Examiner’s Note: the Ethertype identifies the type of ethernet frame);
routing the first type of ethernet signal to a first offload engine running on a network adapter of an output interface (¶ [0035] states “The NIC 468 includes a host interface 467, packet engines (PEs) 404-M and 404-N (collectively referred to as “packet engines 404”, “PE 404”, and/or the like).” ¶ [0037] states “The PEs 404 is/are a HW components that offload protocol processing from the host platform 490, places received data payloads directly into queues 472 with little or no host processor involvement.” ¶ [0046] states “The Rx packet/frame (or the packet header) then goes through a packet processing pipeline where parsing, switching, ACL, and classification/filtering takes place. For the filtering, the MAC 405 forwards the packet to one or more Rx filters, and if the packet matches (pre-programmed or configured) criteria of the Rx filter(s), the packet is forwarded to the Rx buffer 411. As examples, the Rx filters can include Ethertype.” ¶ [0047] states “the Rx frame steering function 422 detects the incoming Rx frames and steers the Rx frames to the appropriate queue 411. The Rx frame steering function 422 uses various matching criteria of any of the aforementioned filtering mechanisms (or combinations thereof), packet inspection/snooping techniques, and/or some other packet steering mechanism/technique.” See FIG. 4. Examiner’s Note: packet engines are offload engines. The Rx frame steering function 422 determines which queue 411 an incoming packet should be placed in. Based on the queue 411-M, a corresponding packet engine 404-M then performs processing that offloads processing from the host platform. The Rx frame steering function 422 uses Ethertype to perform filtering, classification, and routing, so the first type of ethernet signal is appropriately routed to an offload engine).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date to combine the ethernet frame classification and frame steering to packet engine of Ong with the memory subsystem of Maroney and the multi-protocol interfaces of Berman. As a result, different types of ethernet signals received by the PHY of Berman can be processed by appropriate offload engines of Ong. A person having ordinary skill in the art would have been motivated to make this combination because “The capabilities and implementations discussed herein decrease the amount of jitter resulting from Rx packet/frame processing, which improves the function of the computing device/component itself by improving resource consumption efficiencies of such devices/components” (¶ [0023]).
With regard to claim 6, Maroney and Berman teach the system of claim 1. Maroney and Berman do not explicitly teach assigning a priority level.
However, in an analogous art, Ong teaches the processing device to further perform operations comprising: assigning, based on a QoS (quality of service) requirement of a type of a frame decoded from the Ethernet signal, a priority level from a plurality of priority levels to the type of data (¶ [0043] states “TSN-based NICs 468 have eight HW queues 411, each belonging to a particular traffic class (e.g., TC7 to TC0), where traffic class 7 (TC7) to traffic class 5 (TC5) are assigned to queues 411 for handling higher priority data streams (e.g., cyclic data streams) and TC0 to TC4 are assigned to lower priority data streams (e.g., non-cyclic (or acyclic) data streams).” ¶ [0047] states “In one example, the Rx frame steering function 422 steers Rx packets/frames to a buffer 411 according to priority information included in a VLAN tag of each packet/frame.” ¶ [0264] states “the term “Quality of Service” or “QoS” can be used interchangeably with the term “Class of Service” or “CoS”.” ¶ [0063] states “The TPID includes an EtherType value that is used to identify the frame as a tagged frame and to select the correct tag decoding functions.” ¶ [0064] states “The PCP and/or CoS value maps to a frame priority level.” In FIG. 5, see how TPID and PCP are in VLAN tag 510. Examiner’s Note: Rx frame steering 422 steers a packet into a buffer/queue 411 based on priority information. Each queue 411 handles different priority levels, so steering a frame to one of the queues is assigning a priority level to the type of data. Traffic classes are a type of data. The PCP/CoS/QoS value maps to a priority level and is associated with an Ethertype in the TPID in the VLAN tag, so the assigning of priority is based on a QoS requirement of a type of frame).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date to combine the steering of ethernet packets based on priority information that is further based on a QoS of Ong with the memory subsystem of Maroney and the ethernet controller and ethernet ports of Berman. A person having ordinary skill in the art would have been motivated to make this combination because “The capabilities and implementations discussed herein decrease the amount of jitter resulting from Rx packet/frame processing, which improves the function of the computing device/component itself by improving resource consumption efficiencies of such devices/components” (¶ [0023]).
With regard to claim 14, Maroney and Berman teach the method of claim 13. Berman additionally teaches routing the first type of ethernet signal to a first offload engine running on a network adapter of an output interface (¶ [0043] states “The Offload engines 715 are used to provide hardware assist on the data coming into and out of the MPSC.” See FIG. 7. Examiner’s Note: the ethernet controller 704 is a network adapter of an output interface);
and routing the second type of ethernet signal to a second offload engine running on the network adapter of the output interface (¶ [0043] states “The Offload engines 715 are used to provide hardware assist on the data coming into and out of the MPSC.” See FIG. 7. Examiner’s Note: the ethernet controller 704 is a network adapter of an output interface).
Maroney and Berman do not explicitly teach identifying a first type of ethernet frame.
However, in an analogous art, Ong teaches further comprising: identifying, based on a header in the ethernet signal, a first type of ethernet signal (¶ [0061] states “The frame of each packet includes … a length/type field (e.g., 2 octets)” and “The length/type field indicates either the number of MAC client data octets contained in the subsequent MAC client data field of the basic frame (e.g., a “length interpretation”) or the Ethertype of the MAC client protocol (e.g., a “type interpretation”).” Examiner’s Note: the Ethertype identifies the type of ethernet frame);
routing the first type of ethernet signal to a first offload engine running on a network adapter of an output interface (¶ [0035] states “The NIC 468 includes a host interface 467, packet engines (PEs) 404-M and 404-N (collectively referred to as “packet engines 404”, “PE 404”, and/or the like).” ¶ [0037] states “The PEs 404 is/are a HW components that offload protocol processing from the host platform 490, places received data payloads directly into queues 472 with little or no host processor involvement.” ¶ [0046] states “The Rx packet/frame (or the packet header) then goes through a packet processing pipeline where parsing, switching, ACL, and classification/filtering takes place. For the filtering, the MAC 405 forwards the packet to one or more Rx filters, and if the packet matches (pre-programmed or configured) criteria of the Rx filter(s), the packet is forwarded to the Rx buffer 411. As examples, the Rx filters can include Ethertype.” ¶ [0047] states “the Rx frame steering function 422 detects the incoming Rx frames and steers the Rx frames to the appropriate queue 411. The Rx frame steering function 422 uses various matching criteria of any of the aforementioned filtering mechanisms (or combinations thereof), packet inspection/snooping techniques, and/or some other packet steering mechanism/technique.” See FIG. 4. Examiner’s Note: packet engines are offload engines. The Rx frame steering function 422 determines which queue 411 an incoming packet should be placed in. Based on the queue 411-M, a corresponding packet engine 404-M then performs processing that offloads processing from the host platform. The Rx frame steering function 422 uses Ethertype to perform filtering, classification, and routing, so the first type of ethernet signal is appropriately routed to an offload engine);
identifying, based on the header in the ethernet signal, a second type of ethernet signal (¶ [0061] states “The frame of each packet includes … a length/type field (e.g., 2 octets)” and “The length/type field indicates either the number of MAC client data octets contained in the subsequent MAC client data field of the basic frame (e.g., a “length interpretation”) or the Ethertype of the MAC client protocol (e.g., a “type interpretation”).” Examiner’s Note: the Ethertype identifies the type of ethernet frame. There are multiples types represented by Ethertype);
and routing the second type of ethernet signal to a second offload engine running on the network adapter of the output interface (¶ [0035] states “The NIC 468 includes a host interface 467, packet engines (PEs) 404-M and 404-N (collectively referred to as “packet engines 404”, “PE 404”, and/or the like).” ¶ [0037] states “The PEs 404 is/are a HW components that offload protocol processing from the host platform 490, places received data payloads directly into queues 472 with little or no host processor involvement.” ¶ [0046] states “The Rx packet/frame (or the packet header) then goes through a packet processing pipeline where parsing, switching, ACL, and classification/filtering takes place. For the filtering, the MAC 405 forwards the packet to one or more Rx filters, and if the packet matches (pre-programmed or configured) criteria of the Rx filter(s), the packet is forwarded to the Rx buffer 411. As examples, the Rx filters can include Ethertype.” ¶ [0047] states “the Rx frame steering function 422 detects the incoming Rx frames and steers the Rx frames to the appropriate queue 411. The Rx frame steering function 422 uses various matching criteria of any of the aforementioned filtering mechanisms (or combinations thereof), packet inspection/snooping techniques, and/or some other packet steering mechanism/technique.” See FIG. 4. Examiner’s Note: packet engines are offload engines. the Rx frame steering function 422 determines which queue 411 an incoming packet should be placed in. Based on the queue 411-M, a corresponding packet engine 404-M then performs processing that offloads processing from the host platform. The Rx frame steering function 422 uses Ethertype to perform filtering, classification, and routing, so the first type of ethernet signal is appropriately routed to an offload engine. There is a plurality of packet engines such as packet engine 404-M and 404-N. Each packet engine has a corresponding queue such as 411-M and 411-N).
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date to combine the ethernet frame classification and frame steering to packet engine of Ong with the memory subsystem of Maroney and the multi-protocol interfaces of Berman. As a result, different types of ethernet signals received by the PHY of Berman can be processed by appropriate offload engines of Ong. A person having ordinary skill in the art would have been motivated to make this combination because “The capabilities and implementations discussed herein decrease the amount of jitter resulting from Rx packet/frame processing, which improves the function of the computing device/component itself by improving resource consumption efficiencies of such devices/components” (¶ [0023]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150339250 A1
teaches
ETHERNET OVER USB INTERFACES WITH FULL-DUPLEX DIFFERENTIAL PAIRS
US 20210232528 A1
teaches
Features of claims 2-3, 9-10, and 18-19 such as SR-IOV and S-IOV
US 20200028749 A1
teaches
Features of claims 2, 9, and 18 such as network function virtualization
US 20220066807 A1
teaches
Features of claims 2, 9, and 18 such as multi-physical function
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/PETER LI YUAN/Examiner, Art Unit 2197
/MELISSA A HEADLY/Examiner, Art Unit 2197
Prosecution Insights