DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 03/19/2026 have been fully considered but they are not persuasive.
Applicants argues, see REMARKS page 7, “The stacked TG switch illustrated in FIG. 5 is part of the charge pump of FIG. 3, and is not "analog input circuitry."
The Office respectfully disagrees. Applicants arguments fails address why the “Stacked TG switch” in Harikumar2014’s Fig. 5 is not functionally the claimed "analog input circuitry." While Fig. 3 depicted the arrangements/integration of respective electronic components of the charge pump and the “Stacked TG switch,” Fig. 5 expressively depicts the charge pump and the “Stacked TG switch” as separate circuitries. Further, as required by the claim language, "analog input circuitry" receives an analog signal and outputs the analog signal as “analog input signal to signal conversion circuitry.” Similarly, the “Stacked TG switch” in Harikumar2014’s Fig. 1 and 5, receives analog input signal at , VIP, VIN (Fig. 1) or Vin (Fig. 5) node and provides the analog input signal to signal conversion circuitry, SAR ADC comprising at least elements from DAC to SAR in Fig. 1. Therefore, the claimed “analog input circuitry” and the “Stacked TG switch” provide eqaulivent functionality.
Applicants argues, see REMARKS page 7-8, regarding Harikumar2016’s teaches fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
The Office maintains that the combination of Harikumar2104 in view of Harikumar2106 discloses all as applied to claimed limitations of at least the independent claims 1, 8, and 15 as addressed previously and detailed below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Harikumar et al. (NPL titled "Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump," 2014 NORCHIP, Tampere, Finland, 2014, pp. 1-4, hereafter referred to as Harikumar2014) in view of Harikumar et al. (NPL titled "A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 8, 2016, pp. 743-747, hereafter referred to as Harikumar2016).
Regarding Claim 1 and 15, Harikumar2014 discloses:
A system and a method (Fig. 1), comprising:
analog input circuitry (Fig. 1, 5: “VIP, VIN Sample” switch; “Stacked TG switch”) configured to supply an analog input signal to signal conversion circuitry (Fig. 1: Stacked TG switch supply an analog input signal, Vin, to signal conversion circuitry, SAR ADC, comprising at least elements from DAC to SAR in Fig. 1);
charge pump circuitry (Fig. 3, 5: “multi-stage charge pump”) configured to supply a supplemental power to the analog input circuitry (Fig. 4, Section III. DESIGN OF THE MULTI-STAGE CHARGE PUMP: charge pump provide “an output control voltage > 2VDD” ); and
the signal conversion circuitry (Fig. 1: elements from DAC to SAR in Fig. 1) configured to, during each iteration of a conversion cycle (Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: “The 8-bit SAR ADC requires ten clock cycles for each conversion, one clock cycle for input sampling and the remaining clock cycles for bit cycling):
convert the analog input signal to a digital output signal (Fig. 1, Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: “The 8-bit SAR ADC requires ten clock cycles for each conversion, one clock cycle for input sampling and the remaining clock cycles for bit cycling.” As depicted in Fig. 1, analog signal, Vin, is converted to a 8-bit digital output signal for each conversion cycle); and
control the charge pump circuitry based on a state of the conversion cycle (Fig. 1, 3, Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: “During the bit cycling period, the sampling switches are turned OFF (HOLD phase)”; Section III. DESIGN OF THE MULTI-STAGE CHARGE PUMP: “The signal Clkin in Fig. 3 corresponds to the sampling pulse for the SAR ADC.” As depicted in Fig. 3, the multi-stage charge pump is controlled by Clkin signal, corresponding to “the sampling pulse for the SAR ADC,” based on “input sampling” state and the “bit cycling” state of the “each conversion” cycle).
Although Harikumar2014 discloses the multi-stage charge pump is receiving Clkin signal, corresponding to “the sampling pulse for the SAR ADC,” as above, they do not teach the Clkin signal is provided by:
“the signal conversion circuitry.”
On the other hand in the same field of endeavor (Abstract: “8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC)”), Harikumar2016 teaches (Fig. 1, 7, Section II. ADC ARCHITECTURE, Part D. SAR Logic) “The signal samp [Clkin] generated by the leftmost DFF on the top row constitutes the sampling pulse for the ADC. It is provided as input to the charge pump to obtain the boosted gate control voltage” where the signal samp [Clkin] is provided by:
“the signal conversion circuitry (Fig. 1, 6, Section II. ADC ARCHITECTURE, Part D. SAR Logic: “Successive Approximation Control Logic”/ “SAR controller”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the input signal, Clkin, to the charge pump in Harikumar2014’s invention can be provided by the “Successive Approximation Control Logic”/ “SAR controller” as taught by Harikumar2016 where doing so would (Harikumar2016, Section V. CONCLUSION) “achieves satisfactory dynamic and static performance and maintains almost constant SNDR over the entire signal bandwidth.”
Regarding Claim 8, Harikumar2014 discloses:
A system (Fig. 1), comprising:
analog input circuitry (Fig. 1, 5: “VIP, VIN Sample” switch; “Stacked TG switch”) configured to supply an analog input signal to signal conversion circuitry (Fig. 1: Stacked TG switch supply an analog input signal, Vin, to signal conversion circuitry, SAR ADC, comprising at least elements from DAC to SAR in Fig. 1);
charge pump circuitry (Fig. 3, 5: “multi-stage charge pump”) configured to supply a supplemental power to the analog input circuitry (Fig. 4, Section III. DESIGN OF THE MULTI-STAGE CHARGE PUMP: charge pump provide “an output control voltage > 2VDD” ); and
the signal conversion circuitry (Fig. 1: elements from DAC to SAR in Fig. 1) comprising:
a digital-to-analog converter (Fig. 1: digital-to-analog converters DACP and DACN) coupled to receive the analog input from the analog input circuitry (Fig. 1: DACP and DACN receives the analog input signal Vin from the “VIP, VIN Sample” switch/“Stacked TG switch”);
a comparator (Fig 1: element with “+” input and “-” input) coupled to the digital-to-analog converter (Fig 1: element with “+” input and “-” input are coupled to the outputs of the DACP and DACN, respectively); and
a successive-approximation-register converter (Fig. 1: “SAR”) coupled to the digital-to-analog converter and to the comparator (Fig. 1: “SAR” is coupled to the element with “+” input and “-” input and the DACP and DACN);
wherein the signal conversion circuitry (Fig. 1: elements from DAC to SAR in Fig. 1) configured to, during each iteration of a conversion cycle (Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: “The 8-bit SAR ADC requires ten clock cycles for each conversion, one clock cycle for input sampling and the remaining clock cycles for bit cycling):
convert the analog input signal to a digital output signal (Fig. 1, Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: “The 8-bit SAR ADC requires ten clock cycles for each conversion, one clock cycle for input sampling and the remaining clock cycles for bit cycling.” As depicted in Fig. 1, analog signal, Vin, is converted to a 8-bit digital output signal for each conversion cycle); and
control the charge pump circuitry based on a state of the conversion cycle (Fig. 1, 3, Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: “During the bit cycling period, the sampling switches are turned OFF (HOLD phase)”; Section III. DESIGN OF THE MULTI-STAGE CHARGE PUMP: “The signal Clkin in Fig. 3 corresponds to the sampling pulse for the SAR ADC.” As depicted in Fig. 3, the multi-stage charge pump is controlled by Clkin signal, corresponding to “the sampling pulse for the SAR ADC,” based on “input sampling” state and the “bit cycling” state of the “each conversion” cycle).
Although Harikumar2014 discloses the multi-stage charge pump is receiving Clkin signal, corresponding to “the sampling pulse for the SAR ADC,” as above, they do not teach the Clkin signal is provided by:
“the signal conversion circuitry.”
On the other hand in the same field of endeavor (Abstract: “8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC)”), Harikumar2016 teaches (Fig. 1, 7, Section II. ADC ARCHITECTURE, Part D. SAR Logic) “The signal samp [Clkin] generated by the leftmost DFF on the top row constitutes the sampling pulse for the ADC. It is provided as input to the charge pump to obtain the boosted gate control voltage” where the signal samp [Clkin] is provided by:
“the signal conversion circuitry (Fig. 1, 6, Section II. ADC ARCHITECTURE, Part D. SAR Logic: “Successive Approximation Control Logic”/ “SAR controller”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the input signal, Clkin, to the charge pump in Harikumar2014’s invention can be provided by the “Successive Approximation Control Logic”/ “SAR controller” as taught by Harikumar2016 where doing so would (Harikumar2016, Section V. CONCLUSION) “achieves satisfactory dynamic and static performance and maintains almost constant SNDR over the entire signal bandwidth.”
Regarding Claim 2, 9, and 16, Harikumar2104 in view of Harikumar2106 discloses all as applied to claim 1, 8 and 15 above, where Harikumar2014 further teaches:
wherein the conversion cycle comprises a set of conversion sub-cycles (Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: “The 8-bit SAR ADC requires ten clock cycles for each conversion, one clock cycle for input sampling and the remaining clock cycles for bit cycling”. That is, each conversion cycle consists of a set of 10 conversion sub-cycles), and wherein, to control the charge pump circuitry, the signal conversion circuitry is configured to disable the charge pump circuitry during a first portion of the set of conversion sub-cycles (Fig. 1, Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH ; “During the bit cycling period” the multi-stage charge pump Clkin single (Fig. 1: “Sample” waveform) is “turned OFF (HOLD phase)”) and enable the charge pump circuitry during a second portion of the set of conversion sub-cycles (Fig. 1, Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH; During the input sampling period, the multi-stage charge pump Clkin single (Fig. 1: “Sample” waveform) is turned ON/high state).
Regarding Claim 3, 10 and 17, Harikumar2104 in view of Harikumar2106 discloses all as applied to claim 1, 8, and 15 above, where Harikumar2016 further teaches:
wherein to control the charge pump circuitry, the signal conversion circuitry is configured to:
identify a count of clock cycles during the conversion cycle (Fig. 1, 6, 7 Section II. ADC ARCHITECTURE, Part D. SAR Logic: “The D flip-flops (DFFs) in the top row act as a ring counter” whereas depicted in Fig. 7, identify two input sampling clock period/cycle of the conversion cycle and eight clock periods/cycles);
determine that the count of clock cycles exceeds a threshold clock cycle (Fig. 6, 7: SAR Logic determines that the count of the ring counter exceeds a 2 count threshold clock cycle); and
in response to determining that the count of clock cycles exceeds the threshold clock cycle, disable the charge pump circuitry (Fig. 6, 7 Section III. CIRCUIT IMPLEMENTATION: “During the bit cycling period, which consists of eight clock periods of the system clock, the sampling switches are turned OFF (hold phase).” That is the “signal samp”/Clkin is not provided to the charge pump).
Regarding Claim 4, 11 and 18, Harikumar2104 in view of Harikumar2106 discloses all as applied to claim 1, 8 and 15 above, where Harikumar2014 further teaches:
wherein to convert the analog input signal to the digital output signal, the signal conversion circuitry is configured to sample the analog input signal using a first clock signal (Fig. 1, Section II. DESIGN TRADE-OFFS FOR THE SAMPLING SWITCH: 8-bit digital output signal is sampled using “fsys [that] is the system clock frequency used by the SAR logic”).
Regarding Claim 5, 12 and 19, Harikumar2104 in view of Harikumar2106 discloses all as applied to claim 4, 11 and 18 above, where Harikumar2104 further teaches:
wherein to supply the supplemental power to the analog input circuitry, the charge pump circuitry is configured to produce the supplemental power using a second clock signal (Fig. 1, 3 Section III. DESIGN OF THE MULTI-STAGE CHARGE PUMP: the multi-stage charge pump is operated using second clock signal, Clkin, to produce the supplemental power, 2VDD, to the analog input circuitry/”Stacked TG switch”).
Regarding Claim 6, 13 and 20, Harikumar2104 in view of Harikumar2106 discloses all as applied to claim 5, 12 and 19 above, where Harikumar2014 further teaches:
wherein the first clock signal differs from the second clock signal (Fig. 1, 3 Section III. DESIGN OF THE MULTI-STAGE CHARGE PUMP: first/system clock signal, fsys differs from the second/sample clock signal, Clkin as depicted in Fig. 1).
Allowable Subject Matter
Claims 7 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMNEET SINGH whose telephone number is (571)272-2414. The examiner can normally be reached 9:30am to 5:30pm.
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/AMNEET SINGH/Examiner, Art Unit 2633
/SAM K AHN/Supervisory Patent Examiner, Art Unit 2633
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