DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/4/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, 8-9, 11, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu et al. (U.S. Publication 2018/0217957), hereinafter Zhu further evidence incorporated by reference, PCI Express Base Specification 5.0 hereinafter PCIe5.
Referring to claim 1, Zhu teaches, as claimed, an information handling system comprising:
a storage medium (non-volatile memory; see Paragraph 48);
a first storage interface (PCIe link, see Paragraph 48) communicatively coupled to the storage medium; and a second storage interface (number of the example PCIe communications, see Paragraph 48) communicatively coupled to the storage medium; wherein:
communications lanes of a communications port (see Fig. 2, PHY 0) of the first storage interface are routed via standard routing to lower communications lanes (see Fig. 2, PHY 0 to PHY N/2-1) of the storage medium, such that a lowest-indexed communications lane (see Fig. 2, 121 and PHY 0; Note, zero is lowest indexed) of the communications port of the first storage interface is communicatively coupled to a lowest-indexed communications lane (see Fig. 2, PHY 0) of the storage medium and each successively higher-indexed communications lane of the communications port of the first storage interface is communicatively coupled to a successively higher-indexed (see Fig. 2, PHY 1) communications lane of the storage medium; and
communications lanes of a communications port (see Fig. 2, PHY N/2) of the second storage interface are routed via lane reversal routing (lane reversal operation, see Paragraph 41) to higher communications lanes (see Fig. 2, PHY N/2 to PHY N-1) of the storage medium, such that a lowest-indexed communications lane of the communications port (see Fig. 2, PHY N/2) of the second storage interface is communicatively coupled to a highest-indexed communications lane (see Fig. 2, PHY N/2) of the storage medium and each successively higher-indexed communications lane of the communications port of the second storage interface is communicatively coupled to a successively lower-indexed (see Fig. 2, PHY N-1) communications lane of the storage medium.
As to claim 2, Zhu teaches the information handling system of Claim 1, wherein the information handling system is configured to operate in a single-port mode (see Fig. 2 first half if row; Note, when user selects the 2nd half of row to be inactive, it is equivalent to single-port mode) in which the first storage interface is active, the second storage interface is inactive (used in power saving and inactive state, see PCIe5, Page 1069, Section 8.4.5.5), and the storage medium performs training (see PCIe5, Page 312, Section 4.2.4.13 Lane vs Link Training) with the first storage interface in a standard lane configuration (see Zhu, Fig. 2 first half of row; Note, none lane reversal will be considered a standard lane configuration).
As to claim 4, Zhu teaches the information handling system of Claim 1, wherein the information handling system is configured to operate in a single-port mode in which the second storage interface is active, the first storage interface is inactive (used in power saving and inactive state, see PCIe5, Page 1069, Section 8.4.5.5), and the storage medium performs training with the storage interface in a reversed lane configuration (Note, PCIe standard allows for inactive states any unused lanes).
As to claim 6, Zhu teaches the information handling system of Claim 1, wherein the information handling system is configured to operate in a dual-port mode in which the first storage interface is active, the second storage interface is active, and a first port of the storage medium performs training (see PCIe5, Page 312, Section 4.2.4.13 Lane vs Link Training) with the first storage interface in a standard lane configuration and a second port of the storage medium performs training with the second storage interface in a reversed lane configuration.
As to claims 8-9, 11, and 13, they are directed to a method to implement the system as set forth in claims 1-2, 4, and 6 respectively. Therefore, they are rejected on the same basis as set forth hereinabove.
Allowable Subject Matter
Claims 3, 5, 7, 10, 12, and 14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicants’ arguments filed 7/13/2026 have been fully considered but they are moot in view of new grounds of rejections.
Regarding the 35 U.S.C. §112, second paragraph problems, Applicant's response/amendment has overcome these rejections.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN NAM/Primary Examiner, Art Unit 2183
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