DETAILED ACTION
This Office action responds to the application filed on 04/26/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species 1, reading on figures 1-4, in the reply filed on 07/28/2024, is acknowledged. The applicant indicates that claims 1-20 read on the elected species. The examiner disagrees.
Claim 10 recites the limitation “wherein the first interface is provided along at least 90 percent of the first die” which reads on Figure 6 of Species 3 as stated in Applicant’s specification (see, e.g., para.0045-0046). Accordingly, claim 10 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claims 1-9 & 11-20 will be examined in this Office action.
Claim Objections
Claim 1 is objected to because of the following informalities: in the limitation “a sixth interface on sixth side,” the “a” is missing such as “on a sixth side.”
Claim 5 is objected to because of the following informalities: in the limitation “the second integrated circuit die comprises a a high bandwidth memory,” the word “a” is repeated.
Claim 6 is objected to because of the following informalities: in the limitation “an sixth side,” the word “an” is grammatically incorrect.
Claim 19 is objected to because of the following informalities: in the limitation “a sixth interface on sixth side,” the “a” is missing such as “on a sixth side.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “the first integrated circuit die comprises an eighth interface an sixth side” in lines 3-4 and fails to particularly point out and distinctly claim how the eight interface and the sixth side are related in the Applicant’s invention.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11, 19, & 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 20220189934).
Regarding Claim 1, Kim (see, e.g., figs. 1-2, para.0021-0023, para.0026) shows an integrated circuit package, comprising
a first integrated circuit die 106a-d;
a second integrated circuit die 106e-h;
a third integrated circuit die 102;
and a support structure (150 and/or 208, see, e.g., para.0027),
wherein the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are attached to the support structure (see, e.g., fig. 2),
wherein the first integrated circuit die 106a-d comprises
a first interface (112d & bottom side of 106d are both considered the first interface, the limitation “interface” is broad and can be interpreted as both the electrical connection and the physical area where the connection takes place) on a first side of the first integrated circuit die 106a-d (bottom side of 106d, each component 106a-d of the first integrated circuit dies have 4 sides)
and the second integrated circuit die 106e-h comprises
a second interface 112h on a second side of the second integrated circuit die 106e-h (bottom left side of 106h, each component 106e-h of the first integrated circuit dies have 4 sides),
wherein the first side neighbors the second side (the limitation “neighbors” is broad and does not clearly define position, all sides/interfaces/dies neighbor one another since they are on the same support structure),
wherein the first integrated circuit die 106a-d is configured to communicate with the second integrated circuit die 106e-h via the first interface 112d and the second interface 112h (all interfaces 110a-h & 112a-h communicate with one another throughout the support structure, 112d & 112h communicate through 110a-d of die 102 and therefore anticipates the limitation, see, e.g., para.0022-0023),
wherein the first integrated circuit die 106a-d comprises
a third interface 112c on a third side of the first integrated circuit die 106a-d (right side of 106c)
and the second integrated circuit die 106e-h comprises
a fourth interface 112g on a fourth side of the second integrated circuit die 106e-h (bottom left side of 106g),
wherein the third integrated circuit die 102 comprises
a fifth interface 110b on a fifth side (left side of 102, in top view fig. 1)
and a sixth interface 110d on sixth side (right side of 102, in top view fig. 1),
the sixth side being parallel to the third side and the fifth side (third, fifth, and sixth sides are all vertical sidewalls of their respective dies and are therefore parallel, see, e.g., figs. 1-2),
wherein the first integrated circuit die 106a-d is configured to communicate with the third integrated circuit die via the fifth interface and the third interface (112c to 110b, see, e.g., para.0022-0023),
wherein the second integrated circuit die 106e-h is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface (112g to 110d, see, e.g., para.0022-0023).
The mapping “bottom” refers to fig. 2 of the prior art wherein the dies 106b, 104, & 106f are shown. All elements 102, 104, 106a-h, 110a-h, & 112a-h, are connected to the same interconnections and thus “bottom” refers to the bottom sides of the dies connected to interconnections 201, 202, & 203 (see, e.g., para.0023, para.0026).
Regarding Claim 2, Kim shows the integrated circuit package as set forth claim 1,
wherein the support structure (150 and/or 208) comprises an interposer 150 (see, e.g., para.0027).
Regarding Claim 3, Kim shows the integrated circuit package as set forth in claim 2,
wherein the support structure (150 and/or 208) comprises a package substrate 208 (see, e.g., para.0027).
Regarding Claim 4, Kim shows the integrated circuit package as set forth in claim 1,
wherein the first integrated circuit die 106a-d and the second integrated circuit die 106e-h comprise a memory circuit (stated to be high bandwidth memory devices and thus form memory circuits, see, e.g., para.0021).
Regarding Claim 5, Kim shows the integrated circuit package as set forth in claim 1,
wherein the first integrated circuit die 106a-d and the second integrated circuit die 106e-h comprise a a high bandwidth memory (see, e.g., para.0021).
Regarding Claim 6, Kim shows the integrated circuit package as set forth in claim 1, comprising
a fourth integrated circuit die 104,
wherein the fourth integrated circuit die 104 includes a seventh interface 110e on a seventh side (bottom left side of 104),
and wherein the first integrated circuit die 106a-d comprises an eighth interface 112b an sixth side (bottom right side of 106b),
wherein the first integrated circuit die 106a-d is configured to communicate with the fourth integrated circuit die via the seventh interface and the eighth interface (106b to 104, see, e.g., para.0026),
wherein the sixth side and seventh side are neighboring sides and the sixth side is opposite the first side (106b & 106d defining the sixth and first sides, respectively, are on opposite ends closer to line B-B and closer to line A-A, therefore anticipating the limitation).
Regarding Claim 7, Kim shows the integrated circuit package as set forth in claim 6,
wherein the fourth integrated circuit die 104 comprises an input/output circuit 140 (see, e.g., para.0024-0025).
Regarding Claim 8, Kim shows the integrated circuit package as set forth in claim 6,
wherein the fourth integrated circuit die comprises a compute circuit 140 (computes connections to other electrical components, see, e.g., para.0024-0025).
Regarding Claim 9, Kim shows the integrated circuit package as set forth in claim 1,
wherein the first interface and the second interface is configurable (interfaces are configured to establish connections with other dies/devices in the package and are therefore considered configurable).
Regarding Claim 11, Kim shows the integrated circuit package as set forth in claim 1,
wherein the first interface (112d & bottom side of 106d are both considered the first interface) is larger than the third interface 112c (see, e.g., fig. 1).
Regarding Claim 19, Kim (see, e.g., figs. 1-2, para.0021, para.0026) shows a method, comprising:
providing a first integrated circuit die 106a-d on an interposer 150 or a package substrate 208;
providing a second integrated circuit die 106e-h on the interposer or the package substrate;
providing a third integrated circuit die 102 on the interposer or the package substrate;
and wherein the first integrated circuit die comprises
a first interface 112d on a first side of the first integrated circuit die (bottom side of 106d, all elements 106a-h are connected to 203 as shown in fig. 2, see, e.g., para.0023)
and the second integrated circuit die comprises
a second interface 112h on a second side of the second integrated circuit die (bottom side of 106h),
wherein the first side neighbors the second side (the limitation “neighbors” is broad and does not clearly define position, all sides/interfaces/dies neighbor one another since they are on the same support structure),
wherein the first integrated circuit die is configured to communicate with the second integrated circuit die via the first interface and the second interface (through connections 203 and 102, see, e.g., para.0022-0023),
wherein the first integrated circuit die comprises
a third interface 112c on a third side of the first integrated circuit die (right side of 106c)
and the second integrated circuit die comprises
a fourth 112g interface on a fourth side of the second integrated circuit die (bottom side of 106g),
wherein the third integrated circuit die comprises
a fifth interface 110b on a fifth side (left side of 102) and a sixth interface 110d on sixth side (right side of 102),
the sixth side being parallel to the third side and the fifth side (all parallel since they are the vertical sidewalls of their respective dies),
wherein the first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface (all interfaces 110a-h & 112a-h communicate with one another throughout the support structure, see, e.g., para.0022-0023),
wherein the second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface (all interfaces 110a-h & 112a-h communicate with one another throughout the support structure, see, e.g., para.0022-0023),
Regarding Claim 20, Kim (see, e.g., para.0026-0029) shows the method of claim 19,
wherein the first interface is configurable and uses through vias (206 & 212) coupled to the interposer 150 or the package substrate 208 (the first interface is configured to be a memory device and is therefore configurable, the first interface is connected to the through vias and therefore uses them since the limitation does not define what they are used for, see, e.g., fig. 2).
Claims 12-14 & 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220189934) in view of Pietambaram (US 20220375865).
Regarding Claim 12, Kim (see, e.g., figs. 1-2, para.0021, para.0026) shows a package, comprising:
a first high bandwidth memory die 106a-d comprising
and a first die to die interface 112d on a first side (right side of 106d)
and a second die to die interface 112c on a second side (right side of 106c);
a second high bandwidth memory die 106e-h comprising
and a third die to die interface 112g on a third side (left side 106h)
and a fourth die to die interface 112h on a fourth side (left side of 106h);
and a compute die 104 comprising
a fifth die to die interface 110c on a fifth side (right side of 110c) and in communication with the fourth die to die interface (110a-h communicates with 112a-h, see, e.g., para.0022-0023),
the fifth side is parallel to the fourth side (right and left sides are parallel since they are the vertical sidewalls of their respective dies) and the first die to die interface is in communication with the third die to die interface (110a-h communicates with 112a-h, see, e.g., para.0022-0023),
wherein the first side and the third side are parallel (first and third sides are parallel since they are the vertical sidewalls of their respective dies).
Kim, however, fails to show
the first high bandwidth memory die comprising
a first cross bar circuit on a first bottom level
the second high bandwidth memory die comprising
a second cross bar circuit on a second bottom level
Pietambaram (see, e.g., fig. 1, para.0064), in a similar device to Kim, shows a configuration wherein
a high bandwidth memory die 114-3 (die comprising high memory bandwidth) comprising
a cross bar circuit 114-2 (die functioning as input/output circuitry between multiple components) on a bottom level 104-2
Pietambaram teaches the configuration of a cross bar circuit, in the form of input/output circuitry, in a high bandwidth memory die would facilitate and control connections to other dies within an integrated circuit package.
The cross bar circuit of Pietambaram is incorporated into the first and second high bandwidth memory dies of Kim.
It would have been obvious at the time of filing the invention to incorporate the cross bar circuit of Pietambaram in the device of Kim to facilitate and control connections to other dies within an integrated circuit package.
Regarding Claim 13, Kim, in view of Pietambaram, shows the package as set forth in claim 12,
wherein the fourth die to die interface is configurable (the fourth die to die interface is configured for connections to other dies and is therefore considered configurable).
Regarding Claim 14, Kim, in view of Pietambaram, shows the package as set forth in claim 12,
wherein the fourth die to die interface is configurable in size (the fourth die to die interface has been configured in size to form the interface and is therefore considered configurable in size).
Regarding Claim 16, Kim, in view of Pietambaram, shows the package as set forth in claim 12, further comprising
an input/output die 102 (facilitates connections to elements 106a-h and 104, see, e.g., para.0023-0025).
Regarding Claim 17, Kim, in view of Pietambaram, shows the package as set forth in claim 16,
wherein the input/output die 102 comprises a serializer deserializer circuit 142a-c (see, e.g., para.).
Regarding Claim 18, Kim, in view of Pietambaram, shows the package as set forth in claim 16,
wherein the input/output die comprises a memory interface circuit (any of the interfaces surrounding 102).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220189934) in view of Pietambaram (US 20220375865) and further in view of Elsherbini (US 20220406751).
Regarding Claim 15, Kim, in view of Pietambaram, shows the package as set forth in claim 12,
Kim, in view of Pietambaram, however, fails to state
wherein the first die to die interface is the same size as the second die to die interface.
Elsherbini (see, e.g., para.0038, para.0057), in a similar device to Kim, in view of Pietambaram, states the size of dies and their connections within an integrated circuit package can alter the speed of the connections.
Kim (see, e.g., para.0022-0023) states 112d & 112c pertain to components 112a-h and are established together. As stated by Elsherbini, altering the different sizes would lead do different and inconsistent speeds of connections. Therefore, one would be motivated to form the components 112a-h of Kim with the same size would provide a consistent reliable connection speed throughout the package.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the same sizes of die to die interfaces, as motivated by Elsherbini, in the device of Kim, in view of Pietambaram, to provide a consistent reliable connection speed throughout the package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
