DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
Claims 7, 13, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding these claims, lines 2-3 both say “a second pole” associated with the differential amplifier and the active inductor. This language makes the claim unclear and indefinite. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 14, and 17 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 8222967 by Raman et al.
Regarding claim 1, Raman teaches a two-stage continuous-time linear equalizer (CTLE) to increase a peaking gain (Fig. 2, 4), the two-stage CTLE comprising:
a first stage (Fig. 4 #10a) comprising a first equalizer core cell (Abstract); and
a second stage (10b) comprising a second equalizer core cell (Abstract), wherein the first equalizer core cell and the second equalizer core cell each comprise:
a differential amplifier comprising a first n-type metal-oxide-semiconductor (NMOS) transistor (Fig. 2 #14a); and
an active inductor load (Fig. 2 #30; Col. 3 lines 54-55) coupled to the differential amplifier, the active inductor load comprising a second NMOS transistor (32a) and a load resistor (34a).
Regarding claim 4, Raman teaches the two-stage CTLE of claim 1, wherein the first NMOS transistor (14a) of the differential amplifier is coupled to:
an input voltage reference node (VIP) of a pair of differential input voltage reference nodes (VIP, VIN);
an output voltage reference node (VON) of a pair of differential output voltage reference nodes (VON, VOP), wherein the output voltage reference node is further coupled to the load resistor (34a);
a boost-control capacitor network (22); and
one of: a gain control NMOS transistor operating in linear mode, or a gain-control resistor network (20).
Regarding claim 14, Raman teaches a Universal Serial Bus (USB) Physical Layer (PHY) of a USB system, the USB PHY comprising (This is standard practice in any modern amplifier for universality):
a continuous-time linear equalizer (CTLE) equalizer core cell (Fig. 2, 4) comprising:
a differential amplifier comprising a first n-type metal-oxide-semiconductor (NMOS) transistor (Fig. 2 #14a); and
an active inductor load (30) coupled to the differential amplifier, the active inductor load comprising a second NMOS transistor (32a) and a load resistor (34a).
Regarding claim 17, Raman teaches the USB PHY of claim 14, wherein the first NMOS transistor (14a) of the differential amplifier is coupled to:
an input voltage reference node (VIP) of a pair of differential input voltage reference nodes (VIN, VIP);
an output voltage reference node (VON) of a pair of differential output voltage reference nodes (VON, VOP), wherein the output voltage reference node is further coupled to the load resistor (34a);
a boost control capacitor network (22); and
one of: a gain control NMOS transistor operating in linear mode, or a gain control resistor network (20).
Claim(s) 8-9 and 14-16 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20090074048 by Amin et al.
Regarding claim 8, Amin teaches an equalizer filter (Fig. 1) comprising:
a differential amplifier (12) comprising a first n-type metal-oxide-semiconductor (NMOS) transistor (22; Par. 23), the differential amplifier to provide a frequency response having a first gain in a first bandwidth and a first peaking gain in a second bandwidth (Fig. 11); and
an active inductor load (14) coupled to the differential amplifier (12), the active inductor load comprising a second NMOS transistor (56; par. 25) and a load resistor (52), the active inductor load to provide a second peaking gain in the second bandwidth, the first peaking gain and the second peaking gain combining to obtain an increased peaking gain in the second bandwidth (Fig. 11).
Regarding claim 9, Amin teaches the equalizer filter of claim 8, wherein:
the first bandwidth corresponds to a transmission channel bandwidth of a transmission channel (Abstract) associated with the equalizer filter;
the second bandwidth corresponds to a high-frequency attenuation bandwidth of the transmission channel (Par. 43); and
the first bandwidth comprises the second bandwidth.
Regarding claim 14, Raman teaches a Universal Serial Bus (USB) Physical Layer (PHY) of a USB system, the USB PHY comprising (This is standard practice in any modern amplifier for universality):
a continuous-time linear equalizer (CTLE) equalizer core cell (Fig. 1) comprising:
a differential amplifier comprising a first n-type metal-oxide-semiconductor (NMOS) transistor (12); and
an active inductor load (14) coupled to the differential amplifier, the active inductor load comprising a second NMOS transistor (56) and a load resistor (52).
Regarding claim 15, Amin teaches the USB PHY of claim 14, wherein:
the differential amplifier (12) is to provide a frequency response having a first gain in a first bandwidth and a first peaking gain in a second bandwidth (Fig. 11);
the active inductor load (14) is to provide a second peaking gain in the second bandwidth, the first peaking gain and the second peaking gain combining to obtain an increased peaking gain in the second bandwidth (Fig. 11); and
the increased peaking gain is greater than the first peaking gain (combining the gains will increase it more than the first peaking gain).
Regarding claim 16, Amin teaches the USB PHY of claim 15, wherein:
the first bandwidth corresponds to a transmission channel bandwidth (Abstract) of a transmission channel associated with the USB PHY;
the second bandwidth corresponds to a high-frequency attenuation bandwidth of the transmission channel (Par. 43); and
the first bandwidth comprises the second bandwidth.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20090074048 by Amin et al. in view of US 8222967 by Raman et al.
Regarding claim 1, Amin teaches a continuous-time linear equalizer (CTLE) to increase a peaking gain comprising:
a differential amplifier (12) comprising a first n-type metal-oxide-semiconductor (NMOS) transistor (22; Par. 23); and
an active inductor load (14) coupled to the differential amplifier (12), the active inductor load comprising a second NMOS transistor (56; par. 25) and a load resistor (52).
Amin is silent in a two stage CTLE with a first stage comprising a first equalizer core cell and a second stage comprising a second equalizer core cell. However, Raman teaches a multi-stage CTLE with a differential amplifier stage and an active inductor load in each stage (Raman fig. 2, 4). It would be obvious to combine the multi-stage teaching of Raman with the CTLE circuit of Amin in order to have increased gain.
Regarding claim 2, the combination of Amin and Raman teaches the two-stage CTLE of claim 1, wherein:
the differential amplifier (12) is to provide a frequency response having a first gain in a first bandwidth and a first peaking gain in a second bandwidth (Fig. 11);
the active inductor load (14) is to provide a second peaking gain in the second bandwidth, the first peaking gain and the second peaking gain combining to obtain an increased peaking gain in the second bandwidth (Fig. 11); and
the increased peaking gain is greater than the first peaking gain (combining the gains will increase it more than the first peaking gain).
Regarding claim 3, the combination of Amin and Raman teaches the two-stage CTLE of claim 2, wherein: the first bandwidth corresponds to a transmission channel bandwidth (Abstract) of a transmission channel associated with the two-stage CTLE;
the second bandwidth corresponds to a high-frequency attenuation bandwidth of the transmission channel (Par. 43); and
the first bandwidth comprises the second bandwidth.
Regarding claim 4, the combination of Amin and Raman teaches the two-stage CTLE of claim 1, wherein the first NMOS transistor (Raman #14a) of the differential amplifier is coupled to:
an input voltage reference node (Raman VIP) of a pair of differential input voltage reference nodes (Raman VIP, VIN);
an output voltage reference node (Raman VON) of a pair of differential output voltage reference nodes (Raman VON, VOP), wherein the output voltage reference node is further coupled to the load resistor (Raman #34a);
a boost-control capacitor network (Raman #22); and
one of:
a gain control NMOS transistor operating in linear mode, or a gain-control resistor network (Raman #20).
Allowable Subject Matter
Claims 5-6, 10-12, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach the limitations in these claims.
Claims 7, 13, and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The prior art does not teach wherein the differential amplifier corresponds to a first zero, a first pole, and a second pole; the active inductor load corresponds to a second zero and a second pole; and the second zero and second pole correspond to a high-frequency attenuation bandwidth of a transmission channel.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11777491 by Biswas teaches a CTLE circuit with an active inductor.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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