DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 11/19/2025. Claims 1, 3, 5-20 are pending and are under examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiah (US 2004/0140832) in view of Choi et al. (US 2019/0130948) and McClure (USP 6,294,939).
Regarding claim 1, Shiah’s figures 7 and 8 shows a circuit portion for filtering digital signals, the circuit portion comprising: an overall signal input (220) for receiving a digital input signal (Signal_in) and an overall signal output (256) for outputting a digital output signal (signal_out); a first delay circuit portion (210, 232) coupled to the signal input and configured to output a first delayed digital signal (rise -delayed signal) comprising one or more leading edges each corresponding to a rising edge of the input signal (rising and falling edges of the Signal_in), and one or more trailing edges each corresponding to a falling edge of the input signal, each of said leading edges in the first delayed digital signal (rise-delayed signal) being subject to a first time delay (T1) relative to the corresponding rising edge in the input signal such that a time period between each leading edge and the ensuing trailing edge (the duration of the logic high level of the rise-delayed signal) is shorter than a time period between the corresponding rising edge and ensuing falling edge in the input signal (the duration of the logic high level of the signal_in), the first delay circuit portion being configured such that it does not output a corresponding leading and trailing edge in the first delayed signal when the time period between the rising edge and the ensuing falling edge in the input signal is less than or equal to the first time delay (when the duration of the logic high of the Signal_in is less than (narrower) the first time delay T1, output from the NAND gate 232 is flat) ; a second delay circuit (214, 236) portion coupled to the signal input and configured to output a second delayed digital signal (Fall-delayed signal) comprising one or more leading edges each corresponding to a falling edge of the input signal (the fall-delayed signal has the leading edge rising at the same time the rising edge of the input signal Signal_In) , and one or more trailing edges each corresponding to a rising edge of the input signal (the falling edge of the fall-delayed signal has a falling edge falling after a time delay T2 from the falling edge of the input signal Signal_in), each of said leading edges in the second delayed digital signal being subject to a second time delay (T2) relative to the corresponding falling edge in the input signal such that a time period between each leading edge and the ensuing trailing edge is longer than a time period between the corresponding falling edge and ensuing rising edge in the input signal (the duration of the logic high level of the fall-delayed signal is longer than the duration of the logic high level of the input signal signal_in), the second delay circuit portion being configured such that it does not output a corresponding leading and trailing edge in the second delayed signal when the time period between the falling edge and the ensuing rising edge in the input signal is less than or equal to the second time delay (inherently present in the second delay circuit portion as explained in the above for the first delay circuit portion); and a logic circuit portion (256) comprising a first input coupled to the first delay circuit portion, and a second input coupled to the output of the second delay circuit portion, the logic circuit portion being configured to output, to the overall signal output, the digital output signal which retains a current state when the first and second delayed digital signals have different states, and a state that is dependent on a state of the first and second delayed signals when the first and second delayed digital signals have the same state.
Shiah reference fails to disclose: (1) logic circuit portion is a Muller-C circuit portion; (2) the first delay time and the second delay time are equal as called for in claim 1.
Regarding the difference noted in item (1), Choi et al.’s figure 4 shows a muller-C circuit that is a capable of solving the undetermined state of a conventional RS latch. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the present invention to have Choi et al.’s muller-C in Shiah’s circuit arrangement for the purpose of eliminating the undetermined states within the conventional RS latch as taught by Choi et al. reference.
Regarding the difference noted in item (2), Shiah’s figures 7 and 8 shows a circuit comprising all the aspects of the present invention as noted above except for the first and second time delays (T1 and T2) are equal. Shiah suggests that the first and second time delays T1 and T2 can be independently adjusted and different delays can be chosen. Thus, one skilled in the art would have recognized that the first and second time delays can be chosen equally when required. McClure (USP 6,294,939) demonstrates that when the first and second delays are chosen to be equal (see McClure’s figure 5). Therefore, outside of any non-obvious results, the obvious of setting the first and second delay times to be equal for the purpose of obtaining a glitch free output signal as taught by McClure reference will not be patentable under 35USC 103.
Regarding claim 3, wherein the output signal output by the logic circuit portion has a state which matches a state of the first and second delayed digital signals when the first and second delayed digital signals have the same state (state when the output signal, the rise-delayed signal and the fall-delayed signal are at logic high state).
Regarding claim 5, Shiah’s figures 7 and 8 shows a circuit comprising all the aspects of the present invention as noted above except Shiah’s second delay circuit portion (214, 236, 248) including an inverter (248) at the output instead of being at the input of the second delay circuit portion as called for in claim 5. However, one skilled in the art would have been recognized by placing an inverter at the input of the delay circuit or at the output of the delay circuit, the circuit operation remain unchanged (see Shiah’s figure 8 which shows similar waveforms to the present invention figure 2a). Therefore, outside of any non-obvious results, the obviousness of placing an inverter at the input of the delay circuit portion will not be patentable under 35USC 103.
Regarding claim 6, wherein the first and/or second delay circuit portion comprises a capacitance element (capacitor C1 to C3; figure 6) and an impedance element (on-resistance of the transistors within the inverters I1 to I7) arranged such that: upon receipt of a first type of edge of the digital input signal, a first current path is formed between the capacitance element and a first supply rail (one of the transistors within an inverter I turns on forming a first current path between the power supply and the capacitor C); upon receipt of a second type of edge of the digital input signal, a second current path is formed between the capacitance element and a second supply rail (a second transistor within the inverter I turns on forming a second current path between the capacitance element C with the second supply rail (ground); and wherein: the impedance element (on resistance of the transistors within the inverter I) forms part of the second current path (a transistor turns on, conduct a current via the transistor to ground), and does not form part of the first current path.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiah (US 2004/0140832), Choi et al. (US 2019/0130948) and McClure (USP 6,294,939) further in view of Takahashi (US 2007/0296479).
Regarding claim 8, the combination of Shiah, Choi et al. and McClure references shows a circuit comprising all the aspects of the present invention as note above except for the first/second delay circuit portion whose impedance element comprises a resistor and the capacitance element comprises a transistor having its drain and source terminals connected together as called for in claim 8. Takahashi’s figure 11 shows a delay circuit comprising impedance element comprises a resistor (R) and the capacitance element comprises a transistor (MNC1 or MPC1) having its drain and source terminals connected together. Such a delay circuit provides a stable delay time with a controlled temperature characteristic. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Takahashi’s delay circuit in Shiah’s delay circuit arrangement in order to provide a stable delay time with a controlled temperature characteristic as taught by Takahashi reference.
Claim(s) 9-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiah (US 2004/0140832), Choi et al. (US 2019/0130948) and McClure (USP 6,294,939) and further in view of Witt et al. (USP 5,059,818).
Regarding claim 9, the combination of Shiah, Choi et al. and McClure references shows a circuit comprising all the aspects of the present invention as noted above except for an invert connected to the logic circuit portion as called for in claim 9. Witt et al.’s figure 1 shows the logic circuit portion (62/64) further comprising an inverter (108/110) coupled its output. The allows the output of the logic circuit portion properly buffered prior to delivering to the next circuit. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have an inverter in Shiah’s circuit arrangement in order to protect the integrity of the output signal of the logic circuit portion as taught by Witt et al. reference.
Regarding claims 10-13, Shiah’s figures 7 and 8 shows a circuit comprising all the aspects of the present invention as noted above except Shiah’s logic circuit portion is an RS latch instead of a combination of a first mutex and a second mutex circuits as called for in claims 10-13.
Choi et al.’s figure 4 shows a mutex circuit that is a capable of solving the undetermined state of a conventional RS latch. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the present invention to have Choi et al.’s mutex circuit in Shiah’s circuit arrangement for the purpose of eliminating the undetermined states within the RS latch as taught by Choi et al. reference.
Regarding claim 14, the combination Shiah, Choi et al. and McClure references shows a circuit comprising all the aspects of the present invention as noted above except for a single ended amplifier connected to the first or second output of the mutex circuit as called for in claim 14. Witt et al.’s figure 1 shows the logic circuit portion (62/64) further comprising a single ended amplifier (i.e., an inverter (108/110)) coupled its output. The allows the output of the logic circuit portion properly buffered prior to delivering to the next circuit. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have an inverter in Shiah’s circuit arrangement in order to protect the integrity of the output signal of the logic circuit portion as taught by Witt et al. reference.
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiah (US 2004/0140832), Choi et al. (US 2019/0130948), McClure (USP 6,294,939) and Witt et al. (USP 5,059,818) and in further view of Fong (USP 7,411,427).
Regarding claim 15, the combination of Shiah, Choi et al., McClure and Witt et al. references shows all the aspects of the present invention except for additional NAND and OR logic gates coupled to the inputs of the mutex circuit portion as called for in claim 15. Fong’s figure 4 shows additional NAND and OR logic gates coupled to the inputs of the mutex circuit portion (crossed coupled NAND gates). This arrangement would prevent the inputs applied to the mutex circuit assumes a same logic state, thus, to prevent erroneous operation. Therefore, it would have obvious to person skilled in the art at before the effective filing date of the invention to have Fong’s logic gates in Shiah and Choi et al. references combined for the purpose of preventing erroneous operation as taught by Fong reference.
Regarding claim 16, Fong et al.’s figure 4 also shows an inverter (DELBUF).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shiah (US 2004/0140832), Choi et al. (US 2019/0130948), McClure (USP 6,294,939) and Witt et al. (USP 5,059,818) and in further view of Rochard (USP 6,535,024).
Regarding the claim 17, the combination of Shiah, Choi et al., McClure and Witt et al. references shows all the aspects of the present invention except for additional inverters and two NAND gates coupled to the inputs of the mutex circuit portion as called for in claim 17. Rochard’s figure 3 shows additional inverters (58, 59), NAND gates (55, 56) coupled to the inputs of the mutex circuit (10). This arrangement would prevent the inputs applied to the mutex circuit assumes a same logic state, thus, to prevent erroneous operation. Therefore, it would have obvious to person skilled in the art at before the effective filing date of the invention to have Rochard’s inverters and logic gates in Shiah and Choi et al. references combined for the purpose of preventing erroneous operation as taught by Rochard et al. reference.
Allowable Subject Matter
Claims 7 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TUAN T LAM/Primary Examiner, Art Unit 2842 1/20/2026