Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 12 and 16.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 04/26/2024. These drawings are review and accepted by examiner.
Information Disclosure Statement
3. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 08/21/2025. The information disclosed therein was considered.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-2, 6-8, 11-12, 15-16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nien et al (Patent No.: US 11,562,786 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6) comprising:
a power supply node for a memory power supply voltage (a lowest VDD voltage (positive power supply voltage), column 2, lines 25-26);
a first bit line (a bit line BL, BLB, Figs 1-2) for a first column of bit-cells (a memory cell array 104 includes a plurality of Bit Cell, Figs. 1-2 and 5-6);
a first write driver transistor (a first write driver transistor 202, Figs 2, 5-6) coupled between the first bit line (the bit line BL, BLB) and the power supply node (the lowest VDD voltage (positive power supply voltage));
a second write driver transistor (a second write driver transistor 204, Figs. 2, 5-6) coupled between the first bit line (the bit line BL, BLB) and ground (the transistor 204 connected to the ground, Fig. 2, 5-6); and
a write driver logic circuit (a control circuit 112 connected to a write driver circuit 108, Figs. 1-2, 5-6) configured to drive the first write driver transistor (the first write driver transistor 202) and the second write driver transistor (the second write driver transistor 204) responsive to a data in signal during a write operation in which a write mask signal is not asserted, the write driver logic circuit (the write driver circuit 108) being further configured to switch on the first write driver transistor (the write driver transistor 202) and to switch off the second write driver transistor (the write driver transistor 204) during a first portion of a write operation in which the write mask signal is asserted (the control circuit 112 is operative to assist in a write operation in cell array 104 and provide a write path for the write operation when negative voltage generate circuit 110 is not enabled or enabled in response to the write assist signal, see at least in Figures 1-2 and 5-6, column 2, lines 57 to column 6, lines 32 and the related disclosures).
Regarding dependent claim 2. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6), wherein the write driver logic circuit (a control circuit 112 connected to a write driver circuit 108, Figs. 1-2, 5-6) is further configured to switch off the first write driver transistor (the write driver transistor 202) and to maintain the second write driver transistor (the write driver transistor 204) off during a remaining second portion of the write operation in which the write mask signal is asserted (the control circuit 112 is operative to assist in a write operation in cell array 104 and provide a write path for the write operation when negative voltage generate circuit 110 is not enabled or enabled in response to the write assist signal, see at least in Figures 1-2 and 5-6, column 2, lines 57 to column 6, lines 32 and the related disclosures).
Regarding dependent claim 6. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6) further comprising: a first write multiplexer transistor (the transistor 202) coupled between the first write driver transistor and the first bit line; and a second write multiplexer transistor (the transistor 204) coupled between the second write driver transistor and the first bit line (the multiplexer 106 includes the transistor 202 and the transistor 204, which is connected to the bit line BL, BLB of memory cell array 104).
Regarding dependent claim 7. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6) wherein the first write multiplexer transistor (the multiplexer 106) and the first write driver transistor (the transistor 202) each comprises a p-type metal-oxide semiconductor (PMOS) transistor (the transistor 202 is the type of pmos transistor).
Regarding dependent claim 8. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6) wherein the second write multiplexer transistor (the multiplexer 106) and the second write driver transistor (the transistor 204) each comprises an n-type metal-oxide semiconductor (NMOS) transistor (the transistor 204 may use as alternated nmos transistor).
Regarding dependent claim 11. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6) wherein the write driver logic circuit (a control circuit 112 connected to a write driver circuit 108, Figs. 1-2, 5-6) is further configured to switch off the first write driver transistor (the transistor 202) and to maintain the second write driver transistor (the transistor 204) off during the remaining second portion of the write operation in response to an assertion of a write clock signal (the control circuit 112 is operative to assist in a write operation in cell array 104 and provide a write path for the write operation when negative voltage generate circuit 110 is not enabled or enabled in response to the write assist signal, see at least in Figures 1-2 and 5-6, column 2, lines 57 to column 6, lines 32 and the related disclosures).
Regarding to independent claim 16. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6) comprising:
a column of bit-cells (a memory cell array 104 includes a plurality of Bit Cell, Figs. 1-2 and 5-6) including a bit line (a bit line BL, BLB, Figs 1-2);
a first write driver transistor (a first write driver transistor 202, Figs 2, 5-6) configured to charge the first bit line (the bit line BL, BLB) to a power supply voltage node (the lowest VDD voltage (positive power supply voltage)) in response to an assertion of a first control signal;
a second write driver transistor (a second write driver transistor 204, Figs. 2, 5-6) configured to ground the bit line (the bit line BL, BLB, the transistor 204 connected to the ground, Fig. 2, 5-6) in response to an assertion of a second control signal; and
a write driver logic circuit (a control circuit 112 connected to a write driver circuit 108, Figs. 1-2, 5-6) configured to invert a data in signal to form the first control signal (the first write driver transistor 202) and the second control signal (the first write driver transistor 204) during a write operation in which a write mask is not active and to assert the first control signal and to de-assert the second control signal during a first portion of a write operation in which the write mask is active (the control circuit 112 is operative to assist in a write operation in cell array 104 and provide a write path for the write operation when negative voltage generate circuit 110 is not enabled or enabled in response to the write assist signal, see at least in Figures 1-2 and 5-6, column 2, lines 57 to column 6, lines 32 and the related disclosures).
Regarding dependent claim 20. Nien et al in Figures 1-7 are directly discloses a serial read write memory (memory device 100, Figures 1-2 and Figures 5-6) wherein the first write driver transistor is a PMOS transistor (the transistor 202 is the type of pmos transistor) and wherein the second write driver transistor is an NMOS transistor (the transistor 204 may use as alternated nmos transistor).
Regarding claims 12 and 15, they encompass the same scope of invention as that of claims 1-2, 6-8, 11, 16 and 20, except they draft the invention in method format instead of apparatus format. Nien et al. teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claims 12 and 15, are therefore rejected in method format for the same reasons claims 1-2, 6-8, 11, 16 and 20, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
5. Claims 3-5, 9-10, 13-14 and 17-19 insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected dependent claims 3-5 and 9-10, the prior art fails to tech or suggest the claimed limitations, namely, wherein the write driver logic circuit comprises: a first inverter configured to invert the data in signal to produce a complement data in signal; a first logic gate configured to process the write mask signal with the complement data in signal to produce a first write mask data in signal; and a second logic gate configured to process the write mask signal with the data in signal to produce a second write mask data in signal that is a complement of the first write mask data in signal during the write operation in which the write mask signal is not asserted and equals the first write mask data in signal during the write operation in which the write mask signal is asserted, wherein the write driver logic circuit further comprises: a second inverter configured to invert the first write mask data in signal, the second inverter having an output terminal coupled to a gate of the first write driver transistor, further comprising: a first complement bit line for the first column of bitcells; and a third write driver transistor coupled between the first complement bit line and ground, wherein the write driver logic circuit further comprises a third inverter configured to invert the second write mask data in signal, the third inverter having an output terminal coupled to a gate of the third write driver transistor, wherein the first logic gate and the second logic gate each comprises a NAND gate and wherein the write driver logic circuit is further configured to process the first write mask data in signal and the second write mask data in signal to determine whether the write mask signal was asserted.
With respected dependent claims 13-14, the prior art fails to tech or suggest the claimed limitations, namely, further comprising: inverting the write mask signal to form an inverted write mask signal; processing the inverted write mask signal with a data in signal to form a first write mask data in signal; and processing the inverted write mask signal with a complement of the data in signal to form a second write mask data in signal, wherein performing the write operation to the selected column is responsive to the first write mask data in signal and to the second write mask data in signal and further comprising: inverting the write mask signal to form a first write driver control signal; and controlling whether a first write driver transistor coupled between a bit line in the pair of bit lines and ground is on or off responsive to the first write driver control signal.
With respected dependent claims 17-18, the prior art fails to tech or suggest the claimed limitations, namely, further comprising: a complement bit line for the column of bitcells; a third write driver transistor configured to charge the complement bit line to a power supply voltage in response to an assertion of a third control signal; and a fourth write driver transistor configured to ground the complement bit line in response to an assertion of a fourth control signal, wherein the write driver logic circuit is further configured to form the third control signal and the fourth control signal to equal the data in signal during the write operation in which the write mask is not active, wherein the write driver logic circuit is further configured to assert the third control signal and to de-assert the fourth control signal during the first portion of the write operation in which the write mask is active.
With respected dependent claim 19, the prior art fails to tech or suggest the claimed limitations, namely, the write driver logic circuit is further configured to de-assert the first control signal and the second control signal during a second portion of the write operation in which the write mask is active.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gupta et al (US. 11,004,503 B1) discloses the device may include write assist circuitry having pass gates coupled to the bitcells via bitlines.
Liaw (US. 10,381,070 B2) discloses an integrated circuit a plurality of first memory cells and a plurality of second memory cells.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov