CTNF 18/648,331 CTNF 74165 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07 August 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-6, 15, 17, 22 and 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by WIPO Publication No. WO/2023/241687 ( Hu et al ) . Regarding claim 1, Hu et al . discloses: “an apparatus for wireless communication (FIG. 17:1710; [0049]: “ apparatus 1710 … may be a part of an electronic apparatus … such as a portable or mobile apparatus, a wearable apparatus, a wireless communication apparatus or a computing apparatus”) , comprising: at least one memory (FIG. 17: 1714; [0053]: “ apparatus 1710 may further include a memory 1714 coupled to processor 1712 and capable of being accessed by processor 1712 and storing data therein”) comprising computer-executable instructions; and one or more processors configured to execute the computer-executable instructions (FIG. 17: 1712) and cause the apparatus to: obtain a set of data bits ([0053]: “ processor 1712 of apparatus 1710 may receive a plurality of input bits ”; FIG. 18: 1810) ; encode the data bits ([0053]: “Moreover, processor 1712 may code the plurality of input bits”; FIG. 18: 1820) , based on at least a first nominal code rate (FIG. 18: 1822) ([0053]: “For instance, processor 1712 may encode the input bits by a LDPC encoder 1715 of processor 1712 using a base code rate”; FIG. 18: 1822 ) , to generate one or more codewords associated with a reduced nominal code rate that is lower than the first nominal code rate ([0055]: “Additionally, processor 1712 may perform either or both of a repeating operation and a shortening operation on an output of the LDPC encoder 1715 to result in an effective coding rate of coding the input bits that is lower than the base code rate ”; FIG. 18: 1824) ; and output the one or more codewords” ([0057]-[0063]: “codeword”) . With respect to claim 2, Hu et al . discloses: “the encoding involves at least one of: low density parity check (LDPC) encoding ([0008]: “ coding the plurality of input bits by: (i) encoding the input bits by a LDPC encoder of the processor using a base code rat e”) ; or binary convolutional code (BCC) encoding”. Regarding claim 3, Hu et al . discloses: “the encoding comprises: generating first codewords comprising coded bits; and repeating the coded bits of the first codewords to generate second codewords, wherein the one or more codewords comprise the second codewords” ([0038]: “ That is, a codeword generated by the LDPC encoder may be repeated by N x times before puncturing parity bits of the codeword and repeating data bits of the codeword for a number of times ”) . With respect to claim 4, Hu et al . discloses: “at least one of: the repetition comprises repeating the coded bits of the first codewords N times; the size of one of the second codewords is N times the size of one of the first codewords ([0038]: “ That is, a codeword generated by the LDPC encoder may be repeated by N x times before puncturing parity bits of the codeword and repeating data bits of the codeword for a number of times ”) ; or the reduced nominal code rate is (1/N) of the first nominal code rate”. Regarding claim 5, Hu et al . discloses: “a quantity of shortening bits in each of the second codewords is a multiple of N” (“a coding rate R of 1/2 may be used as the base coding rate to achieve an effective low coding rate by N times (Nx) of repetitions, Nx = 2, 3, 4, 6, 8 or 16 corresponding to the effective coding rate (eR) = 1/4, 1/6, 1/8, 1/12, 1/16, 1/24 or 1/32 . In a second option or approach (Approach-2) , R = 1/2 may be used as the base coding rate to achieve a low effective coding rate eR = 1/3, 1/4, 1/6 or 1/8 by a “default shortening” operation ”) . With respect to claim 6, Hu et al . discloses: “generating first codewords comprises: encoding the data bits based on the first nominal code rate to obtain first coded bits (FIG. 18: 1822; [0069]: “At 1822, process 1800 may involve processor 1712 encoding the input bits by a LDPC encoder 1715 of processor 1712 using a base code rate ”) ; and encoding the first coded bits based on a second nominal code rate to obtain the first codewords” (FIG. 18: 1824; [0070]: “At 1824, process 1800 may involve processor 1712 performing either or both of a repeating operation and a shortening operation on an output of the LDPC encoder 1715 to result in an effective coding rate of coding the input bits that is lower than the base code rate ”) . Regarding claim 15, Hu et al . discloses: “the encoding comprises: encoding the set of data bits based on the first nominal code rate to generate first codewords (FIG. 18: 1822; [0069]: “At 1822, process 1800 may involve processor 1712 encoding the input bits by a LDPC encoder 1715 of processor 1712 using a base code rate ”) ; and further encoding the first codewords based on at least a second nominal code rate to generate second codewords that have the reduced nominal code rate that is a function of at least the first code rate and the second code rate ([0055]: “Additionally, processor 1712 may perform either or both of a repeating operation and a shortening operation on an output of the LDPC encoder 1715 to result in an effective coding rate of coding the input bits that is lower than the base code rate”; FIG. 18: 1824 ), wherein the one or more codewords comprise the second codewords” ([0038]: “ That is, a codeword generated by the LDPC encoder may be repeated by N x times before puncturing parity bits of the codeword and repeating data bits of the codeword for a number of times ”) . Regarding claim 17, Hu et al . discloses: “the further encoding comprises performing at least one of a fixed quantity of puncturing of parity bits or a fixed quantity of repetition of data bits” ([0038]: “ That is, a codeword generated by the LDPC encoder may be repeated by N x times before puncturing parity bits of the codeword and repeating data bits of the codeword for a number of times ”) . With respect to claim 22, Hu et al . discloses: “the one or more processors are further configured to cause the apparatus to at least one of: adjust a nominal codeword size based on a nominal codeword size of the second codewords; or adjust at least one of a quantity of coded bits, a quantity of shortening bits (FIG. 18: 1824; [0070]: “At 1824, process 1800 may involve processor 1712 performing either or both of a repeating operation and a shortening operation on an output of the LDPC encoder 1715 to result in an effective coding rate of coding the input bits that is lower than the base code rate”) , or a quantity of data bits based on the reduced nominal code rate”. With respect to claim 30, Hu et al . discloses: “a method for wireless communication at a wireless node (FIG. 18; [0066]: “FIG. 18 illustrates an example process 1800”; “ process 1800 may represent an aspect of the proposed concepts and schemes pertaining to LDPC low coding rate designs for next-generation WLANs ”) , comprising: obtaining a set of data bits (FIG. 18:1810; [0067]: “At 1810, process 1800 may involve processor 1712 of apparatus 1710 receiving a plurality of input bits ”) ; encoding the data bits (FIG. 18: 1820; [0068]: “At 1820, process 1800 may involve processor 1712 coding the plurality of input bits ”) , based on at least a first nominal code rate (FIG. 18: 1822; [0069]: “At 1822, process 1800 may involve processor 1712 encoding the input bits by a LDPC encoder 1715 of processor 1712 using a base code rate ”) , to generate one or more codewords associated with a reduced nominal code rate that is lower than the first nominal code rate (FIG. 18: 1824; [0070]: “At 1824, process 1800 may involve processor 1712 performing either or both of a repeating operation and a shortening operation on an output of the LDPC encoder 1715 to result in an effective coding rate of coding the input bits that is lower than the base code rate” ) ; and outputting the one or more codewords” ([0057]-[0063]: “codeword”) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 7, 16, 18, 23 - 29 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al . in view of US Patent Application Publication No. 20100275090 ( Kuri et al ) . Claims 7 and 18 are dependent upon claims 3 and 1, respectively. As discussed above, claims 3 and 1 are disclosed by Hu et al . Thus, those limitations of claims 3 and 1 that are recited in claims 7 and 18, respectively, are also disclosed by Hu et al . However, Hu et al . does not clearly disclose the remaining limitations of the claim. To that end, regarding claim 7, Kuri et al . discloses: “generating the first codewords comprises: forming systematic bits by appending padding bits to the data bits, encoding the systematic bits to generate parity bits, and appending the parity bits to the data bits to generate the first code words” ([0010]: “ a configuration that includes an insertion section that inserts a padding bit in a first bit sequence to generate a second bit sequence, an encoding section that performs LDPC encoding using a parity check matrix on the second bit sequence to obtain a codeword comprising a systematic bit and a parity bits ”) . It is respectfully submitted that it would have been obvious to one of ordinary skill in the art at the time of the invention to combine Hu et al . with the invention of Kuri et al . in order to provide a codeword comprising systematic bits and parity bits (e.g., see Kuri et al . @ [0010] ). With respect to claim 16, Hu et al . discloses: “the one or more processors” (FIG. 17: 1714; [0053]: “apparatus 1710 may further include a memory 1714 coupled to processor 1712 and capable of being accessed by processor 1712 and storing data therein”) . In addition, Kuri et al . discloses: “to cause the apparatus to: form a set of systematic bits by appending a set of padding bits to the set of data bits prior to the encoding, encoding the systematic bits based on the first nominal code rate to generate the first codewords and further encoding the first codewords based on the second nominal code rate to generate the second codewords” ([0010]: “a configuration that includes an insertion section that inserts a padding bit in a first bit sequence to generate a second bit sequence, an encoding section that performs LDPC encoding using a parity check matrix on the second bit sequence to obtain a codeword comprising a systematic bit and a parity bits”) . With respect to claim 18, Hu et al . discloses: “generating second codewords of a second size with the data bits and the parity bits, wherein the one or more codewords comprise the second codewords” ([0038]: “ That is, a codeword generated by the LDPC encoder may be repeated by N x times before puncturing parity bits of the codeword and repeating data bits of the codeword for a number of times ”) . In addition, Kuri et al . discloses: “the one or more processors are further configured to cause the apparatus to: form systematic bits by appending padding bits to the data bits, wherein the encoding comprises encoding the systematic bits to generate first codewords of a first size with parity bits ([0010]: “ a configuration that includes an insertion section that inserts a padding bit in a first bit sequence to generate a second bit sequence, an encoding section that performs LDPC encoding using a parity check matrix on the second bit sequence to obtain a codeword comprising a systematic bit and a parity bits ”) . Claim 23 is dependent upon claim 1. As discussed above, claim 1 is disclosed by Hu et al . Thus, those limitations of claim 23 that are recited in claim 1 are also disclosed by Hu et al . However, Hu et al . does not clearly disclose the remaining limitations of claim 23. To that end, Kuri et al . discloses: ”at least one transceiver (FIG. 1: 106, 108) configured to transmit the one or more codewords, wherein the apparatus is configured as a wireless station” (FIG. 1: 106; [0031]: “ Radio transmitting section 106 performs transmission processing such as D/A conversion, amplification, and up-conversion on the multiplex signal, and transmits the resulting signal to the receiving-side radio communication apparatus from an antenna 107 ”; Fig. 108; [0032]: “a radio receiving section 108 receives a control signal transmitted from the receiving-side radio communication apparatus via antenna 107, performs reception processing ) . It is respectfully submitted that it would have been obvious to one of ordinary skill in the art at the time of the invention to combine Hu et al. with the invention of Kuri et al. in order to provide a radio transmitter/receiver (transceiver) for transmission processing (e.g., see Kuri et al . @ [0031]-[0032] ). With respect to claim 24, Hu et al . discloses: ”an apparatus for wireless communication (FIG. 17:1710; [0049]: “ apparatus 1710 … may be a part of an electronic apparatus … such as a portable or mobile apparatus, a wearable apparatus, a wireless communication apparatus or a computing apparatus”) , comprising: at least one memory (FIG. 17: 1714) comprising computer-executable instructions; and one or more processors configured to execute the computer-executable instructions ([0053]: “ apparatus 1710 may further include a memory 1714 coupled to processor 1712 and capable of being accessed by processor 1712 and storing data therein”). and In addition, Kuri et al . discloses: “cause the apparatus to obtain one or more codewords associated with a reduced nominal code rate; and decode the one or more codewords, based on at least a first nominal code rate, to recover a set of data bits, wherein the first nominal code rate is higher than the reduced nominal code rate” ([Claim 5]: “a padding section that pads a received bit sequence with a padding bit to generate first received data, and also pads the first received data with a logarithmic likelihood ratio 0 bit at parity bit positions from a parity bit position corresponding to a variable node in descending order of total number of connections to the padding bit via a check node, to generate second received data; and a decoding section that performs LDPC decoding on the second received data using a parity check matrix to obtain a decoded bit sequence ”) . Regarding claim 25, Kuri et al . discloses: “the decoding involves at least one of: low density parity check (LDPC) decoding ([Claim 5]: “ a decoding section that performs LDPC decoding on the second received data using a parity check matrix to obtain a decoded bit sequence ”) ; or binary convolutional code (BCC) decoding. With respect to claim 26, Kuri et al . discloses:” the decoding comprises: decoding the one or more codewords; and combining decoded bits after the decoding” ([0068]: “Using a parity check matrix identical to the parity check matrix used by LDPC encoding section 102 (FIG. 1), LDPC decoding section 206 performs LDPC decoding on data input from bit adjustment section 205, to obtain a received bit sequence ”) . Regarding claim 27, Kuri et al . discloses: “the decoding comprises: decoding the one or more codewords based on the first nominal code rate to obtain first codewords; and decoding the first codewords based on a second nominal code rate” (FIG. 5; [0102]: “the number of punctured parity bits may also be determined based on the difference between the mother coding rate and coding rate R of an LDDC codeword ”; [Claim 5]: “ a decoding section that performs LDPC decoding on the second received data using a parity check matrix to obtain a decoded bit sequence”) . With respect to claim 28, Kuri et al . discloses: “the decoding comprises: decoding the one or more codewords to obtain a set of systematic bits that includes a set of padding bits appended to the set of data bits” ([0098]: “bit adjustment section 205 of receiving-side radio communication apparatus 200 (FIG. 5) identifies systematic bit positions at which padding is performed with padding bits using the same method as padding bit insertion section 101) . Regarding claim 29, Kuri et al . discloses: “further comprising at least one transceiver (FIG. 5: 202, 211) configured to receive the one or more codewords, wherein the apparatus is configured as a wireless station” (FIG. 5: 200; [0063]: “In receiving-side radio communication apparatus 200, a radio receiving section 202 receives a multiplex signal transmitted from transmitting-side radio communication apparatus 100 (FIG. 1) via an antenna 201”; [0073]: Radio transmitting section 211 performs transmission processing such as D/A conversion, amplification, and up-conversion on the control signal, and transmits the resulting signal to transmitting-side radio communication apparatus 100 (FIG. 1) from antenna 201 ”) . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hu et al . in view of US Patent Application Publication No. 202190372714 ( Xu et al .) . Claim 8 is dependent upon claim 1. As discussed above, claim 1 is disclosed by Hu et al . Thus, those limitations of claim 1 that are recited in claim 8 are also disclosed by Hu et al . In addition with respect to claim 8, Hu et al . further discloses: “the encoding comprises: generating first codewords (FIG. 18: 1822; [0069]: “At 1822, process 1800 may involve processor 1712 encoding the input bits by a LDPC encoder 1715 of processor 1712 using a base code rate ”) ; repeating coded bits associated with the first codewords to generate second codewords ([0038]: “ That is, a codeword generated by the LDPC encoder may be repeated by N x times before puncturing parity bits of the codeword and repeating data bits of the codeword for a number of times ”) . However, Hu et al . does not clearly disclose the remaining limitations of the claim. To that end, Xu et al . discloses: “applying a mask sequence to the repeated coded bits within each of the second codewords to generate the one or more codewords” ([0088]: “ The final puncturing pattern functions as a mask, puncturing N-M coded bits of the polar codeword to which it is applied ”) . It is respectfully submitted that it would have been obvious to one of ordinary skill in the art at the time of the invention to combine Hu et al. with the invention of Xu et al. in order to provide a mask sequence to codded bits within a codeword (e.g., see Xu et al . @ [0088] ) . 07-21-aia AIA Claim s 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al . in view of Xu et al .. and Official Notice . Claims 9-10 are ultimately dependent upon claim 8. As discussed above, claim 8 is disclosed by the combination of Hu et al . and Xu et al . Thus, those limitations of claim 8 that are recited in claims 9-10 are also disclosed by the combination of Hu et al . and Xu et al . However, the combination of Hu et al . and Xu et al . does not clearly disclose the remaining limitations of claims 9-10. To that end, the Examiner takes Official Notice that the limitations of claims 9-10 of: “the mask sequence is based on a known sequence used in a long training field (LTF).” respectively, are well known in the art . 07-21-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Hu et al . in view of US Patent Application Publication No. 20140023156 ( Zhang et al ) . Claim 11 is dependent upon claim 1. As discussed above, claim 1 is disclosed by Hu et al . Thus, those limitations of claim 1 that are recited claim 11 are also disclosed by Hu et al . In addition, regarding claim 11, Hu et al . further discloses: “the encoding comprises: generating first codewords comprising coded bits (FIG. 18: 1822; [0069]: “At 1822, process 1800 may involve processor 1712 encoding the input bits by a LDPC encoder 1715 of processor 1712 using a base code rate ”) ; and repeating the coded bits of the first codewords to generate second codewords ([0038]: “ That is, a codeword generated by the LDPC encoder may be repeated by N x times before puncturing parity bits of the codeword and repeating data bits of the codeword for a number of times ”) . However, Hu et al . does not clearly disclose the remaining limitations of the claim. To that end, Zhang et al . discloses: “performing constellation mapping of the repeated coded bits to generate orthogonal frequency division multiplexing (OFDM) symbols ([0052]: “ the coded bits are then provided to the constellation mapping unit 306, which maps the coded bits to constellation points corresponding to OFDM tones of the base bandwidth ”) ; and applying a mask sequence ([0056]: “ training sequences corresponding to the multiple spatial streams are mapped ”) to data tones of the OFDM symbols when outputting the one or more codewords” ([0052]:”Then, tone duplication and insertion unit 308 duplicates the resulting OFDM tones and/or inserts additional OFDM tones to generate a wider bandwidth OFDM symbol , such as an 80 MHz OFDM symbol or a 160 MHz OFDM symbol”) . It is respectfully submitted that it would have been obvious to one of ordinary skill in the art at the time of the invention to combine Hu et al . with the invention of Zhang et al . in order to provide OFDM constellation mapping for coded bits (e.g., see Zhang et al .@ [0052] ) . 07-21-aia AIA Claim s 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al . in view of Zhang et al . and Official Notice . Claims 12-14 are ultimately dependent upon claim 11. As discussed above, claim 11 is disclosed by the combination of Hu et al . and Zhang et al . Thus, those limitations of claim 11 that are recited in claims 12-14 are also disclosed by the combination of Hu et al . and Zhang et al . However, the combination of Hu et al . and Zhang et al . does not clearly disclose the remaining limitations of claims 12-14. To that end, the Examiner takes Official Notice that the limitations of claims 12-14 of: “the mask sequence is based on a sequence of values that comprise +1 and - 1 values”; “the mask sequence is based on a known sequence of +1 and -1 values”; and “the mask sequence is based on a known sequence used in a long training field (LTF)”, respectively, are well known in the art . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 19-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MYRON K WYCHE whose telephone number is (571)272-3390. The examiner can normally be reached 7:30 am - 3:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kathy Wang-Hurst can be reached at 571-270-5371. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Myron Wyche/ 28 March 2026 Primary Examiner AU2644 Application/Control Number: 18/648,331 Page 2 Art Unit: 2644 Application/Control Number: 18/648,331 Page 3 Art Unit: 2644 Application/Control Number: 18/648,331 Page 4 Art Unit: 2644 Application/Control Number: 18/648,331 Page 5 Art Unit: 2644 Application/Control Number: 18/648,331 Page 6 Art Unit: 2644 Application/Control Number: 18/648,331 Page 7 Art Unit: 2644 Application/Control Number: 18/648,331 Page 8 Art Unit: 2644 Application/Control Number: 18/648,331 Page 9 Art Unit: 2644 Application/Control Number: 18/648,331 Page 10 Art Unit: 2644 Application/Control Number: 18/648,331 Page 11 Art Unit: 2644 Application/Control Number: 18/648,331 Page 12 Art Unit: 2644 Application/Control Number: 18/648,331 Page 13 Art Unit: 2644 Application/Control Number: 18/648,331 Page 14 Art Unit: 2644