DETAILED ACTION
1. This Office action is in response to the amendment filed on 04/10/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
4. Claims 14 and 16 are objected to because of the following informalities:
Claim 14 recites “… generating an abnormal signal corresponding to a corresponding one of the plurality…”. However, it appears that it should recite ““… generating an abnormal signal corresponding to one of the plurality…”.
Claim 16 recites “… generating another abnormal signal corresponding to a corresponding one of…”. However, it appears that it should recite ““… generating another abnormal signal corresponding to one of…”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claim(s) 1 - 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Hiramatsu et al (US Pub. No. 2006/0186892 A1) and Tallam et al (US Pub. No. 2015/0171772 A1); (hereinafter Hiramatsu et al and Tallam et al).
Regarding claim 1, Hiramatsu et al [e.g., Figs. 1 - 9] discloses a power supply system [e.g., a three-phase converter] comprising: a voltage conversion circuit configured to convert an alternating current voltage into a DC voltage [e.g., AC to DC converter]; and at least one voltage detector [e.g., branch containing resistors (2, 5), coupled to operational amplifier 8 to A/D converter 11 coupled to CPU 14 detecting voltage of phase r] comprising: a voltage dividing circuit coupled to the voltage conversion circuit to receive the alternating current voltage [e.g., branch with voltage dividing resistors (2, 5) receiving phase r, For examination purposes, the examiner will interpret the term "coupled" in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], wherein the voltage dividing circuit comprises a plurality of impedance elements and a plurality of voltage dividing nodes to output a plurality of divided voltages [e.g., branch containing resistors (2, 5) and nodes]; a phase voltage detection circuit [e.g., phase detected by operational amplifier 8 and A/D converter 11] coupled to one of the plurality of voltage dividing nodes of the voltage dividing circuit [e.g., coupled to nodes between resistors (2, 5)] to generate a phase voltage detection signal based on one of the plurality of divided voltages [e.g., generating signal r-n, p. 0043 recites "In order to detect the voltage r-n of the r-phase as seen from the negative pole side bus N, the voltage r1 obtained by dividing the r-phase voltage with the resistors (2, 5) has to be inputted into the AD converter 11."]; and a line voltage detection circuit [e.g., A/D converters 11 - 13 and CPU 14] coupled to a part of the plurality of voltage dividing nodes of the voltage dividing circuit [e.g., coupled to nodes between resistors via operational amplifier] to generate a line voltage detection signal based on the part of the plurality of divided voltages [e.g., line voltage calculated by CPU 14 during open- phase period, p. 0045 recites "The CPU 14 calculates the difference between the values of two phases to obtain the sine wave line voltages r-s, s-t and t-r as shown in FIG. 6". It continues on p. 0047 recites "However, when there is an open-phase, the signs of two of the line voltages on the basis of the open-phase voltage become different with each other and the two of the line voltages exhibits a half-wave rectification waveform with a phase difference of 180.degree.. Accordingly, an open-phase can be detected by making the CPU 14 monitor that the signs of two of the three line voltages are different and the two of the line voltages exhibits a half-wave rectification waveform with a phase difference of 180.degree."].
Hiramatsu et al does not disclose wherein the plurality of divided voltages generated by the voltage dividing circuit are provided to the phase voltage detection circuit and the line voltage detection circuit to make the phase voltage detection circuit and the line voltage detection circuit receive same divided voltages.
Tallam et al [e.g., Figs 1 and 2] teaches wherein the plurality of divided voltages generated by the voltage dividing circuit [e.g., divided voltages 173u, 173v and 173w via dividing resistors R1-R3, R4 - R6 and R7-R0, respectively] are provided to the phase voltage detection circuit [e.g., provided to voltage divider circuit 174u, 174v and 174w] and the line voltage detection circuit [e.g., provided to op amps 177a and 177b] to make the phase voltage detection circuit and the line voltage detection circuit receive same divided voltages [e.g., same divided voltage from 173u, 173v and 173w via dividing resistors R1-R3, R4 - R6 and R7-R0, respectively]
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al wherein the plurality of divided voltages generated by the voltage dividing circuit are provided to the phase voltage detection circuit and the line voltage detection circuit to make the phase voltage detection circuit and the line voltage detection circuit receive same divided voltages as suggested by Tallam et al to detect output voltage measurement, including without limitation line-neutral voltages, line-ground voltages, etc..
Regarding claim 2, Hiramatsu et al [e.g., Figs. 1 - 9] discloses a plurality of conversion subcircuits [e.g., rectifying circuit 15], the plurality of conversion subcircuits is configured to receive a plurality of alternating current voltages of different phases [e.g., configured to receive phase voltages r, S and t], and the voltage dividing circuit further comprises: a plurality of voltage dividing subcircuits [e.g., branches containing voltage dividing resistors (2, 5), (3, 6), (4, 7)] coupled to the plurality of conversion subcircuits [e.g., branches containing voltage dividing resistors (2, 5), (3, 6), (4, 7) coupled to rectifying circuit 15] and a floating node [e.g., coupled to neutral point node N1. For examination purposes, the examiner will interpret the term "floating node" to mean the voltage neutral point] to generate the plurality of divided voltages based on the plurality of alternating current voltages [e.g., generate voltages r-n, s-n and t-n], wherein the phase voltage detection circuit generates the phase voltage detection signal based on a reference voltage of the floating node and the one of the plurality of divided voltages [e.g., phase voltages r-n, s-n and t-n based on phase voltages and neutral reference].
Regarding claim 5, Hiramatsu et al [e.g., Figs. 1 - 9] discloses wherein the line voltage detection circuit comprises a plurality of amplifier circuits [e.g., operational amplifiers 8 - 10 coupled to A/D converters 11 - 13].
Hiramatsu et al does not disclose each of the plurality of amplifier circuits is coupled to two of the plurality of voltage dividing subcircuits so as to generate the line voltage detection signal based on two of the plurality of divided voltages. Tallam et al [e.g., Figs. 1 - 2] teaches each of the plurality of amplifier circuits is coupled two of the plurality of voltage dividing subcircuits so as to generate the line voltage detection signal based on two of the plurality of divided voltages [e.g., op amps 177a and 177, p. 0024 recites “…the first op amp circuit 177a provides a buffered output voltage representing the line-line voltage between the inverter output phases "U" and "V"”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al with each of the plurality of amplifier circuits is coupled two of the plurality of voltage dividing subcircuits so as to generate the line voltage detection signal based on two of the plurality of divided voltages as suggested by Tallam et al to provide a buffer line to line measurement.
8. Claim(s) 3 - 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hiramatsu et al (US Pub. No. 2006/0186892 A1), Tallam et al (US Pub. No. 2015/0171772 A1) and Masahiro et al (JP 2014219266 A); (hereinafter Hiramatsu et al, Tallam et al and Masahiro et al).
Regarding claim 3, Hiramatsu et al discloses the claimed invention except for a plurality of amplifier circuits, one input terminal of each of the plurality of amplifier circuits is coupled to the floating node, another input terminal of each of the plurality of amplifier circuits is coupled to the floating node and one of the plurality of voltage dividing subcircuits.
Masahiro et al [e.g., Fig. 3] teaches a plurality of amplifier circuits [e.g., differential amplifiers A1 - A3], one input terminal of each of the plurality of amplifier circuits is coupled to the floating node [e.g., coupled to common line (COM) via resistors R1 - R3], another input terminal of each of the plurality of amplifier circuits is coupled to the floating node [e.g., input of differential amplifiers A1 - A3 coupled to common line (COM) via resistors Ru2, Rv2 and Rw2] and one of the plurality of voltage dividing subcircuits [e.g., coupled to nodes between resistance voltage dividing circuits 121 - 123 and resistors Ru2, Rv2 and Rw2].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al with wherein the phase voltage detection circuit comprises a plurality of amplifier circuits, one input terminal of each of the plurality of amplifier circuits is coupled to the floating node, another input terminal of each of the plurality of amplifier circuits is coupled to the floating node and one of the plurality of voltage dividing subcircuits as suggested by Masahiro et al to reduce or suppress fluctuations in the potential of the common wiring.
Regarding claim 4, Hiramatsu et al discloses the claimed invention except for a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits.
Masahiro et al [e.g., Fig. 3] teaches a plurality of buffer circuits [e.g., filters F1 - F3] coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits [e.g., coupled to differential amplifiers A1 - A3, p. 0031 - 0032 recites "The buffer B is an example of the “filter” according to the present invention, and is not limited to the voltage follower circuit. For example, instead of a voltage follower circuit, … Moreover, the input impedance of the inverter is high, while the output impedance is low. For this reason, similarly to the voltage follower, fluctuations in the potential of the common wiring line COM can be suppressed. Alternatively, the “filter” according to the present invention may be an RC circuit….. However, when an RC circuit is provided in each of the plurality of voltage detection circuits, the characteristics of each RC circuit may be different mainly due to variations in capacitors. The voltage follower circuit is more preferable because the influence of variation is relatively small."].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits as suggested by Masahiro et al to reduce the influence of variations.
Regarding claim 6, Hiramatsu et al discloses the claimed invention except for wherein the line voltage detection circuit further comprises a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits.
Masahiro et al [e.g., Fig. 3] teaches wherein the line voltage detection circuit further comprises a plurality of buffer circuits [e.g., filters F1 - F3] coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits [e.g., coupled to differential amplifiers A1 - A3, p. 0031 - 0032 recites "The buffer B is an example of the “filter” according to the present invention, and is not limited to the voltage follower circuit. For example, instead of a voltage follower circuit, … Moreover, the input impedance of the inverter is high, while the output impedance is low. For this reason, similarly to the voltage follower, fluctuations in the potential of the common wiring line COM can be suppressed. Alternatively, the “filter” according to the present invention may be an RC circuit….. However, when an RC circuit is provided in each of the plurality of voltage detection circuits, the characteristics of each RC circuit may be different mainly due to variations in capacitors. The voltage follower circuit is more preferable because the influence of variation is relatively small."].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al wherein the line voltage detection circuit further comprises a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits as suggested by Masahiro et al to reduce the influence of variations.
9. Claim(s) 7 - 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hiramatsu et al (US Pub. No. 2006/0186892 A1) in view of Tallam et al (US Pub. No. 2015/0171772 A1), Masahiro et al (JP 2014219266 A) and Miyake et al (US Pub. No. 2020/0044457 A1); (hereinafter Hiramatsu et al, Tallam et al, Masahiro et al and Miyake et al).
Regarding claim 7, Hiramatsu et al discloses the claimed invention except for wherein the voltage conversion circuit comprises a plurality of protection elements and a plurality of power switching elements, and the at least one voltage detector comprises: a first voltage detector coupled to the plurality of protection elements and configured to detect a plurality of first phase voltage detection signals; and a second voltage detector coupled to a plurality of detection nodes between the plurality of protection elements and the plurality of power switching elements, and being configured to detect a plurality of second phase voltage detection signals; wherein the power supply system further comprises a controller, the controller is coupled to the at least one voltage detector to receive the plurality of first phase voltage detection signals and the plurality of second phase voltage detection signals.
Miyake et al [e.g., Fig. 1 teaches wherein the voltage conversion circuit comprises a plurality of protection elements [e.g., fuses FR, FS and FT] and a plurality of power switching elements [e.g., switching section 5], and the at least one voltage detector [e.g., voltage detected by DC voltage detecting section 7 supplied to diagnostic device 3]comprises: a first voltage detector coupled to the plurality of protection elements and configured to detect a plurality of first phase voltage detection signals [e.g., voltage detecting section 7 coupled to fuses FR, FS and FT and configured to detect a pattern of DC voltage obtained p. 0066 recites “The diagnostic device 3 controls the inrush current preventing section 4 and the switching section 5, and determines an abnormal region of the converter circuit 2 based on AC voltages obtained from the AC voltage detecting sections 8R, 8S, and 8T and a measurement result pattern of a DC voltage obtained from the DC voltage detecting section 7.”]; and a second voltage detector coupled to a plurality of detection nodes between the plurality of protection elements and the plurality of power switching elements [e.g., AC voltage detecting sections 8R, 8S and 8T, p. 0064 recites “On the input side of the switching section 5, AC voltage detecting sections 8R, 8S and 8T for detecting the three-phase AC voltages inputted to the converter circuit 2 for each phase are provided”.], and being configured to detect a plurality of second phase voltage detection signals [e.g., detect voltages R_V, S_V, T_V]; wherein the power supply system further comprises a controller [e.g., diagnostic device 3], the controller is coupled to the at least one voltage detector to receive the plurality of first phase voltage detection signals and the plurality of second phase voltage detection signals [e.g., coupled to DC voltage detecting section 7 and AC voltage detecting section 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al wherein the voltage conversion circuit comprises a plurality of protection elements and a plurality of power switching elements, and the at least one voltage detector comprises: a first voltage detector coupled to the plurality of protection elements and configured to detect a plurality of first phase voltage detection signals; and a second voltage detector coupled to a plurality of detection nodes between the plurality of protection elements and the plurality of power switching elements, and being configured to detect a plurality of second phase voltage detection signals; wherein the power supply system further comprises a controller, the controller is coupled to the at least one voltage detector to receive the plurality of first phase voltage detection signals and the plurality of second phase voltage detection signals as suggested by Miyake et al to detect the voltage at multiple points to detect and diagnose an abnormality of the converter circuit.
Regarding claim 8, Hiramatsu et al discloses the claimed invention except for wherein the controller is configured to compare the plurality of second phase voltage detection signals to determine whether there is an abnormality in the plurality of second phase voltage detection signals or not.
Miyake et al [e.g., Fig. 1] teaches wherein the controller is configured to compare the plurality of second phase voltage detection signals to determine whether there is an abnormality in the plurality of second phase voltage detection signals or not [e.g., p. 0008 recites “The converter may further include: an AC voltage detecting section configured to detect the AC voltage; and a DC voltage detecting section configured to detect the DC voltage, wherein the diagnostic device may determine the abnormal region of the converter circuit based on the AC voltage or the DC voltage.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al wherein the controller is configured to compare the plurality of second phase voltage detection signals to determine whether there is an abnormality in the plurality of second phase voltage detection signals or not as suggested by Miyake et al to determine the abnormal region of the converter circuit based on the AC voltage.
Regarding claim 9, Hiramatsu et al discloses the claimed invention except for wherein when the controller determines that there is one of the plurality of second phase voltage detection signals to be abnormal, the controller generates an abnormal signal according to one of the plurality of protection elements corresponding to the one of the plurality of second phase voltage detection signals.
Miyake et al [e.g., Fig. 1] teaches wherein when the controller determines that there is one of the plurality of second phase voltage detection signals to be abnormal, the controller generates an abnormal signal according to one of the plurality of protection elements corresponding to the one of the plurality of second phase voltage detection signals.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al wherein when the controller determines that there is one of the plurality of second phase voltage detection signals to be abnormal, the controller generates an abnormal signal according to one of the plurality of protection elements corresponding to the one of the plurality of second phase voltage detection signals as suggested by Miyake et al to determine the abnormal region of the converter circuit based on the AC voltage.
10. Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hiramatsu et al (US Pub. No. 2006/0186892 A1) in view of Tallam et al (US Pub. No. 2015/0171772 A1), Masahiro et al (JP 2014219266 A), Miyake et al (US Pub. No. 2020/0044457 A1) and Hiramatsu et al_2 (US Pub. No. 2013/0058144 A1); (hereinafter Hiramatsu et al_1, Tallam et al, Masahiro et al, Miyake et al and Hiramatsu et al_2).
Regarding claim 10, Hiramatsu et al_1 discloses the claimed invention except for a power control circuit, the power control circuit is coupled to the controller to generate a phase-locked control signal based on the line voltage detection signal.
Hiramatsu et al_2 [e.g., Figs. 3 and 7] teaches a power control circuit [e.g., detection voltage adjustor 40 with PLL 70], the power control circuit is coupled to the controller to generate a phase-locked control signal based on the line voltage detection signal [e.g., generates Vq and phase ϴ from voltages VR and VT].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al_1 with a power control circuit, the power control circuit is coupled to the controller to generate a phase-locked control signal based on the line voltage detection signal as suggested by Hiramatsu et al_2 to track and synchronize the phase and frequency of the line voltages.
Response to Amendment
11. Applicant’s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner’s Note
12. Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
13. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
14. Claims 11 - 20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 11 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… coupling a first voltage detector to a plurality of first detection nodes of a medium voltage system cabinet, and coupling a second voltage detector to a plurality of second detection nodes of the medium voltage system cabinet, wherein the plurality of first detection nodes are coupled between a plurality of phase voltage input nodes and a plurality of first circuit elements, and the plurality of second detection nodes are coupled between the plurality of first circuit elements and a plurality of second circuit elements; obtaining a plurality of first phase voltage detection signals of the plurality of first detection nodes through the first voltage detector, and obtaining a plurality of second phase voltage detection signals of the plurality of second detection nodes through the second voltage detector; determining whether the plurality of first phase voltage detection signals and the plurality of second phase voltage detection signals are normal or not through a controller; and generating an abnormal signal when the plurality of first phase voltage detection signals are normal but one of the plurality of second phase voltage detection signals is abnormal.”
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
CN 111781419A (Zhou et al) discloses an integrated voltage detection and signal acquisition system for a medium-high voltage generator.
JP 2018066678A (Tamura) discloses a non-conduction detection device for detecting electrical non-conduction in semiconductor switching elements constituting AC switches.
16. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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