DETAILED ACTION
1. This Office action is in response the application filed on 04/27/2024.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
4. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
5. The information disclosure statement (IDS) submitted on 04/27/2024 and 02/25/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
6. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
7. Claim 5 is objected to because of the following informalities:
Claim 5 recites “…amplifier circuits is coupled two of the plurality of voltage dividing subcircuits…”. However, it appears that it should recite “…amplifier circuits are coupled to two of the plurality of voltage dividing subcircuits…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
9. Claim(s) 1 and 2 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2006/0186892 A1; (hereinafter Hiramatsu et al), cited in IDS as CN 100447574
Regarding claim 1, Hiramatsu et al [e.g., Figs. 1 - 9] discloses a power supply system [e.g., p. 0040 recites “FIG. 1 shows an embodiment of a three-phase converter according to the method of the present invention,…”] comprising: a voltage conversion circuit configured to convert an alternating current voltage into a DC voltage [e.g., AC to DC converter]; and at least one voltage detector comprising [e.g., branch containing resistors (2, 5), coupled to operational amplifier 8 to A/D converter 11 coupled to CPU 14 detecting voltage of phase r]: a voltage dividing circuit coupled to the voltage conversion circuit to receive the alternating current voltage [e.g., branch with voltage dividing resistors (2, 5) receiving phase r, For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], wherein the voltage dividing circuit comprises a plurality of impedance elements and a plurality of voltage dividing nodes to output a plurality of divided voltages [e.g., branch containing resistors (2, 5) and nodes]; a phase voltage detection circuit [e.g., phase detected by operational amplifier 8 and A/D converter 11] coupled to one of the plurality of voltage dividing nodes of the voltage dividing circuit [e.g., coupled to nodes between resistors (2, 5)] to generate a phase voltage detection signal based on one of the plurality of divided voltages [e.g., generating signal during open-phase, p. 0043 recites “In order to detect the voltage r-n of the r-phase as seen from the negative pole side bus N, the voltage r1 obtained by dividing the r-phase voltage with the resistors (2, 5) has to be inputted into the AD converter 11.”. It continues on p. 0047 recites “However, when there is an open-phase, the signs of two of the line voltages on the basis of the open-phase voltage become different with each other and the two of the line voltages exhibits a half-wave rectification waveform with a phase difference of 180.degree.. Accordingly, an open-phase can be detected by making the CPU 14 monitor that the signs of two of the three line voltages are different and the two of the line voltages exhibits a half-wave rectification waveform with a phase difference of 180.degree.. Furthermore, it also becomes possible to specify the opened phase. For example, in the case shown in FIG. 7, since the line voltage r-s among the respective line voltages exhibits a sine wave, it is possible to judge that the remaining phase, i.e., the t-phase, is open"]; and a line voltage detection circuit [e.g., A/D converters 11 - 13 and CPU 14] coupled to a part of the plurality of voltage dividing nodes of the voltage dividing circuit [e.g., coupled to nodes between resistors via operational amplifier] to generate a line voltage detection signal based on the part of the plurality of divided voltages [e.g., line voltage calculated by CPU 14 during open-phase period, p. 0045 recites “The CPU 14 calculates the difference between the values of two phases to obtain the sine wave line voltages r-s, s-t and t-r as shown in FIG. 6”. It continues on p. 0047 recites “However, when there is an open-phase, the signs of two of the line voltages on the basis of the open-phase voltage become different with each other and the two of the line voltages exhibits a half-wave rectification waveform with a phase difference of 180.degree.. Accordingly, an open-phase can be detected by making the CPU 14 monitor that the signs of two of the three line voltages are different and the two of the line voltages exhibits a half-wave rectification waveform with a phase difference of 180.degree.. Furthermore, it also becomes possible to specify the opened phase. For example, in the case shown in FIG. 7, since the line voltage r-s among the respective line voltages exhibits a sine wave, it is possible to judge that the remaining phase, i.e., the t-phase, is open"].
Regarding claim 2, Hiramatsu et al [e.g., Figs. 1 - 9] discloses a plurality of conversion subcircuits [e.g., rectifying circuit 15], the plurality of conversion subcircuits is configured to receive a plurality of alternating current voltages of different phases [e.g., configured to receive phase voltages r, s and t], and the voltage dividing circuit further comprises: a plurality of voltage dividing subcircuits [e.g., branches containing voltage dividing resistors (2, 5), (3, 6), (4, 7)] coupled to the plurality of conversion subcircuits [e.g., branches containing voltage dividing resistors (2, 5), (3, 6), (4, 7) coupled to rectifying circuit 15] and a floating node [e.g., coupled to neutral point node N1. For examination purposes, the examiner will interpret the term “floating node” to mean the voltage neutral point] to generate the plurality of divided voltages based on the plurality of alternating current voltages [e.g., generate voltages r-n, s-n and t-n], wherein the phase voltage detection circuit generates the phase voltage detection signal based on a reference voltage of the floating node and the one of the plurality of divided voltages [e.g., phase voltages r-n, s-n and t-n based on phase voltages and neutral reference].
Claim Rejections - 35 USC § 103
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
12. Claim(s) 3 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Hiramatsu et al in view of JP 2017085889 A; (hereinafter Hiramatsu et al and Masahiro et al), both cited in IDS’s
Regarding claim 3, Hiramatsu et al discloses the claimed invention except for a plurality of amplifier circuits, one input terminal of each of the plurality of amplifier circuits is coupled to the floating node, another input terminal of each of the plurality of amplifier circuits is coupled to the floating node and one of the plurality of voltage dividing subcircuits.
Masahiro et al [e.g., Fig. 3] teaches a plurality of amplifier circuits [e.g., differential amplifiers A1 - A3], one input terminal of each of the plurality of amplifier circuits is coupled to the floating node [e.g., coupled to common line (COM) via resistors R1 - R3], another input terminal of each of the plurality of amplifier circuits is coupled to the floating node [e.g., input of differential amplifiers A1 - A3 coupled to common line (COM) via resistors Ru2, Rv2 and Rw2] and one of the plurality of voltage dividing subcircuits [e.g., coupled to nodes between resistance voltage dividing circuits 121 - 123 and resistors Ru2, Rv2 and Rw2].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al with wherein the phase voltage detection circuit comprises a plurality of amplifier circuits, one input terminal of each of the plurality of amplifier circuits is coupled to the floating node, another input terminal of each of the plurality of amplifier circuits is coupled to the floating node and one of the plurality of voltage dividing subcircuits as suggested by Masahiro et al to amplify the potential difference between the divided voltage from the resistance voltage dividing circuit and the divided voltage from the resistance voltage dividing circuit and output a voltage to the microcomputer.
Regarding claim 4, Hiramatsu et al discloses the claimed invention except for a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits.
Masahiro et al [e.g., Fig. 3] teaches a plurality of buffer circuits [e.g., filters F1 - F3] coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits [e.g., coupled to differential amplifiers A1 - A3, p. 0031 - 0032 recites “The differential amplifier circuit 111 (first differential amplifier circuit) has a differential amplifier A1, input resistors R11 and R12, and a filter F1. The differential amplifier circuit 112 (second differential amplifier circuit) has a differential amplifier A2, input resistors R21 and R22, and a filter F2. The differential amplifier circuit 113 (third differential amplifier circuit) has a differential amplifier A3, input resistors R31 and R 32, and a filter F3. The non-inverting input terminal of the differential amplifier A1 receives the divided voltage V1. The inverting input terminal of the differential amplifier A1 receives the divided voltage V2. The differential amplifier A1 amplifies the potential difference between the divided voltage V1 and the divided voltage V2 and outputs it to the filter F1. The filter F1 removes the noise component contained in the output signal from the differential amplifier A1. Since the functions of the differential amplifier circuits 112 and 113 are equivalent to those of the differential amplifier circuit 111, detailed description thereof will not be repeated”. It continues on p. 0036 “Note that the buffer B is an example of the "filter" according to the present invention, and is not limited to a voltage follower circuit. For example, instead of a voltage follower circuit, a general purpose logic IC (Integrated Circuit) of an inverter can be used as a buffer. The gain of the inverter is approximately 1. Also, while the input impedance of the inverter is high, the output impedance is low. For this reason, it is possible to suppress fluctuation in the potential of the common wiring COM similarly to the voltage follower”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits as suggested by Masahiro et al to remove noise contained in the output signal from the differential amplifiers.
Regarding claim 5, Hiramatsu et al [e.g., Figs. 1 - 9] discloses wherein the line voltage detection circuit comprises a plurality of amplifier circuits [e.g., operational amplifiers 8 - 10 coupled to A/D converters 11 - 13].
Hiramatsu et al does not discloses each of the plurality of amplifier circuits is coupled two of the plurality of voltage dividing subcircuits so as to generate the line voltage detection signal based on two of the plurality of divided voltages.
Masahiro et al [e.g., Fig. 3] teaches each of the plurality of amplifier circuits [e.g., differential amplifiers A1 - A3] is coupled two of the plurality of voltage dividing subcircuits so as to generate the line voltage detection signal based on two of the plurality of divided voltages [e.g., coupled to nodes between resistance voltage dividing circuits 121 - 123 and resistors Ru2, Rv2 and Rw2].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al with each of the plurality of amplifier circuits is coupled two of the plurality of voltage dividing subcircuits so as to generate the line voltage detection signal based on two of the plurality of divided voltages as suggested by Masahiro et al to amplify the potential difference between the divided voltage from the resistance voltage dividing circuit and the divided voltage from the resistance voltage dividing circuit and output a voltage to the microcomputer.
Regarding claim 6, Hiramatsu et al discloses the claimed invention except for wherein the line voltage detection circuit further comprises a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits.
Masahiro et al [e.g., Fig. 3] teaches wherein the line voltage detection circuit further comprises a plurality of buffer circuits [e.g., filter F1 - F3] coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits [e.g., coupled to differential amplifiers A1 - A3, p. 0031 - 0032 recites “The differential amplifier circuit 111 (first differential amplifier circuit) has a differential amplifier A1, input resistors R11 and R12, and a filter F1. The differential amplifier circuit 112 (second differential amplifier circuit) has a differential amplifier A2, input resistors R21 and R22, and a filter F2. The differential amplifier circuit 113 (third differential amplifier circuit) has a differential amplifier A3, input resistors R31 and R 32, and a filter F3. The non-inverting input terminal of the differential amplifier A1 receives the divided voltage V1. The inverting input terminal of the differential amplifier A1 receives the divided voltage V2. The differential amplifier A1 amplifies the potential difference between the divided voltage V1 and the divided voltage V2 and outputs it to the filter F1. The filter F1 removes the noise component contained in the output signal from the differential amplifier A1. Since the functions of the differential amplifier circuits 112 and 113 are equivalent to those of the differential amplifier circuit 111, detailed description thereof will not be repeated”. It continues on p. 0036 “Note that the buffer B is an example of the "filter" according to the present invention, and is not limited to a voltage follower circuit. For example, instead of a voltage follower circuit, a general purpose logic IC (Integrated Circuit) of an inverter can be used as a buffer. The gain of the inverter is approximately 1. Also, while the input impedance of the inverter is high, the output impedance is low. For this reason, it is possible to suppress fluctuation in the potential of the common wiring COM similarly to the voltage follower”]..
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Hiramatsu et al wherein the line voltage detection circuit further comprises a plurality of buffer circuits coupled between the plurality of amplifier circuits and the plurality of voltage dividing subcircuits as suggested by Masahiro et al to remove noise contained in the output signal from the differential amplifiers.
Examiner’s Note
13. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
14. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
15. Claims 11 - 20 are allowed.
16. Claims 7 - 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
17. The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 7 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the voltage conversion circuit comprises a plurality of protection elements and a plurality of power switching elements, and the at least one voltage detector comprises: a first voltage detector coupled to the plurality of protection elements and configured to detect a plurality of first phase voltage detection signals; and a second voltage detector coupled to a plurality of detection nodes between the plurality of protection elements and the plurality of power switching elements, and being configured to detect a plurality of second phase voltage detection signals; wherein the power supply system further comprises a controller, the controller is coupled to the at least one voltage detector to receive the plurality of first phase voltage detection signals and the plurality of second phase voltage detection signals”.
The primary reason for the indication of the allowability of claim 11 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “a voltage detection method comprising: coupling a first voltage detector to a plurality of first detection nodes of a medium voltage system cabinet, and coupling a second voltage detector to a plurality of second detection nodes of the medium voltage system cabinet, wherein the plurality of first detection nodes are coupled between a plurality of phase voltage input nodes and a plurality of first circuit elements, and the plurality of second detection nodes are coupled between the plurality of first circuit elements and a plurality of second circuit elements; obtaining a plurality of first phase voltage detection signals of the plurality of first detection nodes through the first voltage detector, and obtaining a plurality of second phase voltage detection signals of the plurality of second detection nodes through the second voltage detector; determining whether the plurality of first phase voltage detection signals and the plurality of second phase voltage detection signals are normal or not through a controller; and generating an abnormal signal when the plurality of first phase voltage detection signals are normal but one of the plurality of second phase voltage detection signals is abnormal”.
Conclusion
18. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838