DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-11 in the “RESPONSE TO RESTRICTION REQUIREMENT” filed on August 27, 2026 and withdrawal of non-elected claims 12-20 are acknowledged.
Information Disclosure Statement
The references listed in the Information Disclosure Statement (IDS) submitted on April 28, 2024 have been considered by the Examiner.
Claim Objections
Claim 7 is objected to because of the following informality: on lines 2-3, “of the three different vertical levels” should be “of the at least three different vertical levels”. Appropriate correction is required.
Claim 9 is objected to because of the following informality: on line 2, “a second level” should be “the second vertical level”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, lines 1-5 recite: A moisture barrier for a semiconductor structure, the moisture barrier comprising: a solid bar that is tapered from an uppermost portion to a lowermost portion and extends along a length of the moisture barrier to form a collar that surrounds a designated area of the semiconductor structure configured to arrange at least one through silicon via (TSV). This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, it is unclear how the solid bar . . . extends along a length of the moisture barrier because the moisture barrier is not a separate recited element of claim 1. Rather, the moisture barrier is recited in the preamble as being comprised of a solid bar and a plurality of patterning assist lines. As another example, it is unclear what a collar that surrounds a designated area of the semiconductor structure configured to arrange at least one through silicon via (TSV) means. Is this language reciting a collar that surrounds a through silicon via (TSV) of the semiconductor structure or it reciting something else? What does “configured to arrange at least one through silicon via (TSV) mean? Are the semiconductor structure and/or through silicon via (TSV) structural elements of the claim? For purpose of examination, the Examiner is interpreting lines 1-5 of claim 1 as reciting: “A moisture barrier for a semiconductor structure, the moisture barrier comprising: a solid bar having a length that is tapered from an uppermost portion to a lowermost portion and having a shape of a collar that surrounds a designated area of the semiconductor structure that includes at least one through silicon via (TSV)” because of these ambiguities. Claims 2-11 are also rejected under 35 U.S.C. 112(b) because they depend, directly or indirectly, from claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0178589 A1 (Ku).
Regarding claim 1, Ku discloses, A moisture barrier for a semiconductor structure (semiconductor structure (100); FIG. 1; [0019]), the moisture barrier comprising:
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a solid bar (solid bar (140); first annotated FIG. 1, above, and FIGs. 7A-7D, below; [0029]) that is tapered (first annotated FIG. 1, above) from an uppermost portion (first annotated FIG. 1, above) to a lowermost portion (first annotated FIG. 1, above) and extends along a length (first annotated FIG. 1, above) of the moisture barrier to form a collar (annotated FIGs. 7A-7D) that surrounds a designated area (first annotated FIG. 1, above) of the semiconductor structure (100) configured to arrange at least one through silicon via (TSV) (through silicon via (TSV) (130); FIG. 1; [0029])1; and
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a plurality of patterning assist lines (plurality of patterning assist lines (116); first annotated FIG. 1, above; [0024]) that are arranged at different vertical levels (first annotated FIG. 1, above) adjacent the solid bar (140) within a footprint having a width (W) defined by a topmost level of the solid bar (140) (first annotated FIG. 1, above).
Regarding claim 2, Ku discloses, The moisture barrier according to claim 1, wherein:
the solid bar (140) is tapered (first annotated FIG. 1, above) so that the width (W) of the uppermost portion is a widest portion (first annotated FIG. 1, above); and
the patterning assist lines (116) each have different pitches (first annotated FIG. 1, above) at the different vertical levels (first annotated FIG. 1, above) of tapering of the solid bar (140).
Regarding claim 3, Ku discloses, The moisture barrier according to claim 1, wherein the patterning assist lines (116) have a same pitch at a particular vertical level of the different vertical levels of tapering of the solid bar (140) (second annotated FIG. 1, below).
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Regarding claim 4, Ku discloses, The moisture barrier according to claim 1, wherein:
the at least one TSV (130) is arranged in the designated area (first annotated FIG. 1, above) of the semiconductor structure (100); and
the moisture barrier extends at least along a Back End of Line (BEOL) ([0017]) of the semiconductor structure (100).
Regarding claim 5, Ku discloses, The moisture barrier according to claim 4, wherein a thickness of the patterning assist lines (116 and (patterning assist lines (118); FIG. 6; [0024)) on a particular vertical level of tapering of the solid bar (140) increases as a distance from the at least one TSV (130) decreases (second annotated FIG. 1, above).
Regarding claim 6, Ku discloses, The moisture barrier according to claim 1, further comprising at least three different vertical levels of tapering of the solid bar (140) at which the patterning assist lines (116) are arranged within the footprint of the solid bar (140) (first annotated FIG. 1, above).
Regarding claim 7, Ku discloses, The moisture barrier according to claim 6, wherein:
a first pitch of the patterning assist lines (116) is largest at a topmost first vertical level of the three different vertical levels (third annotated FIG. 1, below) of tapering of the solid bar (140);
a second pitch of the patterning assist lines (116) at a second vertical level below the topmost first vertical level that is smaller than the first pitch (third annotated FIG. 1, below); and
a third pitch of the patterning assist lines (116) at a third vertical level below the second vertical level that is smallest (third annotated FIG. 1, below).
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Regarding claim 8, Ku discloses, The moisture barrier according to claim 7, wherein the patterning assist lines (116) of the topmost first vertical level (third annotated FIG. 1, above) are connected (connected by 118; third annotated FIG. 1, above) to the patterning assist lines of (116) the second vertical level (third annotated FIG. 1, above).
Regarding claim 9, Ku discloses, The moisture barrier according to claim 7, wherein the patterning assist lines (116) of a second level (third annotated FIG. 1, above) are connected (connected by 118; third annotated FIG. 1, above) to the patterning assist lines (116) of the third vertical level (third annotated FIG. 1, above).
Regarding claim 10, Ku discloses, The moisture barrier according to claim 7, wherein:
the patterning assist lines (116) of the topmost first vertical level (third annotated FIG. 1, above) are connected (connected by 118; third annotated FIG. 1, above) to the patterning assist (116) lines of the second vertical level (third annotated FIG. 1, above); and
the patterning assist lines of the second vertical level (third annotated FIG. 1, above) are connected (connected by 118; third annotated FIG. 1, above) to the patterning assist lines (116) of the third vertical level (third annotated FIG. 1, above).
Regarding claim 11, Ku discloses, The moisture barrier according to claim 7, further comprising at least a second TSV (second TSV (118); FIG. 1; [0024]) arranged between the different vertical levels (first annotated FIG. 1, above) of the patterning assist lines (116).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure.
US 2022/0328429 A1 (Chen)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a semiconductor structure (FIG. 1B) may be predicably fabricated to include solid bars (solid bars (136, 140, 144, 148, 152, and 156) FIG. 1B; [0035]) that surround a through silicon via (TSV) (through silicon via (TSV) (133); FIG. 1B; [0025]) in a designated area of the semiconductor structure to form collars.
US 2024/0243078 A1 (Wu)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that moisture barriers (moisture barrier (110); FIG. 1; [0032]) may be predictably utilized on semiconductor structures (semiconductor structure (100); FIG. 1; [0030]) to prevent moisture ingress ([0032]).
US 2016/0148863 A1 (Chen)—Discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that patterning assist lines (patterning assist lines (102 and 104); FIG. 1A; [0002] may be predicably utilized during back end of line (BEOL) processing ([0002]) to define a keep out zone (KOZ) ([0002] for a through silicon via (TSV) (thought silicon via (TSV) (108); FIG 1A; [0002]).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see the rejection of claim 1 under 35 U.S.C. 112(b), above, for how this recited language of claim 1 is being interpreted for purpose of examination.
Prosecution Insights