DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 28 August 2026. Claims 1-12 are pending in this application; however, Claims 1-3 are withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, directed to a semiconductor device, in the reply filed on 28 August 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 4-7 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Bao et. al (CN 113725285 A).
Regarding Claim 4, Bao discloses (as shown in Fig. 18) A semiconductor device comprising:
a channel layer ([0151] The channel layer 11 may include a GaN layer 111) disposed on a substrate; ([0151] substrate 100) ([0151] the channel layer 11 generally needs to be formed on the substrate 100)
a barrier layer ([0151] an AlGaN barrier layer 112) disposed on the channel layer (111); ([0151] The channel layer 11 may include a GaN layer 111 and an AlGaN barrier layer 112 arranged in a stack, wherein the GaN layer 111 is located between the substrate 100 and the AlGaN barrier layer 112.)
a gate structure ([0153] the gate structure 14) disposed on the barrier layer (112); ([0153] Step S302: forming a gate structure 14 on the channel layer 11 to form a structure as shown in FIG. 13b.)
a first dielectric layer ([0155] lower dielectric layer 151) conformally disposed on the barrier layer (112) and the gate structure (14); ([0155] Step S303: forming a lower dielectric layer 151 covering the gate structure 14) (See Fig. 18, showing the first lower dielectric material layer 1511 on the barrier layer 112)
a source electrode ([0167] Step S306: forming the source electrode 12) and a drain electrode ([0167] Step S306: forming …the drain electrode 13) disposed at opposite sides of the gate structure (14) (See Fig. 18, showing the source electrode 12 and the drain electrode 13 on opposite sides of the gate structure 14)
and penetrating the first dielectric layer (151) to contact the barrier layer (112); (See Fig. 18)
a second dielectric layer ([0158] first upper dielectric layer 152) disposed on the first dielectric layer (151), ([0158] Step S304: forming a first upper dielectric layer 152 on the lower dielectric layer 151)
wherein the second dielectric layer (152) is disposed between the gate structure (14) and the drain electrode (13); (See Fig. 18, showing the first upper dielectric layer 152 between the gate structure 14 and the drain electrode 13)
and a field plate ([0167] the field plate 16) disposed between the source electrode (12) and the drain electrode (13) ([0168] Exemplarily, as shown in FIG. 17f, the field plate 16 includes a first extension 161 extending from the source 12 to the drain 13)
and partially covering the second dielectric layer (152), (See Fig. 18, showing the field plate 16 covers part of the first upper dielectric layer 152)
wherein the source electrode (12), the drain electrode (13), and the field plate (16) are made of the same ohmic contact metal. ([0103] , the source electrode 12, the drain electrode 13 and the field plate 14 can be formed by etching the same conductive layer) ([0105] The source 12 and the drain 13 can form an ohmic contact with the GaN layer 111)
Regarding Claim 5, Bao further discloses (as shown in An. Fig. 18) wherein the field plate (16) comprises a first section (See An. Fig. 18 below, First Section of the Field Plate FP1) partially covering the gate structure (14), (See An. Fig. 18 below, showing the First Section of the Field Plate FP1 covering the gate structure 14)
a second section (See An. Fig. 18 below, Second Section of the Field Plate FP2) partially covering the second dielectric layer (152), (See An. Fig. 18 below, showing the Second Section of the Field Plate FP1 partially covering the first upper dielectric layer 152)
and a third section (See An. Fig. 18 below, Third Section of the Field Plate FP3) interconnecting the first section (See An. Fig. 18, FP1) and the second section (See An. Fig. 18, FP1), (See An. Fig. 18)
wherein a height of the first section (FP1) is different from the second section (FP2). (See An. Fig. 18, showing the First Section of the Field Plate FP1 above the Second Section of the Field Plate FP2)
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Regarding Claim 6, Bao further discloses (as shown in An. Fig. 18) wherein the field plate (16) further comprises a fourth section (See An. Fig. 18 below, Fourth Section of the Field Plate FP4) interconnecting the first section (FP1) and the source electrode (12), ([0128] Exemplarily, as shown in FIG. 13g, the field plate 16 includes a first extension 161 extending from the source 12 to the drain 13) (See An. Fig. 18, showing the Fourth Section of the Field Plate FP4 between the source 12 and the First Section of the Field Plate FP1)
wherein a height of the fourth section (FP4) is lower than the height of the second section (FP2). (See An. Fig. 18)
Regarding Claim 7, Bao further discloses (as shown in An. Fig. 18) wherein the field plate (16) comprises a second section (See An. Fig. 18 below, Second Section of the Field Plate FP2) partially covering the second dielectric layer (152) (See An. Fig. 18 below, showing the Second Section of the Field Plate FP1 partially covering the first upper dielectric layer 152)
and a third section (See An. Fig. 18 below, Third Section of the Field Plate FP3) between the second section (FP2) and the gate structure (14), (See An. Fig. 18, showing the Third Section of the Field Plate FP3 between the Second Section of the Field Plate FP2 and the gate structure 14)
wherein the third section (FP3) is connected to the second section (FP2), (See An. Fig. 18)
and a height of the second section (FP2) is higher than a height of the third section (FP3). (See An. Fig. 18)
Alternatively, Claim 4 can be rejected under 35 USC 102a(2) as anticipated
Claim(s) 4, 8-12 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Hwang et. al (US 2024/0274673 A1)
Regarding Claim 4, Hwang discloses (as shown in Fig. 1H) A semiconductor device ([0033] FIG. 1A to FIG. 1H are cross-sectional views of a manufacturing process of a HEMT device) comprising:
a channel layer ([0035] A channel layer 108) disposed on a substrate ([0035] substrate structure 100); ([0035] A channel layer 108 is formed on the substrate structure 100)
a barrier layer ([0046] barrier layer 110a) disposed on the channel layer (108); ([0047] By the above method, the barrier layer 110a may be formed on the channel layer 108)
a gate structure ([0037] A gate electrode 112) disposed on the barrier layer (110a); ([0047] the gate electrode 112 may be formed on the barrier layer 110a)
a first dielectric layer ([0047] dielectric layer 116a) conformally disposed on the barrier layer (110a) and the gate structure (112); ([0047] [The dielectric layer 116a is located on the barrier layer 110a. The dielectric layer 116a may cover the gate electrode 112)
a source electrode ([0055] The portion P1 of the source field plate 128b located on the second side S2 of the gate electrode 112 may be used as a source electrode) and a drain electrode ([0053] a drain electrode 128a) disposed at opposite sides of the gate structure (112) (See Fig. 1H, showing the portion P1 and the drain electrode 128a are on opposite sides of the gate electrode 112)
and penetrating the first dielectric layer (116a) to contact the barrier layer (110a); (See Fig. 1H)
a second dielectric layer ([0047] dielectric layer 120a) disposed on the first dielectric layer (116a), ([0047] The dielectric layer 120a is located on the dielectric layer 116a)
wherein the second dielectric layer (120a) is disposed between the gate structure (112) and the drain electrode (128a); (See Fig. 1H, showing the dielectric layer 120a between the gate electrode 112 and the drain electrode 128a)
and a field plate ([0050] source field plate 128b, and a source field plate 128c) disposed between the source electrode (P1) and the drain electrode (128a) and partially covering the second dielectric layer (120a). (See Fig. 1H, showing the source field plate 128c is between the source P1 and the drain 128a and on top of the dielectric layer 120a)
wherein the source electrode (P1), the drain electrode (128a), and the field plate (128b,c) are made of the same material. ([0050] Referring to FIG. 1H and FIG. 2, the conductive material layer 128 may be patterned to form a drain electrode 128a, a source field plate 128b, and a source field plate 128c)
Regarding Claim 8, Hwang further discloses (as shown in Fig. 1H) wherein the second dielectric layer (120a) and the gate structure (112) are spaced apart, (See Fig. 1H, showing the dielectric layer 120a is separated from the gate electrode 112 in the horizontal direction.)
and the second dielectric layer (120a) and the drain electrode (128a) are spaced apart; (See Fig. 1H, showing the dielectric layer 120a is separated from the drain electrode 128a in the horizontal direction.)
Regarding Claim 9, Hwang discloses (as shown in Fig. 1H) A semiconductor device ([0033] FIG. 1A to FIG. 1H are cross-sectional views of a manufacturing process of a HEMT device) comprising:
a channel layer ([0035] A channel layer 108) disposed on a substrate ([0035] substrate structure 100); ([0035] A channel layer 108 is formed on the substrate structure 100)
a barrier layer ([0046] barrier layer 110a) disposed on the channel layer (108); ([0047] By the above method, the barrier layer 110a may be formed on the channel layer 108)
a gate structure ([0037] A gate electrode 112) disposed on the barrier layer (110a); ([0047] the gate electrode 112 may be formed on the barrier layer 110a)
a first dielectric layer ([0047] dielectric layer 116a) conformally disposed on the barrier layer (110a) and the gate structure (112); ([0047] [The dielectric layer 116a is located on the barrier layer 110a. The dielectric layer 116a may cover the gate electrode 112)
a source electrode ([0055] The portion P1 of the source field plate 128b located on the second side S2 of the gate electrode 112 may be used as a source electrode) and a drain electrode ([0053] a drain electrode 128a) disposed at opposite sides of the gate structure (112) (See Fig. 1H, showing the portion P1 and the drain electrode 128a are on opposite sides of the gate electrode 112)
and penetrating the first dielectric layer (116a) to contact the barrier layer (110a); (See Fig. 1H)
a second dielectric layer ([0047] dielectric layer 120a) disposed on the first dielectric layer (116a), ([0047] The dielectric layer 120a is located on the dielectric layer 116a)
wherein the second dielectric layer (120a) is disposed between the gate structure (112) and the drain electrode (128a); (See Fig. 1H, showing the dielectric layer 120a between the gate electrode 112 and the drain electrode 128a)
an etch stop layer ([0047] etch stop layer 118a) disposed between the second dielectric layer (120a) and the first dielectric layer (116a), ([0047] The etch stop layer 118a is located between the dielectric layer 116a and the dielectric layer 120a.)
wherein the etch stop layer (118a) with the second dielectric layer (120a) thereon and the gate structure (112) are spaced apart, (See Fig. 1H showing the portion of the etch stop layer 118a with the dielectric layer 120a on it is separated from the gate electrode 112 in the horizontal direction.)
and the etch stop layer (118a) with the second dielectric layer (120a) thereon and the drain electrode (128a) are spaced apart; (See Fig. 1H)
and a field plate ([0050] source field plate 128b, and a source field plate 128c) disposed between the source electrode (P1) and the drain electrode (128a) and partially covering the second dielectric layer (120a). (See Fig. 1H, showing the source field plate 128c is between the source P1 and the drain 128a and on top of the dielectric layer 120a)
Claim interpretation Note: under BRI, the limitation “wherein the etch stop layer with the second dielectric layer thereon and the gate structure are spaced apart” only requires the portion of the etch stop layer with the second dielectric layer on it to be separated from the gate structure. Furthermore, since the limitation does not claim in any direction, the etch stop layer can be separated in the vertical direction from the gate structure by the first dielectric layer as in Hwang.
Similarly, the limitation “and the etch stop layer with the second dielectric layer thereon and the drain electrode are spaced apart” would only require the portion of the etch stop layer with the second dielectric layer on it to be separated from the drain electrode.
Regarding Claim 10, Hwang further discloses (as shown in Fig. 1H) wherein the source electrode (P1), the drain electrode (128a), and the field plate (128b,c) are made of the same material. ([0050] Referring to FIG. 1H and FIG. 2, the conductive material layer 128 may be patterned to form a drain electrode 128a, a source field plate 128b, and a source field plate 128c)
Regarding Claim 11, Hwang further discloses (as shown in Fig. 1H) wherein the gate structure comprises a doping layer ([0037] P-type gallium nitride layer 114) and a gate metal layer ([0037] A gate electrode 112) on the doping layer. ([0037] In some embodiments, a P-type gallium nitride layer 114 may be formed between the gate electrode 112 and the barrier material layer 110)
Regarding Claim 12, Hwang further discloses (as shown in Fig. 1H) wherein a material of the etch stop layer (118a) is different from a material of the first dielectric layer (116a) and the second dielectric layer (120a). ([0039] the material of the dielectric material layer 116 is, for example, silicon oxide or silicon nitride… [0040] the material of the etch stop material layer 118 is, for example, aluminum oxide (Al.sub.2O.sub.3) or aluminum nitride… [0041] the material of the dielectric material layer 120 is, for example, silicon oxide or silicon nitride.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhu et. al (US 2023/0197839 A1). Zu discloses (as shown in Fig. 4) an HEMT transistor with a field plate ([0048] a field plate according to embodiments herein (the field plate 450)) which extend over the gate structure ([0049] control electrode 430) and a first dielectric layer ([0048] a field plate dielectric 415) and a second dielectric ([0049] third dielectric material 444); and there is a space between the gate structure (430) and a portion of the second dielectric (444) where there is no second dielectric (144).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON JAMES GREAVING/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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