Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 20210091211 A1) hereinafter referred to as "Kang".
Regarding claim 1, Kang discloses a semiconductor device comprising: a well area (Fig. 2A, element 104; ¶: [0024]) in a substrate (Fig. 2A, element 100; ¶: [0024]), wherein the well area has a first conductivity-type (¶: [0024]); one or more impurity-implanted areas (Fig. 2A, element 106; ¶: [0024]) in the well area, wherein the one or more impurity-implanted areas have a second conductivity-type different from the first conductivity-type (Fig. 2A, element 104; ¶: [0024]), and the one or more impurity-implanted areas are arranged in a first direction, a first fin structure (Fig. 2A, element AFa; ¶: [0027]) on the one or more impurity-implanted areas, wherein the first fin structure has the second conductivity-type (Fig. 2A, element AFa; ¶: [0027]), and wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked (Fig. 2A, element 110, 112; ¶: [0027]); a first contact (Fig. 2A, element CTa; ¶: [0037, 0038]) on the first fin structure; a first epitaxial pattern (Fig. 2A, element 120; ¶: [0030]) on the well area, wherein the first epitaxial pattern has the first conductivity-type (¶: [0030]); and a second contact (Fig. 2A, element CTb; ¶: [0037, 0038]) on the first epitaxial pattern.
Regarding claim 3, Kang discloses the substrate having the second conductivity-type (Fig. 2A, element 100; ¶: [0024]), wherein one or more well areas are arranged along the first direction, and wherein each of the one or more impurity-implanted areas is disposed in each of the one or more well areas (Fig. 2A, element 106; ¶: [0024]).
Regarding claim 4, Kang discloses the plurality of one or more impurity-implanted areas being arranged along a second direction intersecting the first direction (Fig. 2A, element 102a; ¶: [0026, 0039]).
Regarding claim 5, Kang discloses the substrate having the second conductivity-type (Fig. 2A, element 100; ¶: [0024]), wherein one or more well areas and the impurity-implanted areas are arranged along the first direction and the second direction, and wherein each of the one or more impurity-implanted areas is disposed in each of the one or more well areas (Fig. 2A, element 106; ¶: [0024]).
Regarding claim 6, Kang discloses a second epitaxial pattern (Fig. 2A, element 122; ¶: [0031]) on the substrate, wherein the second epitaxial pattern has the second conductivity-type (Fig. 2A, element 122; ¶: [0031]); and a third contact (Fig. 2A, element CTc; ¶: [0037, 0038]) on the second epitaxial pattern, wherein the substrate has the second conductivity-type (Fig. 2A, element 100; ¶: [0024]).
Regarding claim 7, Kang discloses a plurality of gate structures (Fig. 2A, element GS; ¶: [0032]), wherein one of the plurality of gate structures is on each of a plurality of well areas (Fig. 2A, element GS; ¶: [0032]), wherein the gate structures extend in the first direction, and are arranged in a second direction intersecting the first direction (Fig. 2A, element GS; ¶: [0032, 0033]), wherein the first epitaxial pattern is disposed between adjacent ones of the gate structures (Fig. 2A, element 120; ¶: [0056]).
Regarding claim 8, Kang discloses a second fin structure (Fig. 2A, element 120; ¶: [0056]) on the well area, wherein the second fin structure includes a plurality of second semiconductor patterns (Fig. 2A, element 110b, 112b; ¶: [0028]), wherein the first epitaxial pattern is connected to the plurality of second semiconductor patterns (Fig. 2A, element 120; ¶: [0030]).
Regarding claim 9, Kang discloses the well area being in an entirety of the substrate (Fig. 2A, element 104; ¶: [0024]).
PNG
media_image1.png
536
829
media_image1.png
Greyscale
Regarding claim 10, Kang discloses a semiconductor device comprising: a well area (Fig. 2A, element 104; ¶: [0024]) in an entirety of the substrate, wherein the well area has a first conductivity-type (¶: [0024]); one or more impurity-implanted areas (Fig. 2A, element 106; ¶: [0024]) in the well area, wherein the one or more impurity-implanted areas has a second conductivity-type different from the first conductivity-type (¶: [0024]); a first fin structure (Fig. 2A, element AFa; ¶: [0027]) on at least one of the one or more impurity-implanted areas, wherein the first fin structure has the second conductivity-type (¶: [0029]); and an epitaxial pattern (Fig. 2A, element 120; ¶: [0030]) on the well area, wherein the epitaxial pattern has the first conductivity-type (Fig. 2A, element 120; ¶: [0030]).
Regarding claim 11, Kang discloses the one or more impurity-implanted areas being arranged along a first direction and extending in a second direction intersecting the first direction (Fig. 2A, element 102a; ¶: [0026, 0039]), and wherein the first fin structure is on each of the one or more impurity-implanted areas (Fig. 2A, element AFa; ¶: [0027]).
Regarding claim 12, Kang discloses the one or more impurity-implanted areas being arranged along a first direction and a second direction intersecting the first direction (Fig. 2A, element 102a; ¶: [0026, 0039]), and wherein the first fin structure is disposed on each of the one or more impurity-implanted areas (Fig. 2A, element AFa; ¶: [0027]).
Regarding claim 13, Kang discloses the first fin structure including first semiconductor patterns (Fig. 2A, element 112; ¶: [0027]) and first sacrificial patterns (Fig. 2A, element 110; ¶: [0027]) alternately stacked on the one or more impurity-implanted areas.
Regarding claim 14, Kang discloses a plurality of gate structures (Fig. 2A, element GS; ¶: [0032]) on the first fin structure, wherein the gate structures extend in a first direction (Fig. 2A, element GS; ¶: [0032, 0033]), and are arranged in a second direction intersecting the first direction (Fig. 2A, element GS; ¶: [0032, 0033]).
Regarding claim 15, Kang discloses a second fin structure (Fig. 2A, element AFb; ¶: [0028]) on the well area, wherein the second fin structure includes a plurality of second semiconductor patterns (Fig. 2A, element 112b; ¶: [0028]) spaced apart from the well area; and a plurality of gate structures (Fig. 2A, element GS; ¶: [0032]) on the well area, wherein the gate structures extend in a first direction (Fig. 2A, element GS; ¶: [0032, 0033]), and are arranged in a second direction intersecting the first direction (Fig. 2A, element GS; ¶: [0032, 0033]), wherein the epitaxial pattern is disposed between adjacent ones of the plurality of gate structures and is connected to the plurality of second semiconductor patterns (Fig. 2A, element 120; ¶: [0056]).
Regarding claim 16, Kang discloses the plurality of gate structures each including: a gate electrode (Fig. 2A, element GE; ¶: [0033]) on the well area and surrounding the plurality of second semiconductor patterns; and a gate spacer (Fig. 2A, element GSP; ¶: [0033]) on a side surface of the gate electrode.
Regarding claim 17, Kang discloses the gate structures further including an inner spacer (Fig. 2A, element GI; ¶: [0033]) on a portion of a side surface of the gate electrode, wherein the portion is disposed between the well area and the second semiconductor pattern adjacent to the well area, and between adjacent ones of the second semiconductor patterns.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Kim (US 20170170304 A1).
Regarding claim 2, Kang discloses the semiconductor device of claim 1. Kang does not teach a first-first metal line electrically connected to the first contact, wherein the first-first metal line extends in a second direction intersecting the first direction; a first-second metal line electrically connected to the second contact, wherein the first-second metal line extends in the second direction; a second-first metal line electrically connected to the first-first metal line, wherein the second-first metal line extends in the first direction; and a second-second metal line electrically connected to the first-second metal line, wherein the second-second metal line extends in the first direction.
Kim teaches a first-first metal line (Fig. 1, element 172; ¶: [0047]) electrically connected to the first contact, wherein the first-first metal line extends in a second direction intersecting the first direction; a first-second metal line (Fig. 1, element 172; ¶: [0047]) electrically connected to the second contact, wherein the first-second metal line extends in the second direction; a second-first metal line (Fig. 1, element 160; ¶: [0042]) electrically connected to the first-first metal line, wherein the second-first metal line extends in the first direction; and a second-second metal line (Fig. 1, element 162; ¶: [0042]) electrically connected to the first-second metal line, wherein the second-second metal line extends in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include metal lines in order to reduce the number of trapped electrons, improving electron mobility (¶: [0046]).
Regarding claim 18, Kang teaches a semiconductor device comprising: a well area (Fig. 2A, element 104; ¶: [0024]) in a substrate (Fig. 2A, element 100; ¶: [0024]) and having a first conductivity-type (¶: [0024]); one or more impurity-implanted areas (Fig. 2A, element 106; ¶: [0024]) in the well area, having a second conductivity-type different from the first conductivity-type (¶: [0024]), wherein the one or more impurity-implanted areas are arranged in a first direction; a first contact (Fig. 2A, element CTa; ¶: [0037, 0038]) on the one or more impurity-implanted area; a second contact (Fig. 2A, element CTb; ¶: [0037, 0038]) on the well area. Kang does not teach a first-first metal line electrically connected to the first contact and extending in a second direction intersecting the first direction; a first-second metal line electrically connected to the second contact and extending in the second direction; a second-first metal line electrically connected to the first-first metal line and extending in the first direction; and a second-second metal line electrically connected to the first-second metal line and extending in the first direction.
Kim teaches a first-first metal line (Fig. 1, element 172; ¶: [0047]) electrically connected to the first contact and extending in a second direction intersecting the first direction; a first-second metal line (Fig. 1, element 172; ¶: [0047]) electrically connected to the second contact and extending in the second direction; a second-first metal line (Fig. 1, element 160; ¶: [0042]) electrically connected to the first-first metal line and extending in the first direction; and a second-second (Fig. 1, element 162; ¶: [0042]) metal line electrically connected to the first-second metal line and extending in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include metal lines in order to reduce the number of trapped electrons, improving electron mobility (¶: [0046]).
Regarding claim 19, Kang in view of Kim teaches the semiconductor device of claim 18 while Kang further discloses a third contact (Fig. 2A, element CTc; ¶: [0037, 0038]) on the substrate where the substrate has the second conductivity-type (Fig. 2A, element 100; ¶: [0024]). Kang however, does not disclose a first-third metal line electrically connected to the third contact and extending in the second direction; and a second-third metal line connected to the first-third metal line and extending in the first direction.
Kim discloses a first-third metal line (Fig. 1, element 172; ¶: [0047]) electrically connected to the third contact and extending in the second direction; and a second-third metal line (Fig. 1, element 164; ¶: [0042]) connected to the first-third metal line and extending in the first direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date to include metal lines in order to reduce the number of trapped electrons, improving electron mobility (¶: [0046]).
Regarding claim 20, Kang teaches the semiconductor device of claim 18 and further teaches a first fin structure (Fig. 2A, element AFa; ¶: [0027]) on each of the one or more impurity-implanted area, wherein the first fin structure has the second conductivity-type (¶: [0029]), wherein the first fin structure includes first semiconductor patterns (Fig. 2A, element 112; ¶: [0027]) and first sacrificial patterns (Fig. 2A, element 110; ¶: [0027]) alternately stacked; a second fin structure (Fig. 2A, element AFb; ¶: [0028]) on the well area, wherein the second fin structure has the first conductivity-type (Fig. 2A, element AFb; ¶: [0100]), and wherein the second fin structure includes second semiconductor patterns (Fig. 2A, element 112b; ¶: [0028]) and second sacrificial patterns (Fig. 2A, element 110b; ¶: [0028]) alternately stacked, wherein the first contact is connected to the first fin structure (Fig. 2A, element CTa; ¶: [0037, 0038]), and wherein the second contact is connected to the second fin structure (Fig. 2A, element CTb; ¶: [0037, 0038]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IHSAN HAWKINS whose telephone number is (571)272-8594. The examiner can normally be reached Mon-Thu 7:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571)272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/I.H./ Examiner, Art Unit 2899
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights