DETAILED ACTION
1. This Office action is in response to the amendment filed on 02/17/2026
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1 - 3, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2012/0319669 A1 in view of US Patent No. 9,444,343 B1; (hereinafter Chen et al and Barnette et al). Chen et al cited in previous office action dated 12/22/2025.
Regarding claim 1, Chen et al [e.g., Figs. 2 - 4] discloses an operation method of a voltage converter [e.g., operation of buck-boost converter 30], the voltage converter comprising a first switch [e.g., SW1], a second switch [e.g., SW2], a third switch [e.g., SW3], and a fourth switch [e.g., SW4], the first switch coupled between an input of the voltage converter and a first node [e.g., SW1 coupled between input of power converter 30 and node shared with SW2 and first terminal of inductor L], the second switch coupled between the first node and a reference voltage [e.g., SW2 coupled between node shared with SW1 and inductor L and node shared with ground], the third switch coupled between the reference voltage and a second node [e.g., SW3 coupled between node shared with ground and node shared with SW4 and inductor L], the fourth switch coupled between an output of the voltage converter and the second node [e.g., SW4 coupled between node shared with Vout and node shared with SW3 and inductor L], and the operation method comprising: determining the voltage converter to operate in a buck mode [e.g., p. 0028 recites "When a voltage ratio, which is determined by the input voltage Vin, the output voltage Vout, and the load current lload, between the two terminals of the inductor L is smaller than a first threshold value, the power converter 30 operates in a first mode, and FIG. 3 is a waveform diagram thereof. FIG. 4 is a diagram showing an inductor current IL and a switching sequence of the power converter 30 operating in the first mode which is a pure buck mode in this embodiment"] that includes a first phase [e.g., period tAD1 within first period Ts], a second phase [e.g., period tBD1 following period tAD1 within the first period Ts], and a third phase [e.g., tAD1 during period between Ts and 2Ts]; when controlling the voltage converter to operate in the first phase [e.g., period tAD1 within first period Ts], turning on the first switch and the fourth switch and turning off the second switch and the third switch [e.g., p. 0028 recites "During a time period from time t1 to time t2, the control signals VA, VB, VC and VD are low, as shown by waveforms 60, 62, 64 and 66 respectively, and since the switches SW1, SW4 are PMOSes and the switches SW2, SW3 are NMOSes, the switches SW1, SW4 are turned on and the switches SW2, SW3 are turned off. This time period from time t1 to time t2 is defined as tAD1, during which the power supply Vin charges the inductor L and thus the inductor current IL increases, as shown in FIG. 4"]; when controlling the voltage converter to operate in the second phase successively after the first phase [e.g., tBD1 following tAD1], turning on the second switch and the fourth switch [e.g., turns ON switches SW2 and SW4] and turning off the first switch and the third switch [e.g., turns OFF switches SW1 and SW3 p. 0028 recites "During a subsequent time period from time t2 to time t3, the control signals VA, VB are high and the control signals VC, VD remain low. Consequently, the switches SW2, SW4 are turned on and the switches SW1, SW3 are turned off. This time period from time t2 to time t3 is defined as tBD1, during which the inductor L discharges and the inductor current IL decreases"]; and when controlling the voltage converter to operate in the third phase successively after the second phase [e.g., tAD1 during period between Ts and 2Ts (repeating cycle)], turning on the first switch and the fourth switch and turning off the second switch and the third switch [e.g., p. 0028 recites "During a time period from time t1 to time t2, the control signals VA, VB, VC and VD are low, as shown by waveforms 60, 62, 64 and 66 respectively, and since the switches SW1, SW4 are PMOSes and the switches SW2, SW3 are NMOSes, the switches SW1, SW4 are turned on and the switches SW2, SW3 are turned off. This time period from time t1 to time t2 is defined as tAD1, during which the power supply Vin charges the inductor L and thus the inductor current IL increases, as shown in FIG. 4"], wherein the first node is coupled to the second node through an inductor [e.g., first node (node shared between SW1 and SW2) coupled to second node (node shared between SW3 and SW4) through inductor L], and the input of the voltage converter receives an input voltage and the output of the voltage converter generates an output voltage and an output current [e.g., Vin received by the input of power converter 30 to generate Vout and Iload].
Chen et al does not disclose wherein a frequency is generated based on a current relationship between the inductor current and the output current and the first switch, the second switch, the third switch, and the fourth switch are switched based on the frequency.
Barnette et al [e.g., Figs. 1 - 6] teaches a frequency is generated based on a current relationship between the inductor current and the output current [e.g., switching frequency generated based on relationship between change in inductance due to the current flowing in the inductor and the rate of change in the output current, col. 4 - 5 recites “The system controller 12 measures a change in the inductance of the first output inductor 32 resulting from the first output inductor reaching current saturation and measuring a rate of change in the output current of the first output inductor. The system controller 12 controls the switching frequency as a function of the measured change in the inductance and the measured rate of change in the output current in order to prevent an amount of current through the first high-side field-effect transistor 23 from exceeding a maximum operating current setpoint for the first high-side field-effect transistor.”] and the first switch, the second switch, the third switch, and the fourth switch are switched based on the frequency [e.g., switches 21, 22 , 41 and 42 controlled by switching frequency, col 4 recites “cols. 4 - 5 recites “The system controller is in communication with each of the control blocks to control the switching frequency of each field-effect transistor. Specifically, the system controller 12 will alternately (or asynchronously) turn on the first high-side field-effect transistor 23 and the first low-side field-effect transistor 24 at a switching frequency, wherein only one of the first high-side field-effect transistor and the first low-side field-effect transistor are turned on at any point in time.].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al with wherein a frequency is generated based on a current relationship between the inductor current and the output current [e.g., ] and the first switch, the second switch, the third switch, and the fourth switch are switched based on the frequency as suggested by Barnette et al to prevent an amount of current through the first high-side field-effect transistor from exceeding a maximum operating current setpoint for the first high-side field-effect transistor.
Regarding claim 2, Chen et al [e.g., Figs. 2, 9 and 10] discloses determining the voltage converter to operate in a boost mode [e.g., p. 0030 recites "When the voltage ratio between the two terminals of the inductor L, as determined by the input voltage Vin, the output voltage Vout, and the load current lload, is greater than the second threshold value, the power converter 30 operates in a fourth mode, and FIG. 9 is a waveform diagram thereof. FIG. 10 is a diagram showing the inductor current IL and a switching sequence of the power converter 30 operating in the fourth mode which is a pure boost mode"] that includes a fourth phase [e.g., tAD4 within first period Ts], a fifth phase [e.g., tAC3 during period between Ts and 2Ts], and a sixth phase [e.g., tAD4 during period between Ts and 2Ts]; when controlling the voltage converter to operate in the fourth phase [e.g., tAD4 within first period Ts], turning on the first switch and the fourth switch [e.g., turning ON switches SW1 and SW4] and turning off the second switch and the third switch [e.g., turning OFF switches SW2 and SW3, p. 0031 recites "During a subsequent time period from time t13 to time t14, all the control signals VA-VD are low and thus, the switches SW1-SW4 are turned on and the switches SW2, SW3 are turned off. This time period from time t13 to time t14 is defined as tAD4."]; when controlling the voltage converter to operate in the fifth phase successively after the fourth phase [e.g., tAC3 during period between Ts and 2Ts following tAD4], turning on the first switch and the third switch [e.g., turning ON switches SW1 and SW3] and turning off the second switch and the fourth switch [e.g., turning OFF switches SW2 and SW4, p. 0031 recites "During a time period from time t12 to time t13, the control signals VA, VB are low and the control signals VC, VD are high and hence, the switches SW1, SW3 are turned on and the switches SW2, SW4 are turned off. This time period from time t12 to time t13 is defined as tAC3."]; and when controlling the voltage converter to operate in the sixth phase successively after the fifth phase [e.g., tAD4 during period between Ts and 2Ts (repeating cycle)], turning on the first switch and the fourth switch [e.g., turning ON switches SW1 and SW4] and turning off the second switch and the third switch [e.g., turning OFF switches SW2 and SW3, p. 0031 recites "During a subsequent time period from time t13 to time t14, all the control signals VA-VD are low and thus, the switches SW1-SW4 are turned on and the switches SW2, SW3 are turned off. This time period from time t13 to time t14 is defined as tAD4."].
Regarding claim 3, Chen et al [e.g., Figs. 2, 9 - 10] discloses wherein the third switch [e.g., SW3] and the fourth switch [e.g., SW4] are switched between an on state and an off state two times in the boost mode [e.g., (1) switch SW3 switches from OFF to ON while Switch SW4 switches from ON to OFF during tAC3, (2) switch SW3 switches from ON to OFF while Switch SW4 switches from OFF to ON during tAD4 period, p. 0031 recites "During a time period from time t12 to time t13, the control signals VA, VB are low and the control signals VC, VD are high and hence, the switches SW1, SW3 are turned on and the switches SW2, SW4 are turned off. This time period from time t12 to time t13 is defined as tAC3. During a subsequent time period from time t13 to time t14, all the control signals VA-VD are low and thus, the switches SW1-SW4 are turned on and the switches SW2, SW3 are turned off. This time period from time t13 to time t14 is defined as tAD4. In the fourth mode, both the switches SW3, SW4 have a switching period Ts, the inductor current IL has a period equal to Ts, and the boost duty ratio Kboost3 is equal to the duty ratio of the switch SW3"].
Regarding claim 9, Chen et al [e.g., Figs. 2 - 4] discloses wherein the first switch [e.g., SW1] and the second switch [e.g., SW2] are switched between an on state and an off state two times in the buck mode [e.g., (1) switch SW1 switches from OFF to ON while Switch SW2 switches from ON to OFF during tAD1, (2) switch SW1 switches from ON to OFF while Switch SW2 switches from OFF to ON during tBD1 period p. 0028 recites "During a time period from time t1 to time t2, the control signals VA, VB, VC and VD are low, as shown by waveforms 60, 62, 64 and 66 respectively, and since the switches SW1, SW4 are PMOSes and the switches SW2, SW3 are NMOSes, the switches SW1, SW4 are turned on and the switches SW2, SW3 are turned off. This time period from time t1 to time t2 is defined as tAD1, during which the power supply Vin charges the inductor L and thus the inductor current IL increases, as shown in FIG. 4. During a subsequent time period from time t2 to time t3, the control signals VA, VB are high and the control signals VC, VD remain low. Consequently, the switches SW2, SW4 are turned on and the switches SW1, SW3 are turned off. This time period from time t2 to time t3 is defined as tBD1, during which the inductor L discharges and the inductor current IL decreases. In the first mode, both the switches SW1 and SW2 have a switching period Ts, the inductor current IL has a period equal to Ts, and the buck duty ratio Kbuck1 is equal to the duty ratio of the switch SW1"].
7. Claim(s) 6 - 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al in view of Barnette et al and US Patent No. 7,495,419 B1; (hereinafter Chen et al, Barnette et al and Ju). Chen et al and Ju cited in previous office action dated 12/22/2025.
Regarding claim 6, Chen et al discloses the claimed invention except for wherein when the input voltage is greater than the output voltage, the voltage converter operates in the buck mode.
Ju [e.g., Fig. 1] teaches wherein when the input voltage is greater than the output voltage, the voltage converter operates in the buck mode [e.g., column 1 lines 26 - 28 recites "If the input voltage is significantly greater than the output voltage, the three-mode buck/boost regulator operates in buck mode"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al with wherein when the input voltage is greater than the output voltage, the voltage converter operates in the buck mode as suggested by Ju to regulate the voltage level as the input voltage becomes greater than the desired output voltage level.
Regarding claim 7, Chen et al [e.g., Figs. 2 - 4] discloses the claimed invention except for wherein when the input voltage is less than the output voltage, the voltage converter operates in the boost mode.
Ju [e.g., Fig. 1] teaches wherein when the input voltage is less than the output voltage, the voltage converter operates in the boost mode [e.g., column 1 lines 28 - 30 recites "If the input voltage is significantly less than the output voltage, the three-mode buck/boost regulator operates in boost mode."].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al with wherein when the input voltage is less than the output voltage, the voltage converter operates in the boost mode as suggested by Ju to regulate the voltage level as the input voltage becomes less than the desired output voltage level.
Regarding claim 8, Chen et al discloses the claimed invention except for wherein when the input voltage is equal to the output voltage, the voltage converter alternately operates in the boost mode and the buck mode.
Ju [e.g., Fig. 1] teaches wherein when the input voltage is equal to the output voltage, the voltage converter alternately operates in the boost mode and the buck mode [e.g., column 1 lines 30 - 34 recites “If the input voltage and the output voltage are relatively close to each other, it operates in buck/boost mode. In a typical buck/boost topology, in buck/boost mode the boost switches and the buck switches are switching during the same cycle"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al with wherein when the input voltage is equal to the output voltage, the voltage converter alternately operates in the boost mode and the buck mode as suggested by Ju to regulate the voltage level as the input voltage becomes equal than the desired output voltage level.
8. Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al in view of Barnette et al and US Pub. No. 2019/0305666 A1; (hereinafter Chen et al, Barnette et al and Yang et al). Chen et al and Yang et al cited in previous office action dated 12/22/2025.
Regarding claim 10, Chen et al discloses the claimed invention except for the first switch, the second switch, the third switch, and the fourth switch are switched in a pulse-frequency modulation (PFM) mode.
Yang et al teaches the first switch, the second switch, the third switch, and the fourth switch are switched in a pulse-frequency modulation (PFM) mode [e.g., p. 0011 recites "In some implementations, the four-switch BUCKBOOST converter can automatically transition from a pulse-width modulation (PWM) to a pulse- frequency modulation (PFM) with the COT control. As a result, the four-switch BUCKBOOST converter does not require a slope compensation that is required for a PCM control, and, thus, greatly simplifies control circuit and current consumption."].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al with the first switch, the second switch, the third switch, and the fourth switch are switched in a pulse-frequency modulation (PFM) mode as suggested by Yang et al to simplify controls and current consumption.
Examiner’s Note
9. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
10. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
11. Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
12. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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