DETAILED ACTION
1. This Office action is in response to the amendment filed on 03/18/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
4. Claim 1 is objected to because of the following informalities:
Claim 1 line 2 recites “the polarity”. However, it appears that it should recite “a polarity”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1 - 10, 12 - 17 and 19 - 20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2014/0111168 A1; (hereinafter Chen et al), cited in previous Office Action date 12/29/2025.
Regarding claim 1, Chen et al [e.g., Figs. 2 - 4 and 7] discloses an apparatus [e.g., power converter 200], comprising: a polarity detection circuit [e.g., integration controller 213 (comparator CMP)] to identify the polarity of a phase node of a DC-DC converter [e.g., identifies polarity when voltage VSW is lower than voltage VREF (0 V) or voltage VSW is higher than voltage VREF (0 V) and generates signal S4, p. 0024 recites "The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late,…”, “Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early,…."]; and an adaptive diode emulation mode (DEM) offset circuit [e.g., rest of zero current detection circuit 210] to: detect a first early termination or a first late termination of an on time of a low-side gate drive of the DC-DC converter based on the identified polarity of the phase node [e.g., detects either early or late turn off moment of down bridge transistor 102, p. 0024 recites “The integration controller 213 determines if the current on the inductor 104 is zero when the down bridge transistor 102 is turned off by the zero current comparator 215 to know if the moment the transistor 102 being turned off is too early/late,…."]; output an offset voltage [e.g., voltage Vx] to selectively terminate on time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive [e.g., voltage Vx used to advance or delay the switching of down transistor 102, p. 0024 recites “The zero current comparator 215 outputs the signal S3 to turn off the down bridge transistor through the logic circuit 211 when detecting the current on the inductor 104 being zero. In other words, the zero current comparator 215 compares voltage on its positive input end and the voltage VX on its negative input end, and when the voltage on its positive input end is lower than the voltage VX on its negative input end, the zero current comparator 215 outputs the signal S3 with a low level and turns off the down bridge transistor 102 through the logic circuit 211."], a value of the offset voltage based on a polarity of the phase node of the DC-DC converter [e.g., value of voltage Vx corresponds to comparison between voltage VSW and voltage VREF(0V), p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off."]; and increase the offset voltage incrementally until the polarity of the phase node reverses [e.g., Examiner note: for examination purposes, the examiner will interpret the term “incrementally” in its broadest sense to refer as “doing something in a series of small, regular additions, amounts, or stages, rather than all at once.” As recited in p. 0026 “When the signal S4 is logic 1, within the transient period TP, the integrator 212 integrate positively, which means the charge/discharge module 2122 charges the capacitor CX by the constant current source I1 through the transistor Q1 to increase the voltage VX. When the signal S4 is logic 0, within the transient period TP, the integrator 212 integrate negatively, which means the charge/discharge module 2122 discharges the capacitor by the constant current source I2 through the transistor Q2 to decrease the voltage VX.…” As result, when the capacitor begins to charge as a result of CMP 213 operating, it will “incrementally” raise the voltage of Vx as a result of periodic signal S4 to compensate for early/late turn off of down bridge transistor 102]; wherein the second early termination occurs after the first early termination [e.g., second early termination occurs after the first early termination, p. 0024 recites "Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.."] and the second late termination occurs after the first late termination [e.g., second late termination occurs after the first early termination, p. 0024 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off."] .
Regarding claim 2, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein the adaptive DEM offset circuit [e.g., rest of zero current detection circuit 210] is to dynamically adjust the offset voltage based on the polarity of the phase node converter [e.g., increases/decreases value of voltage Vx corresponding to the comparison between voltage VSW and voltage VREF(0V), p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off."].
Regarding claim 3, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein the adaptive DEM offset circuit [e.g., rest of zero current detection circuit 210] is to repeatedly adjust the offset voltage in increments until the polarity of the phase node reverses [e.g., integrator 212 continuously adjust Vx to increase/decrease depending on node SW according to integration controller 213, p. 0024 “The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 4, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein the adaptive DEM offset circuit [e.g., rest of zero current detection circuit 210] is to receive a polarity of a phase node of a DC-DC converter [e.g., identifies polarity when voltage VSW is lower than voltage VREF (0 V) or voltage VSW is higher than voltage VREF (0 V) and generates signal S4, p. 0026 recites “Thus, when the voltage VSW is higher than 0 volt, the signal S4 of the comparator CMP is logic 1, which means the down bridge transistor 102 is turned off too early and the voltage VX is to be increased; when the voltage VSW is lower than 0 volt, the signal S4 of the comparator CMP is logic 0, which means the down bridge transistor 102 is turned off too late and the voltage VX is to be decreased."].
Regarding claim 5, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein the adaptive DEM offset circuit is to detect the first early termination through detection of a voltage of the phase node being pulled below ground [e.g., establishes advanced moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(0V), p. 0018 recites “As shown in FIG. 4, if the down bridge transistor 102 is turned off too late, which means the current on the inductor has been decreased to be negative, the current on the inductor flows to the ground through the body diode of the transistor 102, and the inductor voltage VSW will be decreased to -VD, e.g. 0.7 volt.”. It continues on p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off."].
Regarding claim 6, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein the adaptive DEM offset circuit is to detect the first late termination through detection of a voltage of the phase node being pulled above the input voltage [e.g., establishes delayed moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(0V), p. 0018 recites "As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)", It continues on p. 0024 recites "Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.,…"].
Regarding claim 7, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the offset voltage [e.g., voltage Vx] is approximately zero when a current through the DC-DC converter is greater than zero [e.g., Vx pulled to ground when charge/discharge module 2122 discharges the capacitor Cx via transistor Q2 when voltage VSW is higher than 0V (current in inductor not decreased to zero), p. 0024 recites “More particularly, in the integrator 212, the logic circuit 2121 controls the charge/discharge module 2122 to charge/discharge the capacitor CX in the transient period TP according to the signal S4. If the integration controller 213 indicates to integrate negatively, the constant current source I2 of the charge/discharge module 2122 discharges the capacitor CX through the transistor Q2 to lower the voltage VX; ….”. Additionally, p.0018 recites “As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero,…”].
Regarding claim 8, Chen et al [e.g., Figs. 2 - 4 and 9] discloses an apparatus [e.g., synchronous switching power converter 200], comprising: a DC-DC converter including a low-side gate drive [e.g., down bridge transistor 102 with logic circuit 211 and Transient state adjusting circuit 214] and a phase node [e.g., node SW]; a polarity detection circuit [e.g., integration controller 213 (comparator CMP)] to identify a polarity of the phase node [e.g., identifies polarity when voltage VSW is lower than voltage VREF (0 V) or voltage VSW is higher than voltage VREF (0 V) and generates signal S4, p. 0024 recites " The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late,…”, “Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early,…."]; an adaptive diode emulation mode (DEM) offset circuit [e.g., rest of zero current detection circuit 210] to: receive the identified polarity of the phase node from the polarity detection circuit [e.g., receives signal S4 from CMP 213, p. 0026 recites “Thus, when the voltage VSW is higher than 0 volt, the signal S4 of the comparator CMP is logic 1, which means the down bridge transistor 102 is turned off too early and the voltage VX is to be increased; when the voltage VSW is lower than 0 volt, the signal S4 of the comparator CMP is logic 0, which means the down bridge transistor 102 is turned off too late and the voltage VX is to be decreased.."]; detect a first early termination or a first late termination of an on time of the low- side gate drive based on the identified polarity of the phase node [e.g., detects either early or late turn off moment of down bridge transistor 102, p. 0027 recites “The integration controller 213 determines if the current on the inductor 104 is zero when the down bridge transistor 102 is turned off by the zero current comparator 215 to know if the moment the transistor 102 being turned off is too early/late,…."]; output an offset voltage [e.g., voltage Vx], a value of the offset voltage based on the polarity of the phase node [e.g., value of voltage Vx corresponds to comparison between voltage VSW and voltage VREF(0V), p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.."]; and increase the offset voltage incrementally until the polarity of the phase node reverses [e.g., Examiner note: for examination purposes, the examiner will interpret the term “incrementally” in its broadest sense to refer as “doing something in a series of small, regular additions, amounts, or stages, rather than all at once.” As recited in p. 0026 “When the signal S4 is logic 1, within the transient period TP, the integrator 212 integrate positively, which means the charge/discharge module 2122 charges the capacitor CX by the constant current source I1 through the transistor Q1 to increase the voltage VX. When the signal S4 is logic 0, within the transient period TP, the integrator 212 integrate negatively, which means the charge/discharge module 2122 discharges the capacitor by the constant current source I2 through the transistor Q2 to decrease the voltage VX.…” As result, when the capacitor begins to charge as a result of CMP 213 operating, it will “incrementally” raise the voltage of Vx as a result of periodic signal S4 to compensate for early/late turn off of down bridge transistor 102]; a diode emulation mode (DEM) circuit to: receive the offset voltage [e.g., receives Vx via comparator 215]; and selectively terminate the on time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive [e.g., advances or delays the switching of down transistor 102, p. 0027 recites “The zero current comparator 215 can accurately determine the moment the current on the inductor being zero by the adjustment of the integrator 212 and accurately turn off the down bridge transistor 102, and in this way, the conduction loss and the switching loss can be avoided."].
Regarding claim 9, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to dynamically adjust the offset voltage based on the polarity of the phase node [e.g., increases/decreases value of voltage Vx corresponding to the comparison between voltage VSW and voltage VREF(0V), p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.."].
Regarding claim 10, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to repeatedly adjust the offset voltage in increments until the polarity of the phase node reverses [e.g., integrator 212 continuously adjust Vx to increase/decrease depending on node SW according to integration controller 213, p. 0024 “The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 12, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to detect the first early termination through detection of a voltage of the phase node being pulled below ground [e.g., establishes advanced moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(0V), p. 0018 recites “As shown in FIG. 4, if the down bridge transistor 102 is turned off too late, which means the current on the inductor has been decreased to be negative, the current on the inductor flows to the ground through the body diode of the transistor 102, and the inductor voltage VSW will be decreased to -VD, e.g. 0.7 volt.”. It continues on p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off."].
Regarding claim 13, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein the adaptive DEM offset circuit is to detect the first late termination through detection of a voltage of the phase node being pulled above the input voltage [e.g., establishes delayed moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(0V), p. 0018 recites "As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)", It continues on p. 0024 recites "Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.,…"].
Regarding claim 14, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the offset voltage is approximately zero when a current through the DC-DC converter is greater than zero [e.g., Vx pulled to ground when charge/discharge module 2122 discharges the capacitor Cx via transistor Q2 when voltage VSW is higher than 0V (current in inductor not decreased to zero), p. 0024 recites “More particularly, in the integrator 212, the logic circuit 2121 controls the charge/discharge module 2122 to charge/discharge the capacitor CX in the transient period TP according to the signal S4. If the integration controller 213 indicates to integrate negatively, the constant current source I2 of the charge/discharge module 2122 discharges the capacitor CX through the transistor Q2 to lower the voltage VX;….”. Additionally, p.0018 recites “As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero,…”].
Regarding claim 15, Chen et al [e.g., Figs. 2 - 4 and 7] discloses a method, comprising: receiving a polarity of a phase node of a DC-DC converter [e.g., integration controller 213 identifies polarity when voltage VSW is lower than voltage VREF (0 V) or voltage VSW is higher than voltage VREF (0 V) and generates signal S4, p. 0024 recites " The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late,…”, “Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early,…."]; detecting a first early termination or a first late termination of an on time of a low-side gate drive of the DC-DC converter based on the received polarity of the phase node [e.g., detects either early or late turn off moment of down bridge transistor 102, p. 0027 recites “The integration controller 213 determines if the current on the inductor 104 is zero when the down bridge transistor 102 is turned off by the zero current comparator 215 to know if the moment the transistor 102 being turned off is too early/late,…."]; outputting an offset voltage [e.g., voltage Vx] to selectively terminate the on time of the low-side gate drive to mitigate a second early termination or a second late termination of the on time of the low-side gate drive [e.g., advances or delays the switching of down transistor 102, p. 0027 recites “The zero current comparator 215 can accurately determine the moment the current on the inductor being zero by the adjustment of the integrator 212 and accurately turn off the down bridge transistor 102, and in this way, the conduction loss and the switching loss can be avoided."]; and increasing the offset voltage incrementally until the polarity of the phase node reverses [e.g., Examiner note: for examination purposes, the examiner will interpret the term “incrementally” in its broadest sense to refer as “doing something in a series of small, regular additions, amounts, or stages, rather than all at once.” As recited in p. 0026 “When the signal S4 is logic 1, within the transient period TP, the integrator 212 integrate positively, which means the charge/discharge module 2122 charges the capacitor CX by the constant current source I1 through the transistor Q1 to increase the voltage VX. When the signal S4 is logic 0, within the transient period TP, the integrator 212 integrate negatively, which means the charge/discharge module 2122 discharges the capacitor by the constant current source I2 through the transistor Q2 to decrease the voltage VX.…” As result, when the capacitor begins to charge as a result of CMP 213 operating, it will “incrementally” raise the voltage of Vx as a result of periodic signal S4 to compensate for early/late turn off of down bridge transistor 102].
Regarding claim 16, Chen et al [e.g., Figs. 2 - 4 and 7] discloses comprising dynamically adjusting the offset voltage based on the polarity of the phase node after a previous termination of the low-side gate drive [e.g., increases/decreases value of voltage Vx corresponding to the comparison between voltage VSW and voltage VREF(0V), p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off."].
Regarding claim 17, Chen et al [e.g., Figs. 2 - 4 and 7] discloses comprising repeatedly adjusting the offset voltage in increments until the polarity of the phase node reverses [e.g., integrator 212 continuously adjust Vx to increase/decrease depending on node SW according to integration controller 213, p. 0024 “The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 19, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein detecting a first early termination includes detecting a voltage of the phase node being pulled below ground [e.g., establishes advanced moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(0V), p. 0018 recites “As shown in FIG. 4, if the down bridge transistor 102 is turned off too late, which means the current on the inductor has been decreased to be negative, the current on the inductor flows to the ground through the body diode of the transistor 102, and the inductor voltage VSW will be decreased to -VD, e.g. 0.7 volt.”. It continues on p. 0024 recites "When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, so as to advance the moment the down bridge transistor 102 being turned off."].
Regarding claim 20, Chen et al [e.g., Figs. 2 - 4 and 7] discloses wherein detecting a first late termination includes detecting a voltage of the phase node being pulled above the input voltage [e.g., establishes delayed moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(0V), p. 0018 recites "As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)", It continues on p. 0024 recites "Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, so as to delay the moment the down bridge transistor 102 being turned off.,…"].
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim(s) 11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al in view of US Pub. No 2009/0295350 A1; (hereinafter Chen et al and Yamada), Both cited in IDS.
Regarding claims 11 and 18, Chen et al discloses the claimed invention except for wherein the increments are of equal magnitude.
Yamada [e.g., Fig. 6] teaches wherein the increments are of equal magnitude [e.g., increments provided by up-down counter 630, p. 0048 recites "The up-down counter (630) counts up or down the value of the counter when an output Vsw' (620) of the RS latch (610) is on the logic H level or on the logic L level at the trailing edge of an output Vgn' (622) of the delay circuit (620). That is, when the output Vsw' (620) of the RS latch (610) is on the logic H level (when the Mn (110) is turned off late (corresponding to FIG. 2C and FIG. 4)) or on the logic L level (when the Mn (110) is turned off early (corresponding to FIG. 2B and FIG. 5)) at the trailing edge of the output Vgn' (622) of the delay circuit (620) of the reverse current detector circuit (600), the value of the up-down counter (630) is counted up or down, and the count value counted up or down is held"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al with wherein the increments are of equal magnitude as suggested by Yamada to adjust by increasing or decreasing an effective threshold level where no reverse current exists and, thus prevent the inductor current from flowing back.
Examiner’s Note
10. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
11. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
12. Applicant's arguments filed 03/18/2026 have been fully considered but they are not persuasive.
Applicant(s) argue(s):
The Examiner equates the integration controller 213 of Chen as the claimed "polarity detection circuit" and integrator 212 of Chen as the claimed "adaptive diode emulation mode (DEM) offset circuit." Office Action at 4-5. Chen discloses that integration controller 213 may be a comparator CMP that determines whether voltage Vsw is greater than or less than the reference voltage VREF. Chen at [0030]. Chen also discloses that "[w]hen the comparator CMP determines the voltage Vsw is lower than the reference voltage VREF, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor Cx [and] when the comparator CMP determines the voltage Vsw is higher than the reference voltage VREF, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor Cx." Id. In so far as the Applicant understands the Examiner's rejection, it appears that the Examiner equates voltage Vx to the claimed "offset voltage." While Chen discloses charging and discharging capacitor Cx to increase and decrease the voltage Vx, Chen does not disclose "an adaptive diode emulation mode (DEM) offset circuit to increase the offset voltage incrementally until the polarity of the phase node reverses," as recited in amended Claims 1 and 8. Similarly, Chen does not disclose "increasing the offset voltage incrementally until the polarity of the phase node reverses," as recited by amended Claim 15.
In response, as disclosed by Chen in paragraph 0022 “The integration controller 213 generates the signal S4 to control the direction of the integrator 212 (positive or negative) according to the voltage VSW at the node SW….., if the integration controller 213 determines the voltage VSW is negative, which means the down bridge transistor 102 is turned off too late, the integration controller 213 controls the integrator 212 to integrate positively to increase the basis of the zero current comparator 215 comparing zero current, which advances the moment the signal S3 outputs and the moment the down bridge transistor 102 is to be turned off. … In this way, the zero current detecting circuit 210, adjusts the basis of the zero current comparator 215 comparing zero current by monitoring voltage at the node SW, and therefore eliminates the offset voltage of the zero current comparator 215, which allows the zero current comparator 215 determines the moment of the current on the inductor 104 being zero accurately so as to control the down bridge transistor 102 to turn off so that the efficiency of the power converter 200 can be increased.” As mentioned above, when the voltage at node SW is negative as a result of the down bridge transistor turned off too late (which means the current on the inductor has been decreased to be negative) voltage Vx is increased to advance the moment the down bridge is turned off. As a result, integrator 212 is used to dynamically adjust (between positive and negative) voltage Vx corresponding to the voltage at node SW to allow for zero current switching to improve the efficiency of the power converter. Therefore, the rejection is maintained.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
- US Patent No. 8,278,889 B2 discloses a dynamic adjustment for controlling switching in an inductor based power supply.
14. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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