DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/02/2024 and 12/06/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "a positive direction" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, the examiner will interpret “a positive direction” as in direction towards the input source, as recited in p. 0029 “If the on time of low-side switch 212 is terminated late, the current direction through inductor 214 may reverse, causing the voltage at phase node 216 to rapidly increase to above VIN after termination of low-side switch 212, resulting in increased power dissipation”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 - 10, 12 - 17 and 19 - 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US Pub. No. 2014/0111168 A1; (hereinafter Chen et al). Cited in IDS.
Regarding claim 1, Chen et al [e.g., Figs. 2 - 4 and 9] discloses an apparatus [e.g., synchronous switching power converter 900], comprising: a polarity detection circuit [e.g., integration controller 213] to identify the polarity of a phase node of a DC-DC converter [e.g., identifies polarity of node SW when VSW is lower than VREF or VSW is higher than VREF, p. 0030 recites “The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late,…”. It continues “Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early,...”]; and an adaptive diode emulation mode (DEM) offset circuit [e.g., integrator 212] to: detect a first early termination or a first late termination of an on time of a low-side gate drive of the DC-DC converter based on the identified polarity of the phase node [e.g., detects both early termination and late termination, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off”]; and output an offset voltage [e.g., outputs Vx to delay unit 916] to selectively terminate on time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive [e.g., advances or delays the switching of 102, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off”], a value of the offset voltage based on a polarity of the phase node of the DC-DC converter [e.g., value of Vx corresponds to VSW, p. 0030 recites “If the integration controller 213 indicates to integrate negatively, the constant current source I2 of the charge/discharge module 2122 discharges the capacitor CX through the transistor Q2 to lower the voltage VX; if the integration controller 213 indicates to integrate positively, the constant current source I1 of the charge/discharge module 2122 charges the capacitor CX through the transistor Q1 to increase the voltage VX.”]; wherein the second early termination occurs after the first early termination [e.g., p. 0030 recites “Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”] and the second late termination occurs after the first late termination [e.g., p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off”].
Regarding claim 2, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to dynamically adjust the offset voltage based on the polarity of the phase node converter [e.g., integrator 212 adjust Vx based on node SW, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 3, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to repeatedly adjust the offset voltage in increments until the polarity of the phase node reverses [e.g., integrator 212 continuously adjusts voltage Vx to increase or decrease depending on node SW, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 4, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to receive a polarity of a phase node of a DC-DC converter [e.g., identifies polarity of node SW when VSW is lower than VREF or VSW is higher than VREF via signal S4, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 5, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to detect the first early termination through detection of a voltage of the phase node being pulled below ground [e.g., p. 0018 recites “As shown in FIG. 4, if the down bridge transistor 102 is turned off too late, which means the current on the inductor has been decreased to be negative, the current on the inductor flows to the ground through the body diode of the transistor 102, and the inductor voltage VSW will be decreased to -VD, e.g. 0.7 volt. Therefore, from FIG. 2, FIG. 3, and FIG. 4, it can be seen that the moment of turning off the down bridge transistor 102 can be determined to be too early or too late according to the inductor voltage VSW”].
Regarding claim 6, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to detect the first late termination through detection of a voltage of the phase node being pulled above the input voltage [e.g., p. 0018 recites “As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)”].
Regarding claim 7, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the offset voltage is approximately zero when a current through the DC-DC converter flows in a positive direction [e.g., balances Vx to 0 corresponding to node SW, p. 0030 recites “In detail, the zero current comparator 915 and the delay unit 916 operate according to the changes of the current on the inductor 104, to output the signal S3 to turn off the down bridge transistor through the logic circuit 211 when detecting the current on the inductor 104 being zero. In other words, the zero current comparator 915 compares voltage on its positive input end and the fixed comparing level VF on its negative input end, and when the voltage on its positive input end is lower than the fixed comparing level VF on its negative input end, the zero current comparator 915 outputs the comparing result CR with a low level and the delay unit 916 delays the comparing result CR with the low level to generate the signal S3 with a low level according to the voltage VX, to turns off the down bridge transistor 102 through the logic circuit 211.”].
Regarding claim 8, Chen et al [e.g., Figs. 2 - 4 and 9] discloses an apparatus [e.g., synchronous switching power converter 900], comprising: a DC-DC converter including a low-side gate drive [e.g., down bridge transistor 102] and a phase node [e.g., node SW]; a polarity detection circuit [e.g., integration controller 213 (CMP)] to identify a polarity of the phase node [e.g., identifies polarity of node SW when VSW is lower than VREF or VSW is higher than VREF, p. 0030 recites “The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late,…”. It continues “Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early,...”]; an adaptive diode emulation mode (DEM) offset circuit [e.g., integrator 212 and Delay unit 916] to: receive the identified polarity of the phase node from the polarity detection circuit [e.g., receives signal S4 from CMP 213, p. 0030 recites “More particularly, in the integrator 212, the logic circuit 2121 controls the charge/discharge module 2122 to charge/discharge the capacitor CX in the transient period TP according to the signal S4.”]; detect a first early termination or a first late termination of an on time of the low-side gate drive based on the identified polarity of the phase node [e.g., detects both early termination and late termination, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off”]; and output an offset voltage [e.g., outputs Vx to delay unit 916], a value of the offset voltage based on the polarity of the phase node [e.g., value Vx corresponds to VSW, p. 0030 recites “If the integration controller 213 indicates to integrate negatively, the constant current source I2 of the charge/discharge module 2122 discharges the capacitor CX through the transistor Q2 to lower the voltage VX; if the integration controller 213 indicates to integrate positively, the constant current source I1 of the charge/discharge module 2122 charges the capacitor CX through the transistor Q1 to increase the voltage VX”]; and a diode emulation mode (DEM) circuit to: receive the offset voltage [e.g., received Vx via Delay Unit 916]; and selectively terminate the on time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive [e.g., p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 9, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to dynamically adjust the offset voltage based on the polarity of the phase node [e.g., integrator 212 adjust Vx based on node SW, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 10, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to repeatedly adjust the offset voltage in increments until the polarity of the phase node reverses [e.g., integrator 212 continuously adjusts voltage Vx to increase or decrease depending on node SW, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 12, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to detect the first early termination through detection of a voltage of the phase node being pulled below ground [e.g., p. 0018 recites “As shown in FIG. 4, if the down bridge transistor 102 is turned off too late, which means the current on the inductor has been decreased to be negative, the current on the inductor flows to the ground through the body diode of the transistor 102, and the inductor voltage VSW will be decreased to -VD, e.g. 0.7 volt. Therefore, from FIG. 2, FIG. 3, and FIG. 4, it can be seen that the moment of turning off the down bridge transistor 102 can be determined to be too early or too late according to the inductor voltage VSW. Simply speaking, the moment of turning off the down bridge transistor 102 has to be within the duration that the inductor voltage VSW is zero, and thus the converting efficiency of the power converter will not be decreased”].
Regarding claim 13, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the adaptive DEM offset circuit is to detect the first late termination through detection of a voltage of the phase node being pulled above the input voltage [e.g., p. 0018 recites “As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)”].
Regarding claim 14, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein the offset voltage is approximately zero when a current through the DC-DC converter is greater than zero [e.g., balances Vx to 0 corresponding to node SW, p. 0030 recites “In detail, the zero current comparator 915 and the delay unit 916 operate according to the changes of the current on the inductor 104, to output the signal S3 to turn off the down bridge transistor through the logic circuit 211 when detecting the current on the inductor 104 being zero. In other words, the zero current comparator 915 compares voltage on its positive input end and the fixed comparing level VF on its negative input end, and when the voltage on its positive input end is lower than the fixed comparing level VF on its negative input end, the zero current comparator 915 outputs the comparing result CR with a low level and the delay unit 916 delays the comparing result CR with the low level to generate the signal S3 with a low level according to the voltage VX, to turns off the down bridge transistor 102 through the logic circuit 211.”].
Regarding claim 15, Chen et al [e.g., Figs. 2 - 4 and 9] discloses a method, comprising: receiving a polarity of a phase node of a DC-DC [e.g., identifies polarity of node SW when VSW is lower than VREF or VSW is higher than VREF, p. 0030 recites “The integration controller 213 can be a comparator CMP wherein the positive input end is coupled to the node SW for receiving the voltage VSW, the negative input end receives a reference voltage VREF, which is assumed to 0 volt, and the output end outputs the signal S4. When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late,…”. It continues “Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early,...”]; detecting a first early termination or a first late termination of an on time of a low-side gate drive of the DC-DC converter based on the received polarity of the phase node [e.g., detects both early termination and late termination, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off”]; and outputting an offset voltage [e.g., outputs Vx to delay unit 916] to selectively terminate the on time of the low-side gate drive to mitigate a second early termination or a second late termination of the on time of the low-side gate drive [e.g., p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off”], a value of the offset voltage based on a polarity of a phase node [e.g., p. 0030 recites “If the integration controller 213 indicates to integrate negatively, the constant current source I2 of the charge/discharge module 2122 discharges the capacitor CX through the transistor Q2 to lower the voltage VX; if the integration controller 213 indicates to integrate positively, the constant current source I1 of the charge/discharge module 2122 charges the capacitor CX through the transistor Q1 to increase the voltage VX.”].
Regarding claim 16, Chen et al [e.g., Figs. 2 - 4 and 9] discloses comprising dynamically adjusting the offset voltage based on the polarity of the phase node after a previous termination of the low-side gate drive [e.g., integrator 212 adjust Vx based on node SW, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 17, Chen et al [e.g., Figs. 2 - 4 and 9] discloses comprising repeatedly adjusting the offset voltage in increments until the polarity of the phase node reverses [e.g., integrator 212 continuously adjusts voltage Vx to increase or decrease depending on node SW, p. 0030 recites “When the comparator CMP determines the voltage VSW is lower than the reference voltage VREF, which means the down bridge transistor 102 is turned off too late, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to charge the capacitor CX to increase the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level less to generate the signal S3 with the low level earlier according to the increased voltage VX, to advance the moment the down bridge transistor 102 being turned off. Oppositely, when the comparator CMP determines the voltage VSW is higher than the reference voltage VREF, which means the down bridge transistor 102 is turned off too early, the signal S4 controls the charge/discharge module 2122 of the integrator 212 to discharge the capacitor CX to decrease the voltage VX within the transient period TP, such that the delay unit 916 delays the comparing result CR with the low level more to generate the signal S3 with the low level later according to the increased voltage VX, to delay the moment the down bridge transistor 102 being turned off.”].
Regarding claim 19, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein detecting a first early termination includes detecting a voltage of the phase node being pulled below ground [e.g., p. 0018 recites “As shown in FIG. 4, if the down bridge transistor 102 is turned off too late, which means the current on the inductor has been decreased to be negative, the current on the inductor flows to the ground through the body diode of the transistor 102, and the inductor voltage VSW will be decreased to -VD, e.g. 0.7 volt. Therefore, from FIG. 2, FIG. 3, and FIG. 4, it can be seen that the moment of turning off the down bridge transistor 102 can be determined to be too early or too late according to the inductor voltage VSW. Simply speaking, the moment of turning off the down bridge transistor 102 has to be within the duration that the inductor voltage VSW is zero, and thus the converting efficiency of the power converter will not be decreased”].
Regarding claim 20, Chen et al [e.g., Figs. 2 - 4 and 9] discloses wherein detecting a first late termination includes detecting a voltage of the phase node being pulled above the input voltage [e.g., p. 0018 recites “As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt).”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al in view of US Pub. No. 2009/0295350 A1; (hereinafter Chen et al and Yamada). Both cited in IDS.
Regarding claims 11 and 18, Chen et al discloses the claimed invention except for the wherein the increments are of equal magnitude.
Yamada [e.g., Fig. 6] teaches wherein the increments are of equal magnitude [e.g., increments provided by up-down counter 630, p. 0048 recites “The up-down counter (630) counts up or down the value of the counter when an output Vsw' (620) of the RS latch (610) is on the logic H level or on the logic L level at the trailing edge of an output Vgn' (622) of the delay circuit (620). That is, when the output Vsw' (620) of the RS latch (610) is on the logic H level (when the Mn (110) is turned off late (corresponding to FIG. 2C and FIG. 4)) or on the logic L level (when the Mn (110) is turned off early (corresponding to FIG. 2B and FIG. 5)) at the trailing edge of the output Vgn' (622) of the delay circuit (620) of the reverse current detector circuit (600), the value of the up-down counter (630) is counted up or down, and the count value counted up or down is held”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Chen et al with wherein the increments are of equal magnitude as suggested by Yamada to adjust by increasing or decreasing an effective threshold level where no reverse current exists and, thus prevent the inductor current from flowing back.
Examiner’s Note
11. Examiner has cited particular paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
12. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent No. 8,278,889 B2 discloses a dynamic adjustment for controlling switching in an inductor based power supply.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838