DETAILED ACTION
1. This Office action is in response to the amendment filed on 08/28/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
4. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/28/2026 has been entered.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1 - 5, 7 - 10, 12, 14 – 17 and 19 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Xu et al (US Pub. No. 2025/0105737 A1); (hereinafter Xu).
Regarding claim 1, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses an apparatus [e.g., power conversion circuit 100], comprising: a polarity detection circuit [e.g., polarity detected by switch control circuit 200] to identify a polarity of a phase node of a DC-DC converter [e.g., p. 0055 recites “This switch control circuit dynamically adjusts the timing of turning off the second power switch Q2 in real-time based on the polarity of the voltage at the common node P1 caused by the residual current flowing through the inductor L1 after the second power switch Q2 is turned off.”]; and an adaptive diode emulation mode (DEM) offset circuit [e.g., comparison branch 201 and a feedback branch 202] to: detect a first early termination or a first late termination of an on time of a low-side gate drive of the DC-DC converter [e.g., detects if Q2 is turned off to early or to late] based on the identified polarity of the phase node [e.g., detection based on polarity detected on node P1, p. 0058 recites “Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”]; output an offset voltage [e.g., first voltage V1] to selectively terminate the on time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive [e.g., first voltage V1 used to advance or delay the turn on of Q2, p. 0058 recites “If the first voltage V1 increases, it will cause the comparison branch 201 to delay the turning off the second power switch Q2. If the first voltage V1 decreases, it will cause the comparison branch 201 to advance the turning off of the second power switch Q2”], a value of the offset voltage based on the polarity of the phase node of the DC-DC converter [e.g., value of V1 is adjusted according to the polarity detected on node P1, p. 0060 recites “Then, after a delay of the first duration, the feedback branch 202 determines that the polarity of the voltage difference is positive. Based on this, it determines that, at the time of turning off the second power switch Q2, a residual current flowing through the inductor is less than zero. Consequently, it indicates that the second power switch Q2 is turned off late. In this case, it is necessary to decrease the first voltage V1, which will cause the comparison branch 201 to advance the output of the control signal for turning off the second power switch Q2 in the next cycle, thereby advancing the turning off the second power switch Q2.”]; and increase the offset voltage incrementally over a series of multiple on times of the low-side gate drive until the polarity of the phase node reverses [e.g., first voltage V1 adjusted over N cycles, p. 0075 recites “Furthermore, as shown in FIG. 4, an adjustable voltage source U13 is introduced at the non-inverting input of the first comparator U11. The first voltage V1 output by the adjustable voltage source U13 linearly increases with the increase of the calibration signal AD1 output by the voltage calibration unit U22, or the first voltage V1 linearly decreases with the decrease of the calibration signal AD1.”]; wherein the second early termination occurs after the first early termination and the second late termination occurs after the first late termination [e.g., second early/late termination occurring after first early/late termination, p. 0077 recites “Specifically, after each transition of the first comparison signal dU11 from low to high, the controller U12 causes the control signal tri to transition from low to high, while simultaneously initiate the generation of the signal PM1. The rising edge of the PM1 signal is delayed by the first duration Δt compared to the rising edge of the control signal tri (where the time between moments t41 and t42 is the first duration). In some implementations, the first duration can be set to 30 ns. Then, at the rising edge of the PM1 signal, the D flipflop U21 is used once again to check the output state of the first comparator U11. If, at this time, the first comparison signal dU11 is low, this indicates that the residual current IL1 flowing through the inductor L1 is greater than zero when the second power switch Q2 is turned off. Then, in the next cycle, the calibration signal AD1 should be increased to increase the input equivalent offset voltage of the first comparator U11 (achieved by increasing the first voltage V1 output from the adjustable voltage source U13). Consequently, the voltage at the common node P1 needs to be slightly higher to make the first comparison signal dU11 transition from low to high. As a result, in the cycle when the first comparison signal dU11 transitions from low to high, the residual current IL1 flowing through the inductor L1 is also smaller than that in the previous cycle and closer to zero.”].
Regarding claim 2, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to dynamically adjust the offset voltage based on the polarity of the phase node [e.g., first voltage V1 adjusted continuously according to polarity on node P1, p. 0058 recites “This feedback signal is then used to adjust the first voltage V1. Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”].
Regarding claim 3, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to repeatedly adjust the offset voltage in increments until the polarity of the phase node reverses [e.g., firs voltage V1 adjusted according to the polarity detected on node P1, p. 0058 recites “This feedback signal is then used to adjust the first voltage V1. Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”. It continues on p. 0082 recites “Furthermore, to expedite the calibration process described above in order to find a stable calibration signal AD1, the embodiments of this application propose an adaptive calibration algorithm implemented by the voltage calibration unit U22. Specifically, the voltage calibration unit U22 is used to perform the following method steps: first, configuring MSB of the digital correction code as 1 and all other bits as 0. The digital correction code comprises an N-bit binary number, and N is an integer greater than or equal to 1. Over N cycles, based on feedback signals, sequentially setting each bit of the digital correction code to the corresponding binary value from the most significant bit to the least significant bit, with each pulse corresponding to one cycle. After N cycles, linearly adjusting the digital correction code based on feedback signals. Adjusting the first voltage based on the digital correction code, where there is a positive correlation between the first voltage and the digital correction code.”].
Regarding claim 4, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to receive the polarity of the phase node of the DC-DC converter [e.g., polarity detected by switch control circuit 200, p. 0055 recites “This switch control circuit dynamically adjusts the timing of turning off the second power switch Q2 in real-time based on the polarity of the voltage at the common node P1 caused by the residual current flowing through the inductor L1 after the second power switch Q2 is turned off.]
Regarding claim 5, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to detect the first early termination [e.g., Q2 turned off to early] through detection of a voltage [e.g., difference between voltage detected on node P1 and first voltage V1] of the phase node being pulled below ground [e.g., comparison branch 201 determines that Q2 was turned off to early when voltage difference between the voltage at the common node P1 and the first voltage V1 is negative, p. 0059 recites “In this embodiment, assume that in the current cycle, the comparison branch 201 controls the turning off of the second power switch Q2. Then, after a delay of the first duration, the feedback branch 202 determines that the polarity of the voltage difference between the voltage at the common node P1 and the first voltage V1 is negative. Based on this, it determines that, at the time of turning off the second power switch Q2, a residual current IL1 flowing through the inductor L1 is greater than zero (considering the current flowing from the common node P1 to the output voltage bus Vout as a positive current), which in turn indicates that the second power switch Q2 is turned off early.”].
Regarding claim 7, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the offset voltage is approximately zero [e.g., -- refer to Fig. 6 --, first voltage V1 resulting in comparison signal dU11] when a current through the DC-DC converter is greater than zero [e.g., first voltage V1 decreases to disable comparator when current is not near zero crossing to reduce power consumption, p. 0077 recites “If, at this time, the first comparison signal dU11 is low, this indicates that the residual current IL1 flowing through the inductor L1 is greater than zero when the second power switch Q2 is turned off. Then, in the next cycle, the calibration signal AD1 should be increased to increase the input equivalent offset voltage of the first comparator U11 (achieved by increasing the first voltage V1 output from the adjustable voltage source U13).” It continued on p. 0080 “Typically, the enable signal of the first comparator U11 is high only during the conduction of either the first power switch Q1 or the second power switch Q2. After the control signal tri transitions to a high level, the enable signal of the first comparator U11 goes low to disable the first comparator U11, reducing static power consumption during the high-impedance state, which is especially effective when the high-impedance state is prolonged, such as under very light load conditions.”].
Regarding claim 8, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses an apparatus [e.g., power conversion circuit 100], comprising: a DC-DC converter [e.g., -- refer to Fig. 4 --] including a low-side gate drive [e.g., Q2] and a phase node [e.g., node P1]; a polarity detection circuit [e.g., polarity detected by switch control circuit 200] to identify a polarity of the phase node [e.g., p. 0055 recites “This switch control circuit dynamically adjusts the timing of turning off the second power switch Q2 in real-time based on the polarity of the voltage at the common node P1 caused by the residual current flowing through the inductor L1 after the second power switch Q2 is turned off.”]; an adaptive diode emulation mode (DEM) offset circuit to: receive the identified polarity of the phase node from the polarity detection circuit [e.g., comparison branch 201 and a feedback branch 202 detects if Q2 is turned off to early or to late based on polarity of node P1]; detect a first early termination or a first late termination of an on time of the low- side gate drive based on the identified polarity of the phase node [e.g., early or late turn off detection based on polarity detected on node P1, p. 0058 recites “Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”]; output an offset voltage [e.g., first voltage V1], a value of the offset voltage based on the polarity of the phase node [e.g., value of V1 is adjusted according to the polarity detected on node P1, p. 0060 recites “Then, after a delay of the first duration, the feedback branch 202 determines that the polarity of the voltage difference is positive. Based on this, it determines that, at the time of turning off the second power switch Q2, a residual current flowing through the inductor is less than zero. Consequently, it indicates that the second power switch Q2 is turned off late. In this case, it is necessary to decrease the first voltage V1, which will cause the comparison branch 201 to advance the output of the control signal for turning off the second power switch Q2 in the next cycle, thereby advancing the turning off the second power switch Q2.”]; and increase the offset voltage incrementally over a series of multiple on times of the low-side gate drive until the polarity of the phase node reverses [e.g., first voltage V1 linearly adjusted over N cycles, p. 0075 recites “Furthermore, as shown in FIG. 4, an adjustable voltage source U13 is introduced at the non-inverting input of the first comparator U11. The first voltage V1 output by the adjustable voltage source U13 linearly increases with the increase of the calibration signal AD1 output by the voltage calibration unit U22, or the first voltage V1 linearly decreases with the decrease of the calibration signal AD1.”]; a diode emulation mode (DEM) circuit to: receive the offset voltage [e.g., first voltage V1]; and selectively terminate the on time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive [e.g., first voltage V1 used to advance or delay the turn on of Q2, p. 0058 recites “If the first voltage V1 increases, it will cause the comparison branch 201 to delay the turning off the second power switch Q2. If the first voltage V1 decreases, it will cause the comparison branch 201 to advance the turning off of the second power switch Q2”].
Regarding claim 9, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to dynamically adjust the offset voltage based on the polarity of the phase node [e.g., first voltage V1 adjusted continuously according to polarity, p. 0058 recites “This feedback signal is then used to adjust the first voltage V1. Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”].
Regarding claim 10, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to repeatedly adjust the offset voltage in increments until the polarity of the phase node reverses [e.g., firs voltage V1 linearly adjusted according to the polarity detected on node P1, p. 0058 recites “This feedback signal is then used to adjust the first voltage V1. Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”. It continues on p. 0082 recites “Furthermore, to expedite the calibration process described above in order to find a stable calibration signal AD1, the embodiments of this application propose an adaptive calibration algorithm implemented by the voltage calibration unit U22. Specifically, the voltage calibration unit U22 is used to perform the following method steps: first, configuring MSB of the digital correction code as 1 and all other bits as 0. The digital correction code comprises an N-bit binary number, and N is an integer greater than or equal to 1. Over N cycles, based on feedback signals, sequentially setting each bit of the digital correction code to the corresponding binary value from the most significant bit to the least significant bit, with each pulse corresponding to one cycle. After N cycles, linearly adjusting the digital correction code based on feedback signals. Adjusting the first voltage based on the digital correction code, where there is a positive correlation between the first voltage and the digital correction code.”].
Regarding claim 12, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to detect the first early termination [e.g., Q2 turned off to early] through detection of a voltage of the phase node [e.g., difference between voltage detected on node P1 and first voltage V1] being pulled below ground [e.g., comparison branch 201 determines that Q2 was turned off to early when voltage difference between the voltage at the common node P1 and the first voltage V1 is negative, p. 0059 recites “In this embodiment, assume that in the current cycle, the comparison branch 201 controls the turning off of the second power switch Q2. Then, after a delay of the first duration, the feedback branch 202 determines that the polarity of the voltage difference between the voltage at the common node P1 and the first voltage V1 is negative. Based on this, it determines that, at the time of turning off the second power switch Q2, a residual current IL1 flowing through the inductor L1 is greater than zero (considering the current flowing from the common node P1 to the output voltage bus Vout as a positive current), which in turn indicates that the second power switch Q2 is turned off early.”].
Regarding claim 14, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the offset voltage is approximately zero [e.g., -- refer to Fig. 6 --, first voltage V1 resulting in comparison signal dU11] when a current through the DC-DC converter is greater than zero [e.g., first voltage V1 decreases to disable comparator when current is not near zero crossing to reduce power consumption, p. 0077 recites “If, at this time, the first comparison signal dU11 is low, this indicates that the residual current IL1 flowing through the inductor L1 is greater than zero when the second power switch Q2 is turned off. Then, in the next cycle, the calibration signal AD1 should be increased to increase the input equivalent offset voltage of the first comparator U11 (achieved by increasing the first voltage V1 output from the adjustable voltage source U13).” It continued on p. 0080 “Typically, the enable signal of the first comparator U11 is high only during the conduction of either the first power switch Q1 or the second power switch Q2. After the control signal tri transitions to a high level, the enable signal of the first comparator U11 goes low to disable the first comparator U11, reducing static power consumption during the high-impedance state, which is especially effective when the high-impedance state is prolonged, such as under very light load conditions.”].
Regarding claim 15, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses a method [e.g., method of controlling power conversion circuit 100], comprising: receiving a polarity of a phase node of a DC-DC converter [e.g., polarity detected by switch control circuit 200, p. 0055 recites “This switch control circuit dynamically adjusts the timing of turning off the second power switch Q2 in real-time based on the polarity of the voltage at the common node P1 caused by the residual current flowing through the inductor L1 after the second power switch Q2 is turned off.”]; detecting a first early termination or a first late termination of an on time of a low-side gate drive of the DC-DC converter [e.g., detects if Q2 is turned off to early or to late] based on the received polarity of the phase node [e.g., based on polarity detected on node P1, p. 0058 recites “Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”]; outputting an offset voltage [e.g., first voltage V1] to selectively terminate the on time of the low-side gate drive to mitigate a second early termination or a second late termination of the on time of the low-side gate drive [e.g., first voltage V1 used to advance or delay the turn on of Q2, p. 0058 recites “If the first voltage V1 increases, it will cause the comparison branch 201 to delay the turning off the second power switch Q2. If the first voltage V1 decreases, it will cause the comparison branch 201 to advance the turning off of the second power switch Q2”], a value of the offset voltage based on the polarity of the phase node [e.g., value of V1 is adjusted according to the polarity detected on node P1, p. 0060 recites “Then, after a delay of the first duration, the feedback branch 202 determines that the polarity of the voltage difference is positive. Based on this, it determines that, at the time of turning off the second power switch Q2, a residual current flowing through the inductor is less than zero. Consequently, it indicates that the second power switch Q2 is turned off late. In this case, it is necessary to decrease the first voltage V1, which will cause the comparison branch 201 to advance the output of the control signal for turning off the second power switch Q2 in the next cycle, thereby advancing the turning off the second power switch Q2.”]; and increasing the offset voltage incrementally over a series of multiple on times of the low- side gate drive until the polarity of the phase node reverses [e.g., first voltage V1 adjusted over N cycles, p. 0075 recites “Furthermore, as shown in FIG. 4, an adjustable voltage source U13 is introduced at the non-inverting input of the first comparator U11. The first voltage V1 output by the adjustable voltage source U13 linearly increases with the increase of the calibration signal AD1 output by the voltage calibration unit U22, or the first voltage V1 linearly decreases with the decrease of the calibration signal AD1.”].
Regarding claim 16, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses comprising dynamically adjusting the offset voltage based on the polarity of the phase node after a previous termination of the low-side gate drive [e.g., first voltage V1 adjusted continuously according to polarity, p. 0058 recites “This feedback signal is then used to adjust the first voltage V1. Specifically, if the polarity of the voltage difference is positive, the first voltage V1 is reduced to make the comparison branch 201 turn off the second power switch Q2 earlier. If the polarity of the voltage difference is negative, the first voltage V1 is increased to make the comparison branch 201 delay the turning off the second power switch Q2. The polarity of both the first voltage V1 and the voltage difference could be either positive or negative.”].
Regarding claim 17, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses comprising repeatedly adjusting the offset voltage in increments until the polarity of the phase node reverses [e.g., firs voltage V1 linearly adjusted according to the polarity detected on node P1, p. 0082 recites “Furthermore, to expedite the calibration process described above in order to find a stable calibration signal AD1, the embodiments of this application propose an adaptive calibration algorithm implemented by the voltage calibration unit U22. Specifically, the voltage calibration unit U22 is used to perform the following method steps: first, configuring MSB of the digital correction code as 1 and all other bits as 0. The digital correction code comprises an N-bit binary number, and N is an integer greater than or equal to 1. Over N cycles, based on feedback signals, sequentially setting each bit of the digital correction code to the corresponding binary value from the most significant bit to the least significant bit, with each pulse corresponding to one cycle. After N cycles, linearly adjusting the digital correction code based on feedback signals. Adjusting the first voltage based on the digital correction code, where there is a positive correlation between the first voltage and the digital correction code.”].
Regarding claim 19, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein detecting the first early termination [e.g., Q2 turned off to early] includes detecting a voltage of the phase node [e.g., difference between voltage detected on node P1 and first voltage V1] being pulled below ground [e.g., comparison branch 201 determines that Q2 was turned off to early when voltage difference between the voltage at the common node P1 and the first voltage V1 is negative, p. 0059 recites “In this embodiment, assume that in the current cycle, the comparison branch 201 controls the turning off of the second power switch Q2. Then, after a delay of the first duration, the feedback branch 202 determines that the polarity of the voltage difference between the voltage at the common node P1 and the first voltage V1 is negative. Based on this, it determines that, at the time of turning off the second power switch Q2, a residual current IL1 flowing through the inductor L1 is greater than zero (considering the current flowing from the common node P1 to the output voltage bus Vout as a positive current), which in turn indicates that the second power switch Q2 is turned off early.”].
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim(s) 6, 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al (US Pub. No. 2025/0105737 A1) in view of Chen et al (US Pub. No. 2014/0111168 A1); (hereinafter Xu and Chen).
Regarding claim 6, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to detect the first late termination through detection of a voltage of the phase node [e.g., polarity detected by switch control circuit 200 on node P1, p. 0027 recites “Consequently, it can be determined that the second power switch turns off late, and in such a case, reducing the first voltage is used to advance the turn-off of the second power switch.”].
Xu does not disclose detection of a voltage of the phase node being pulled above an input voltage.
Chen [e.g., Figs. 2 - 4 and 7] teaches the phase node being pulled above an input voltage [e.g., establishes delayed moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(OV), p. 0018 recites "As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Xu with detection of a voltage of the phase node being pulled above an input voltage as disclosed by Chen et al to detect when the voltage at the node is higher than the input voltage as a result of a later termination of the low-side switch causing current to flow back into the node.
Regarding claim 13, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein the adaptive DEM offset circuit is to detect the first late termination through detection of a voltage of the phase node [e.g., polarity detected by switch control circuit 200 on node P1, p. 0027 recites “Consequently, it can be determined that the second power switch turns off late, and in such a case, reducing the first voltage is used to advance the turn-off of the second power switch.”].
Xu does not disclose detection of a voltage of the phase node being pulled above an input voltage.
Chen et al [e.g., Figs. 2 - 4 and 7] teaches the phase node being pulled above an input voltage [e.g., establishes delayed moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(OV), p. 0018 recites "As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Xu with detection of a voltage of the phase node being pulled above an input voltage as disclosed by Chen et al to detect when the voltage at the node is higher than the input voltage as a result of a later termination of the low-side switch causing current to flow back into the node.
Regarding claim 20, Xu [e.g., Figs. 3 - 6 and 11 - 13] discloses wherein detecting the first late termination includes detecting a voltage of the phase node [e.g., polarity detected by switch control circuit 200 on node P1, p. 0027 recites “Consequently, it can be determined that the second power switch turns off late, and in such a case, reducing the first voltage is used to advance the turn-off of the second power switch.”].
Xu does not disclose detection of a voltage of the phase node being pulled above an input voltage.
Chen et al [e.g., Figs. 2 - 4 and 7] teaches detection of a voltage of the phase node being pulled above an input voltage [e.g., establishes delayed moment to turn off down bridge transistor 102 based on comparison of voltage VSW and voltage VREF(OV), p. 0018 recites "As shown in FIG. 2, if the down bridge transistor 102 is turned off too early, which means the current on the inductor has not been decreased to zero, the current on the inductor flows to the input power source through the body diode of the transistor 102, and the voltage VSW at the node SW (hereinafter, inductor voltage VSW) will be suddenly increased (VSW=VIN+VD, where VD is the forward voltage of the body diode of the up bridge transistor 101, e.g. 0.7 volt)"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Xu with detection of a voltage of the phase node being pulled above an input voltage as disclosed by Chen et al to detect when the voltage at the node is higher than the input voltage as a result of a later termination of the low-side switch causing current to flow back into the node.
9. Claim(s) 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al (US Pub. No. 2025/0105737 A1) in view of Yamada (US Pub. No 2009/0295350 A1); (hereinafter Xu and Yamada).
Regarding claims 11 and 18, Xu discloses the claimed invention except for wherein the increments are of equal magnitude.
Yamada [e.g., Fig. 6] teaches wherein the increments are of equal magnitude [e.g., increments provided by up-down counter 630, p. 0048 recites "The up-down counter (630) counts up or down the value of the counter when an output Vsw' (620) of the RS latch (610) is on the logic H level or on the logic L level at the trailing edge of an output Vgn' (622) of the delay circuit (620). That is, when the output Vsw' (620) of the RS latch (610) is on the logic H level (when the Mn (110) is turned off late (corresponding to FIG. 2C and FIG. 4)) or on the logic L level (when the Mn (110) is turned off early (corresponding to FIG. 2B and FIG. 5)) at the trailing edge of the output Vgn' (622) of the delay circuit (620) of the reverse current detector circuit (600), the value of the up-down counter (630) is counted up or down, and the count value counted up or down is held"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Xu with wherein the increments are of equal magnitude as suggested by Yamada to adjust by increasing or decreasing the input offset voltage so that the synchronous rectification device is s turned off at a point where the inductor current is more positive or more negative.
Examiner’s Note
10. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
11. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
12. Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/FRED E FINCH III/Primary Examiner, Art Unit 2838
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