DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 03 September 2026. Claims 1-20 are pending in this application; however, Claim 18 is withdrawn from consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, Modifications 1-1, 2-1, and 3-1 in the reply filed on 03 September 2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 9-10, 15 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Koike et. al (JP 2004273977 A).
Regarding Claim 1, Koike discloses (Figs. 34-35) A semiconductor device comprising:
a chip ([0021] semiconductor chip 10) having a first main surface on one side ([0013] main surface) (See An. Fig. 34, showing the semiconductor chip 10 having a main surface), a second main surface on the other side ([0013] back surface opposite to the main surface) (See An. Fig. 34, showing the semiconductor chip 10 having a bottom surface), and a side surface connecting the first main surface and the second main surface (See An. Fig. 34, showing the semiconductor chip 10 having a side surface connecting the main and bottom surfaces);
a main surface electrode ([0021] electrodes, that is, a source electrode 11 and a gate electrode 12) arranged on the first main surface; ([0021] a source electrode 11 and a gate electrode 12 are provided on the main surface of the semiconductor chip 10)
a terminal electrode ([0022] The source lead 4 and the gate lead 6) arranged on the main surface electrode (11,12); ([0024] The semiconductor device 1 has a structure in which the source electrode 11 and the gate electrode 12 of the semiconductor chip 10 are bump-connected to the back surface of the second portion 8 of the source lead 4 and the gate lead 6)
and a sealing insulator ([0077] A side resin portion 70) having a main surface covering portion that covers a periphery of the terminal electrode (4,6) on the first main surface (main surface) ([0077] The semiconductor device 1 of the sixth embodiment differs from the semiconductor device 1 of the first embodiment in that the outer surfaces of the first portions 7 (the first portions 7 of the source lead 4 and the gate lead 6) on both sides are made of an insulating resin)
such as to expose the terminal electrode (4,6), (See Fig. 34, showing the side resin 70 does not cover the top surface of the gate and source leads)
and a side surface covering portion ([0019] sealing portion 9) that covers the side surface such as to expose the second main surface (bottom surface). (See Fig. 34, showing the sealing portion 9 cover the side surface of the semiconductor chip 10 and exposing the bottom surface of the semiconductor chip 10)
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Regarding Claim 2, Koike further discloses (as shown in Figs. 34-35) wherein the terminal electrode (4,6) has a terminal surface (See An. Fig. 34, showing the terminal surface) and a terminal side wall (See An. Fig. 34, showing the terminal side wall),
and the main surface covering portion (70) exposes the terminal surface and covers the terminal side wall. (See An. Fig. 34)
Regarding Claim 3, Koike further discloses (as shown in Figs. 34-35) wherein the main surface covering portion (70) has an insulating main surface (See An. Fig. 34, insulating main surface) that forms a single flat surface with the terminal surface (An. Fig. 34, terminal surface). (See An. Fig. 34, showing the insulating main surface and terminal surface are coplanar)
Regarding Claim 4, Koike further discloses (as shown in Figs. 34-35) wherein the terminal electrode (4, 6) is thicker than the main surface electrode (11, 12), (See Fig. 34, showing the source lead 4 and gate lead 6 are attached above the source electrodes 11 and the gate electrodes 12, and extend below the source electrodes 11 and the gate electrodes 12)
and the main surface covering portion (70) is thicker than the main surface electrode (11, 12). (See Fig. 34, showing the side resin portion 70 is the same thickness as the source lead 4 and gate lead 6 which are thicker than the source electrodes 11 and the gate electrodes 12)
Regarding Claim 5, Koike further discloses (as shown in Figs. 34-35) wherein the terminal electrode (4, 6) is thicker than the chip (10), (See Fig. 34, showing the source lead 4 and gate lead 6 are attached above the source electrodes 11 and the gate electrodes 12 on top of the semiconductor chip 10, and extend to be coplanar with the bottom surface of the semiconductor chip 10)
and the main surface covering portion (70) is thicker than the chip (10). (See Fig. 34, showing the side resin portion 70 is the same thickness as the source lead 4 and gate lead 6 which are thicker than the semiconductor chip 10)
Regarding Claim 6, Koike further discloses (as shown in Figs. 34-35) wherein the side surface covering portion (9) exposes a whole region of the second main surface (bottom surface). (See An. Fig. 34, showing the sealing portion 9 does not extend to the bottom surface of the semiconductor chip 10)
Regarding Claim 7, Koike further discloses (as shown in Figs. 34-35) wherein the side surface covering portion (9) has an end surface that forms a single flat surface with the second main surface (bottom surface). (See An. Fig. 34, showing the sealing portion 9 is coplanar with the bottom surface of the semiconductor chip 10)
Regarding Claim 9, Koike further discloses (as shown in Figs. 34-35) a second main surface electrode ([0020] drain electrode 5) that covers the second main surface (bottom surface). ([0034] The surface opposite to the main surface is a drain electrode)
Regarding Claim 10, Koike further discloses (as shown in Figs. 34-35) a second main surface electrode ([0020] drain electrode 5) that covers a whole region of the second main surface (bottom surface). ([0034] The surface opposite to the main surface is a drain electrode)
Regarding Claim 15, Koike further discloses (as shown in Figs. 9, 34-35) wherein the sealing insulator includes a thermosetting resin. ([0035] The resin 32 is made of an insulating resin, and for example, an epoxy resin is used. After application of the resin, the resin is cured and cured to form a sealing portion 9)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Alternatively, Claim 1 can be rejected under 35 USC 103 as being obvious in view of Yamaji et. al (US 2020/0111733 A1) in view of Koike et. al (JP 2004273977 A).
Claim(s) 1, 8, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over in view of Yamaji et. al (US 2020/0111733 A1) and Koike et. al (JP 2004273977 A).
Regarding Claim 1, Yamaji discloses (as shown in Fig. 4) A semiconductor device comprising:
a chip ([0042] The chip main body 2) having a first main surface on one side ([0042] a first chip main surface 3 at one side), a second main surface on the other side, ([0042] a second chip main surface 4 at the other side) and a side surface connecting ([0042] chip side surfaces 5A, 5B, 5C, 5D) the first main surface (3) and the second main surface (); ([0042] The chip main body 2 includes a first chip main surface 3 at one side, a second chip main surface 4 at the other side and chip side surfaces 5A, 5B, 5C, 5D which connect the first chip main surface 3 and the second chip main surface 4.)
a main surface electrode arranged on the first main surface; ([0090] The chip main body 2 includes an internal electrode 39 which is formed on the main surface insulation layer 38)
a terminal electrode ([0051] The plurality of terminal electrodes 10 include a first terminal electrode 11 and a second terminal electrode 12) arranged on the main surface electrode (39) (See Fig. 4, showing the terminal electrode 10 on the internal electrode 39)
and a sealing insulator having a side surface covering portion that covers the side surface ([0067] The outer surface resin 21 includes a side surface covering portion 22. The side surface covering portion 22 covers the chip side surfaces 5A to 5D of the chip main body 2.)
However, Yamaji fails to disclose a sealing insulator having a main surface covering portion that covers a periphery of the terminal electrode on the first main surface such as to expose the terminal electrode, and a side surface covering portion that covers the side surface such as to expose the second main surface.
Koike discloses (as shown in Fig. 34-35) a terminal electrode ([0022] The source lead 4 and the gate lead 6) arranged on the main surface electrode (11,12); ([0024] The semiconductor device 1 has a structure in which the source electrode 11 and the gate electrode 12 of the semiconductor chip 10 are bump-connected to the back surface of the second portion 8 of the source lead 4 and the gate lead 6)
a sealing insulator ([0079] Actually, the side resin portion 70 and the coating layer 71 are formed simultaneously with the formation of the sealing portion 9, and the side resin portion 70 and the coating layer 71 are formed integrally with the sealing portion 9) having a main surface covering portion ([0077] A side resin portion 70) that covers a periphery of the terminal electrode (4,6) on the first main surface (main surface) ([0077] The semiconductor device 1 of the sixth embodiment differs from the semiconductor device 1 of the first embodiment in that the outer surfaces of the first portions 7 (the first portions 7 of the source lead 4 and the gate lead 6) on both sides are made of an insulating resin)
such as to expose the terminal electrode (4,6), (See Fig. 34, showing the side resin 70 does not cover the top surface of the gate and source leads)
and a side surface covering portion ([0019] sealing portion 9) that covers the side surface such as to expose the second main surface (bottom surface). (See Fig. 34, showing the sealing portion 9 cover the side surface of the semiconductor chip 10 and exposing the bottom surface of the semiconductor chip 10)
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Koike teaches that that the sealing member creates a flat side surface ([0028] The cut surface becomes a flat surface. The source lead 4 and the sealing portion 9 are exposed on the flat side surface forming the side g, and the source lead 4, the gate lead 6 and the sealing portion 9 are exposed on the flat side surface forming the side i (FIG. 1). reference).) Koike further teaches that the side resin portion 70 improves the moisture resistance of the semiconductor device. ([0077] Due to the presence of the side resin portion 70, since the cut surface is the same member, a uniform surface can be formed and the moisture resistance is improved.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to include the sealing member 9 and the side resin portions 70 of Koike in the device of Yamaji in order to create a flat cut surface and improve moisture resistance.
Regarding Claim 8, Yamaji further discloses the thickness of the chip (2) is 50 µm to 700 µm. ([0049] A thickness TC of the chip main body 2 may be 50 μm or more and 700 μm or less.)
and that the width (thickness) of the side surface covering portion (22) may be 10 μm or more and 100 μm or less.
The lower end of the range for the thickness of the chip 2 is lower than the upper range for the thickness of the side surface covering portion 22. Therefore, it would have been obvious to a person having ordinary skill in the art, based on the teachings of Yamaji, to select thicknesses for the chip 2 and the side surface covering portion 22 such that the width (thickness) of the side surface covering portion is larger than the thickness of the chip.
Regarding Claim 12, Yamaji further discloses (as shown in Fig. ) an insulating film ([0040] insulation layer 45) that partially covers the main surface electrode (39); (See Fig. 4, showing the insulating layer 45 covers a portion of the internal electrodes 39)
However, Yamaji in view of Koike fails to disclose wherein the main surface covering portion covers the main surface electrode across the insulating film.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the main surface covering portion (70, 9) covers the main surface electrode (32) across the insulating film (33). Koike teaches that the sealing portion 9 cover the semiconductor chip. ([0014] Forming a sealing portion by covering the semiconductor chip). Therefore, the sealing portion 9 would cover the insulating film 32 which is on the surface of the semiconductor chip.
Regarding Claim 13, Yamaji further discloses (as shown in Fig. 4) wherein the terminal electrode (10) has a portion that directly covers the insulating film (45). ([0097] the insulation layer 45 covers the internal electrode 39)
Regarding Claim 14, Yamaji further discloses (as shown in Fig. 4) wherein the insulating film (45) includes one of or both of an inorganic insulating film and an organic insulating film. ([0099] In this embodiment, the insulation layer 45 has a stacked-layer structure including a passivation layer 52 and a resin layer 53. [0100] The passivation layer 52 may have a single layer structure including a silicon oxide layer or a silicon nitride layer)
Claim(s) 1, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futamura et. al (JP 20200194959 A) in view of Koike et. al (JP 2004273977 A).
Regarding Claim 1, Futamura discloses (as shown in Fig. 12) A semiconductor device comprising:
a chip ([0009] With reference to FIGS. 1 to 6, the semiconductor device 1 includes a silicon chip 2) having a first main surface on one side ([0012] The chip 2 includes … a non-mounting surface 6 on the other side), a second main surface on the other side ([0012] The chip 2 includes a mounting surface 5 on one side), and a side surface connecting the first main surface (6) and the second main surface (5); (See Fig. 4, showing sidewalls of the substrate 3 connecting the mounting surface 5 and the non-mounting surface 6)
a main surface electrode ([0039] The semiconductor device 1 includes a plurality of (five in this embodiment) electrodes 32) arranged on the first main surface (6); ([0039] The semiconductor device 1 includes a plurality of (five in this embodiment) electrodes 32 formed on the non-mounting surface 6.)
a terminal electrode ([0093] lead wires 106) arranged on the main surface electrode (32);
However, Futamura fails to disclose a sealing insulator having a main surface covering portion that covers a periphery of the terminal electrode on the first main surface such as to expose the terminal electrode, and a side surface covering portion that covers the side surface such as to expose the second main surface.
Koike discloses (as shown in Fig. 34-35) a terminal electrode ([0022] The source lead 4 and the gate lead 6) arranged on the main surface electrode (11,12); ([0024] The semiconductor device 1 has a structure in which the source electrode 11 and the gate electrode 12 of the semiconductor chip 10 are bump-connected to the back surface of the second portion 8 of the source lead 4 and the gate lead 6)
a sealing insulator ([0079] Actually, the side resin portion 70 and the coating layer 71 are formed simultaneously with the formation of the sealing portion 9, and the side resin portion 70 and the coating layer 71 are formed integrally with the sealing portion 9) having a main surface covering portion ([0077] A side resin portion 70) that covers a periphery of the terminal electrode (4,6) on the first main surface (main surface) ([0077] The semiconductor device 1 of the sixth embodiment differs from the semiconductor device 1 of the first embodiment in that the outer surfaces of the first portions 7 (the first portions 7 of the source lead 4 and the gate lead 6) on both sides are made of an insulating resin)
such as to expose the terminal electrode (4,6), (See Fig. 34, showing the side resin 70 does not cover the top surface of the gate and source leads)
and a side surface covering portion ([0019] sealing portion 9) that covers the side surface such as to expose the second main surface (bottom surface). (See Fig. 34, showing the sealing portion 9 cover the side surface of the semiconductor chip 10 and exposing the bottom surface of the semiconductor chip 10)
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Koike teaches that that the sealing member creates a flat side surface ([0028] The cut surface becomes a flat surface. The source lead 4 and the sealing portion 9 are exposed on the flat side surface forming the side g, and the source lead 4, the gate lead 6 and the sealing portion 9 are exposed on the flat side surface forming the side i (FIG. 1). reference).) Koike further teaches that the side resin portion 70 improves the moisture resistance of the semiconductor device. ([0077] Due to the presence of the side resin portion 70, since the cut surface is the same member, a uniform surface can be formed and the moisture resistance is improved.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to include the sealing member 9 and the side resin portions 70 of Koike in the device of Futamura in order to create a flat cut surface and improve moisture resistance.
Furthermore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to replace the lead wires 106 of Futamura with a lead structure as in Koike in order to form the flat cut surface.
Regarding Claim 16, Futamura further discloses (as shown in Fig. 12) wherein the chip has a laminated structure including a substrate and an epitaxial layer, ([0009] the chip 2 has a laminated structure including the substrate 3 and the epitaxial layer 4.)
and includes the first main surface in which the epitaxial layer is exposed. ([0012] The non-mounting surface 6 is formed by the epitaxial layer 4)
Regarding Claim 17, Futamura in view of Koike fails to disclose wherein the epitaxial layer is thicker than the substrate.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date to have the epitaxial layer be thicker than the substrate. Futamura discloses that the semiconductor device can be an IGBT. ([0152] The semiconductor switching device may include at least one of JFET (Junction Field Effect Transistor), BJT (Bipolar Junction Transistor), MISFET (Metal Insulator Field Effect Transistor), and IGBT (Insulated Gate Bipolar Junction Transistor)) In a vertical IGBT, it is common practice to have the drift region (epitaxial layer) be thicker than the substrate in order to withstand high blocking voltages.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futamura in view of Koike as applied to claim 1 above, and further in view of Ota (US 2022/0102502 A1)
Regarding Claim 19, Futamura in view of Koike fails to disclose wherein the chip includes a monocrystal of a wide bandgap semiconductor.
Ota discloses (as shown in Fig. 1) wherein the chip includes a monocrystal of a wide bandgap semiconductor. ([0073] Referring to FIG. 3 to FIG. 8, the SiC semiconductor device 1 includes an SiC chip 2 constituted of the 4H-SiC monocrystal)
Silicon carbide is a well-known wide bandgap semiconductor material, which is used because of its better heat dissipation and faster switching speeds than Silicon. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use a Silicon Carbide monocrystalline substrate, as in Ota, instead of the Silicon substrate of Futamura in order to increase heat dissipation and switching speeds.
Regarding Claim 20, Futamura in view of Koike fails to disclose wherein the chip includes a SiC monocrystal.
Ota discloses (as shown in Fig. 1) wherein the chip includes a SiC monocrystal. ([0073] Referring to FIG. 3 to FIG. 8, the SiC semiconductor device 1 includes an SiC chip 2 constituted of the 4H-SiC monocrystal)
Allowable Subject Matter
Claim 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 11, none of Koike, Yamaji in view of Koike, or Futamura in view of Koike disclose wherein the second main surface electrode has a portion that is drawn out from the second main surface onto the side surface covering portion.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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