Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention II, species A without traverse directed in the reply filed on 07/31/2026 is acknowledged. Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 15-17, 21-22, and 24-28 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim et al. (US 20190051612 A1; hereinafter “Kim”)
In regard to claim 15, Kim teaches a method to manufacture an electronic device (semiconductor package 100) (Fig. 1A and paragraph 26), comprising:
providing a lid (a heat spreading layer 110 and a shielding wall 130 form the lid) comprising a first side and a second side (the heat spreading layer 110 is shown with a top side and bottom side in Fig 1) (Fig. 6C, 6E and paragraphs 25 and 67);
providing an adhesive (chip adhesion layer 150) on the first side of the lid (the chip adhesion layer 150 is shown on the top side of the heat spreading layer 110 in Fig. 6G) (Fig. 6G and paragraph 58);
providing a first electronic component (first semiconductor chip 140A) on the first side of the lid on the adhesive (the first semiconductor chip 140A is shown on the topside of the chip adhesion layer 150) (Fig. 6G and paragraph 58);
providing an encapsulant (a first mold layer 170) on the first side of the lid and covering a lateral side of the first electronic component (the first mold layer 170 is shown on top of the heat spreading layer 110 and on the lateral side of the first semiconductor chip 140A in Fig. 6I) (Fig. 6I and paragraph 59); and
providing a substrate (a redistribution structure 180) over the encapsulant, over the first electronic component, and over the lid (Fig. 6K and paragraph 60), wherein the substrate comprises a dielectric structure (an insulating layer 184) and a conductive structure (upper pad 182) (Fig. 6K and paragraph 60), and wherein the first electronic component is coupled with the conductive structure (the upper pad 182 and first semiconductor chip 140A are connected through second conductive pillar 160) (Fig. 6K and paragraph 58).
In regard to claim 16, Kim teaches wherein the lid comprises a top plate (a heat spreading layer 110) and a sidewall (the shielding wall 130) extending from the top plate, and the sidewall is coupled with the substrate (the shielding wall 130 is shown extending from the heat spreading layer 110 and coupled to the upper pad 182 of the redistribution structure 180 in Fig. 6K) (Fig. 6K and paragraphs 26-27).
In regard to claim 17, Kim teaches a connector (the second conductive pillar 160) between the conductive structure and the first electronic component (Fig. 6K and paragraph 58), wherein the encapsulant is between the substrate and the first electronic component and covers a lateral side of the connector (the first mold layer 170 may fill a space between the redistribution structure 180 and the heat spreading layer 110, while covering a sidewall of the second conductive pillar 160) (Fig. 6K and paragraph 28).
In regard to claim 21, Kim teaches wherein the lid directly contacts the conductive structure of the substrate (the shielding wall 130 directly contacts the upper pad 182) (Fig. 6K).
In regard to claim 22, Kim teaches wherein the encapsulant contacts a lateral side of the adhesive (the first mold layer 170 may cover at least a sidewall of the first semiconductor chip 140A and therefore covers the adhesive as shown in Fig. 6K) (Fig. 6K).
In regard to claim 24, Kim teaches wherein the substrate comprise a redistribution layer (RDL) substrate (the redistribution structure 180 functions as the substrate) (Fig. 6K and paragraph 25).
In regard to claim 25, Kim teaches a method to manufacture an electronic device (semiconductor package 100) (Fig. 1A and paragraph 26), comprising:
providing a lid comprising a top plate comprising a first side, second side opposite to the first side, and a sidewall extending from the first side of the top plate (a heat spreading layer 110 and a shielding wall 130 form the lid, where the shielding wall 130 is shown extending from the heat spreading layer 110) (Fig. 6C, 6E and paragraphs 25-27 and 67);
providing an adhesive (chip adhesion layer 150) on the first side of the top plate (the chip adhesion layer 150 is shown on the top side of the heat spreading layer 110 in Fig. 6G) (Fig. 6G and paragraph 58);
providing a first electronic component (first semiconductor chip 140A) on the first side of the top plate and coupled to the first side of the top plate with the adhesive (the first semiconductor chip 140A is shown on the topside of the chip adhesion layer 150) (Fig. 6G and paragraph 58);
providing an encapsulant (a first mold layer 170) over the first side of the top plate and covering a lateral side of the first electronic component (the first mold layer 170 is shown on top of the heat spreading layer 110 and on the lateral side of the first semiconductor chip 140A in Fig. 6I) (Fig. 6I and paragraph 59); and
proving a substrate (a redistribution structure 180) over the encapsulant (Fig. 6K and paragraph 60), wherein the substrate comprises a dielectric structure (an insulating layer 184) and a conductive structure (upper pad 182) (Fig. 6K and paragraph 60), and wherein the first electronic component is coupled with the conductive structure (the upper pad 182 and first semiconductor chip 140A are connected through second conductive pillar 160) (Fig. 6K and paragraph 58).
In regard to claim 26, Kim teaches wherein the encapsulant contacts a lateral side of the adhesive (the first mold layer 170 may cover at least a sidewall of the first semiconductor chip 140A and therefore covers the adhesive as shown in Fig. 6K) (Fig. 6K).
In regard to claim 27, Kim teaches wherein the encapsulant contacts an interior lateral side of the sidewall (the first mold layer 170 may cover at least a sidewall of the shielding wall 130) (Fig. 6K and paragraph 28).
In regard to claim 28, Kim teaches wherein the encapsulant contacts an exterior lateral side of the sidewall (the first mold layer 170 is shown covering an external sidewall of the shielding wall 130 in Fig. 6K).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 16 above, and further in view of Ree et al. (US 2024/0186213 A1; hereinafter “Ree”)
In regard to claim 23, Kim doesn’t explicitly teach wherein the adhesive contacts a lateral side of the sidewall of the lid.
Ree teaches a method to manufacture an electronic device (electronic device 10) (Fig. 2D and paragraph 38), wherein an adhesive (TIM l16) contacts a lateral side of the sidewall of a lid (TIM overflow 1611 of TIM 16 can flow into and contact the side walls of TIM channels 146. The examiner notes the side wall of the lid includes the full thickness of D1 and D2 as shown in Fig. 2D)) (Fig. 2D and paragraphs 39, 44 and 46)
It would’ve been obvious to one skilled in the art to combine the teachings of Kim with the teachings of Ree to have the adhesive contact a lateral side of the sidewall of the lid since this improves adhesion strength (or bonding force) between components within the device as taught by Ree (paragraph 44).
Claims 29-32 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 25 above, and further in view of Hung et al. (US 2024/0178095 A1; hereinafter “Hung”).
In regard to claim 29, Hung teaches a method to manufacture an electronic device (a semiconductor device 10) (Fig. 3C and paragraph 39), wherein:
a first side of a top plate (a topside of a lid structure 1100) comprises a first region comprising a protrusion (a central region containing a protrusion 1104) and a second region adjacent to the protrusion ( a region of the lid structure 1100 next to the protrusion is shown in Fig. 3C) (Fig. 3C and paragraphs 53-54);
a first portion of an adhesive is on the protrusion (an adhesive layer 900 is shown on the protrusion in Fig. 3C) (Fig. 3C and paragraph 49); and
a first electronic component (semiconductor die 100) is coupled to the protrusion with the first portion of the adhesive (the semiconductor die 100 is shown coupled to the protrusion 1104 through an adhesive layer 900 in Fig. 3C) (Fig. 3C and paragraph 55).
It would have been obvious to one skilled in the art to combine the teachings of Km with the teachings of Hung to have the first side of the top plate comprises a first region comprising a protrusion and a second region adjacent to the protrusion; a first portion of the adhesive is on the protrusion; and the first electronic component coupled to the protrusion with the first portion of the adhesive since it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
In regard to claim 30, Kim in view of Hung teach the method, comprising:
providing a second electronic component (one of the plurality of first semiconductor chip 140A) over a second region of the top plate (the first semiconductor chip 140A on the right is shown over another region of the heat spreading layer 110 in Fig. 6K);
wherein a second portion of the adhesive is on the second region of the top plate (another portion of the chip adhesion layer 150 is shown on the right side of the heat spreading layer 110 in Fig. 6K); and
wherein the second electronic component is coupled to the second region of the top plate with the second portion of the adhesive (the first semiconductor chip 140A may be attached to an underside (e.g., a bottom surface) of the chip portion 112 of the heat spreading layer 110 by a chip adhesion layer 150) (Fig. 6K and paragraph 23).
In regard to claim 31, Kim teaches wherein the encapsulant extends between a first portion of the adhesive and the second portion of the adhesive (the chip adhesion layer 150 is shown separated into two portions on the left and right side with the first mold layer 170 shown in between in Fig. 6K).
In regard to claim 32, Kim teaches wherein the encapsulant contacts the first side of the top plate between the first portion of the adhesive and the second portion of the adhesive (the first mold layer 170 is shown on the topside of the heat spreading layer 110 between the left and right sides of the device as shown in Fig. 6K).
In regard to claim 34, Kim teaches wherein the first portion of the adhesive is discrete from the second portion of the adhesive (the chip adhesion layers 150 are shown separated from one another in Fig. 6K).
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hung as applied to claim 30 above, and further in view of Chen et al. (US 2016/0133602 A1; hereinafter “Chen”).
In regard to claim 33, Kim in view of Hung doesn’t explicitly teach wherein the first portion of the adhesive is continuous with the second portion of the adhesive.
Chen teaches an electronic device (a chip-on-wafer-on-substrate (CoWoS) package 100) (Fig. 1H and paragraph 14), wherein a first portion of an adhesive is continuous with a second portion of the adhesive (as shown in Fig. 1H a portion of a thermal interface material (TIM) 58 over a die stack 10 disposed is continuous with a portion of the thermal interface material (TIM) 58 between two low-power consuming die stacks 12) (Fig. 1H, paragraphs 14 and 20).
It would’ve been obvious to one skilled in the art to combine the teachings of Kim in view of Hung with the teachings of Chen to have the first portion of the adhesive is continuous with the second portion of the adhesive since this layout is well known to allow for reduced production cost and easier manufacture due to less materials used and fewer processing steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Bowers et al. (US 2021/0272862 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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