DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 7, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marchant et al (US 2006/0237781).
Regarding Claim 1, Marchant et al discloses a method of manufacturing a semiconductor device (method of manufacturing a FET device [0016] Fig 3A-F), comprising the steps of:
forming a region of semiconductor material (n-type epitaxial layer 302 [0026] Fig 3A-F) having a surface;
forming a trench (trench 301 [0026] Fig 3A) extending from the surface into the region of semiconductor material (302 Fig 3A-F);
depositing a first oxide (oxide tapers [0024]/insulating layer 303a/b [0030] Fig 3A-F) along an inner wall of the trench (301 Fig 3A), the first oxide (303a/b Fig 3A-F) forming a first slope line (shown in Fig 3D-F) and having a first etch-back ratio;
depositing a second oxide (fill material 305a/b [0027] Fig 3A-F), different (material 305a has a higher etch rate compared to insulating layer 303a [0027]) from the first oxide (303a/b Fig 3A-F), along the first oxide (303a/b Fig 3A-F) that has been deposited (shown in Fig 3C) along the inner wall of the trench (301),
the second oxide (305a/b Fig 3A-F) forming a second slope line and having a second etch-back ratio that is higher than the first etch-back ratio (material 305a has a higher etch rate compared to insulating layer 303a [0027]);
etching back the first oxide (303a/b Fig 3A-F) and the second oxide (305a/b Fig 3A-F) at the same time (both the fill material 305a and insulating layer 303a are isotropically etched) to form a slope morphology comprising the first oxide (303a/b Fig 3A-F) and the second oxide (305a/b Fig 3A-F) in the trench (301 Fig 3A); and
depositing a third oxide (gate oxide layer 307 [0030] Fig 3E-F) along the slope morphology to form a second slope morphology comprising the first oxide (303a/b Fig 3A-F), the second oxide (305a/b Fig 3A-F) and the third oxide (307 Fig 3E-F) in the trench (301 Fig 3A).
Regarding Claim 3, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al further discloses
wherein the etching back step further comprises an isotropic etching process (both the fill material 305a and insulating layer 303a are isotropically etched [0028]).
Regarding Claim 7, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al further discloses
wherein the third oxide (gate oxide layer 307 [0030] Fig 3E-F) is one (the third oxide being an oxide is considered to meet this limitation in the broadest reasonable interpretation) of the first oxide (303a/b Fig 3A-F) and the second oxide (305a/b Fig 3A-F).
Regarding Claim 17, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al further discloses
wherein the semiconductor device is selected from the group consisting of: an Silicon-Gate Trench MOS (SGT-MOS) (trench gate vertical MOSFET [0003]), an Ultra-low ON-resistance MOS (U-MOS), an Insulated Gate Bipolar Transistor (IGBT), and a trench diode.
Regarding Claim 18, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al further discloses
a semiconductor device (FET device [0016] Fig 3A-F) manufactured using the method (method of manufacturing a FET device [0016] Fig 3A-F) according to claim 1.
Regarding Claim 19, Marchant et al discloses the limitations of claim 18 as explained above. Marchant et al further discloses
wherein the semiconductor device is selected from the group consisting of: an Silicon-Gate Trench MOS (SGT-MOS) (trench gate vertical MOSFET [0003]), an Ultra-low ON-resistance MOS (U-MOS), an Insulated Gate Bipolar Transistor (IGBT), and a trench diode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 8, 10-11, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781) in view of Filippi et al (US 2015/0235944), and Arghavani et al (US 2011/0309447).
Regarding Claim 2, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al does not directly disclose
wherein the first oxide and the second oxide are deposited using a thermal or sub-atmospheric chemical vapor deposition process.
Filippi et al, in the related art of semiconductor devices that include FET devices, discloses
wherein the first oxide (oxide layer 204a [0030] Fig 2A) and the second oxide (oxide region 204b [0030] Fig 2A) are deposited using a thermal or sub-atmospheric chemical vapor deposition process (sub-atomic chemical vapor deposition or SACVD process [0020]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marchant et al to include wherein the first oxide and the second oxide are deposited using a thermal or sub-atmospheric chemical vapor deposition process as taught by Filippi et al in order to protect the substrate [0127] as referred to by Arghavani et al. Further, a person of ordinary skill in the art would have recognized that using sub-atomic chemical vapor deposition would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 8, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al further discloses
the first oxide is a thermal oxide (oxide tapers [0024]/insulating layer 303a/b [0030] Fig 3A-F may be a thermal oxide/formed by a thermal oxidation process [0026]).
Marchant et al does not directly disclose
then the second oxide is selected from the group consisting of: a sub-atmospheric chemical vapor deposition (SACVD) oxide, and a high-density plasma (HPD) oxide; and if the first oxide is an SACVD oxide, then the second oxide is a HPD oxide.
Filippi et al, in the related art of semiconductor devices that include FET devices, discloses
then the second oxide (oxide region 204b [0030] Fig 2A) are deposited using a sub-atmospheric chemical vapor deposition process (sub-atomic chemical vapor deposition or SACVD process [0020]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marchant et al to include wherein the second oxide is a sub-atmospheric chemical vapor deposition (SACVD) oxide as taught by Filippi et al in order to protect the substrate [0127] as referred to by Arghavani et al. Further, a person of ordinary skill in the art would have recognized that using sub-atomic chemical vapor deposition would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 10, the combination of Marchant et al, Filippi et al, and Arghavani et al discloses the limitations of claim 2 as explained above. The combination of Marchant et al, Filippi et al, and Arghavani et al further discloses
wherein the etching back step further comprises an isotropic etching process (both the fill material 305a and insulating layer 303a are isotropically etched [0028] Marchant et al).
Regarding Claim 11, the combination of Marchant et al, Filippi et al, and Arghavani et al discloses the limitations of claim 2 as explained above. The combination of Marchant et al, Filippi et al, and Arghavani et al further discloses
wherein the second etch-back ratio (etching of 305a [0029] Marchant et al) is selected from the group consisting of: about 5 times (about 6 or 8 times the etch rate [0029] Marchant et al) the first etch-back ratio (etching of 303a [0029] Marchant et al), and about 10 times the first etch-back ratio (etching of 303a [0029] Marchant et al).
The combination of Marchant et al, Filippi et al, and Arghavani et al does not directly disclose
wherein the second etch-back ratio is selected from the group consisting of: about 5 times the first etch-back ratio, and about 10 times the first etch-back ratio.
However, a person of ordinary skill in the art would know that the second etch-back ratio compared to the first etch-back ratio would be a result effective variable in that having a second etch-back ratio greater than the first-etch back ratio would optimize the efficiency of the fabrication process as having a quicker etch rate without sacrificing quality would optimize cost effectiveness.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Marchant et al, Filippi et al, and Arghavani et al to include wherein the second etch-back ratio is selected from the group consisting of: about 5 times the first etch-back ratio, and about 10 times the first etch-back ratio as taught Marchant et al in order to optimize the efficiency of the fabrication process as having a quicker etch rate without sacrificing quality would optimize cost effectiveness and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 14, the combination of Marchant et al, Filippi et al, and Arghavani et al discloses the limitations of claim 2 as explained above. The combination of Marchant et al, Filippi et al and Arghavani further disclosews
the first oxide is a thermal oxide (oxide tapers [0024]/insulating layer 303a/b [0030] Fig 3A-F may be a thermal oxide/formed by a thermal oxidation process [0026]).
The combination of Marchant et al, Filippi et al, and Arghavani, as applied to claim 2, does not directly disclose
then the second oxide is selected from the group consisting of: a sub-atmospheric chemical vapor deposition (SACVD) oxide, and a high-density plasma (HPD) oxide; and if the first oxide is an SACVD oxide, then the second oxide is a HPD oxide.
Filippi et al, in the related art of semiconductor devices that include FET devices, discloses
then the second oxide (oxide region 204b [0030] Fig 2A) are deposited using a sub-atmospheric chemical vapor deposition process (sub-atomic chemical vapor deposition or SACVD process [0020]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Marchant et al, Filippi et al, and Arghavani et al to include wherein the second oxide is a sub-atmospheric chemical vapor deposition (SACVD) oxide as taught by Filippi et al in order to protect the substrate [0127] as referred to by Arghavani et al. Further, a person of ordinary skill in the art would have recognized that using sub-atomic chemical vapor deposition would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781).
Regarding Claim 4, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al further discloses
wherein the second etch-back ratio (etching of 305a [0029]) is selected from the group consisting of: about 5 times (about 6 or 8 times the etch rate [0029]) the first etch-back ratio (etching of 303a [0029]), and about 10 times the first etch-back ratio (etching of 303a [0029]).
Marchant et al does not directly disclose
wherein the second etch-back ratio is selected from the group consisting of: about 5 times the first etch-back ratio, and about 10 times the first etch-back ratio.
However, a person of ordinary skill in the art would know that the second etch-back ratio compared to the first etch-back ratio would be a result effective variable in that having a second etch-back ratio greater than the first-etch back ratio would optimize the efficiency of the fabrication process as having a quicker etch rate without sacrificing quality would optimize cost effectiveness.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marchant et al to include wherein the second etch-back ratio is selected from the group consisting of: about 5 times the first etch-back ratio, and about 10 times the first etch-back ratio as taught Marchant et al in order to optimize the efficiency of the fabrication process as having a quicker etch rate without sacrificing quality would optimize cost effectiveness and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781) in view of Henson et al (US 2015/0325685) and Zhang et al (CN 106298929).
Regarding Claim 5, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al does not directly disclose
further comprising the steps of: before the step of etching back, performing a chemical mechanical polishing (CMP), and stopping the CMP at the first oxide.
Henson et al, in the related art of semiconductor devices that include FET devices, discloses
performing a chemical mechanical polishing (CMP) (chemical mechanical planarization CMP [0029]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marchant et al to include performing a chemical mechanical polishing process and stopping the CMP at the first oxide as taught by Henson et al in order to smoothen the slope morphology when repeating the step of etching back process and improve the quality of the device [page 9, lines 1-6] as referred to by Zhang et al. Further, a person of ordinary skill in the art would have recognized that using a CMP process would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781) in view of Zhang et al (CN 106298929).
Regarding Claim 6, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al does not directly disclose
further comprising the step of: repeating the step of etching back to smoothen the slope morphology.
Zhang et al, in the related art of semiconductor devices that include FET devices, discloses
using a repairing etching process and repeating the depositing process of passivation film 300 and etching to remove the passivation film until the initial silicon layer 214 becomes smooth ([page8, lines 23-33] Fig 12).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marchant et al to include the step of repeating the step of etching back to smoothen the slope morphology as taught by Zhang et al in order to improve sidewall smoothness and improve the quality of the device [page 9, lines 1-6]. Further, a person of ordinary skill in the art would have recognized that having more smoothness would improve the electrical functioning of the device as well as increase the reliability and durability of the device (see MPEP 2143.I(D)).
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781) in view of Park et al (US 2012/0292696).
Regarding Claim 9, Marchant et al discloses the limitations of claim 1 as explained above. Marchant et al does not directly disclose
further comprising the step of: depositing and etching back a source poly onto the slope morphology.
Park et al, in the related art of semiconductor devices that include FET devices, discloses
depositing (depositing [0039] Fig 4) and etching back (etch back [0039] Fig 4) a source poly (poly-1 [0039] Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Marchant et al to include depositing and etching back a source poly as taught by Park et al in order to form a functioning source with source electrodes [0039]. Further, a person of ordinary skill in the art would have recognized that depositing and etching back a source poly onto the slope morphology would be advantageous in having a fabrication process that is unperturbed [0042] and would result in a more efficient and cost-effective manufacturing process (see MPEP 2143.I(D)).
Regarding Claim 16, the combination of Marchant et al and Park et al discloses the limitations of claim 9 as explained above. The combination of Marchant et al and Park et al further discloses
forming in the trench at least one structure selected from the group consisting of: an input parasitic output capacitance, a gate oxide (gate oxide layer 307 [0030] Fig 3E-F Marchant et al), a gate poly, a P-body, an N-source, a contact, and a metal layer.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781) in view of Filippi et al (US 2015/0235944), and Arghavani et al (US 2011/0309447), and in further view of Henson et al (US 2015/0325685) and Zhang et al (CN 106298929).
Regarding Claim 12, the combination of Marchant et al, Filippi et al, and Arghavani et al discloses the limitations of claim 2 as explained above. The combination of Marchant et al, Filippi et al, and Arghavani et al does not directly disclose
further comprising the steps of: before the step of etching back, performing a chemical mechanical polishing (CMP), and stopping the CMP at the first oxide.
Henson et al, in the related art of semiconductor devices that include FET devices, discloses
performing a chemical mechanical polishing (CMP) (chemical mechanical planarization CMP [0029]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Marchant et al, Filippi et al, and Arghavani et al to include performing a chemical mechanical polishing process and stopping the CMP at the first oxide as taught by Henson et al in order to smoothen the slope morphology when repeating the step of etching back process and improve the quality of the device [page 9, lines 1-6] as referred to by Zhang et al. Further, a person of ordinary skill in the art would have recognized that using a CMP process would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781) in view of Filippi et al (US 2015/0235944), and Arghavani et al (US 2011/0309447), and in further view of Zhang et al (CN 106298929).
Regarding Claim 13, the combination of Marchant et al, Filippi et al, and Arghavani et al discloses the limitations of claim 2 as explained above. The combination of Marchant et al, Filippi et al, and Arghavani et al does not directly disclose
further comprising the step of: repeating the step of etching back to smoothen the slope morphology.
Zhang et al, in the related art of semiconductor devices that include FET devices, discloses
using a repairing etching process and repeating the depositing process of passivation film 300 and etching to remove the passivation film until the initial silicon layer 214 becomes smooth ([page8, lines 23-33] Fig 12).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Marchant et al, Filippi et al, and Arghavani et al to include the step of repeating the step of etching back to smoothen the slope morphology as taught by Zhang et al in order to improve sidewall smoothness and improve the quality of the device [page 9, lines 1-6]. Further, a person of ordinary skill in the art would have recognized that having more smoothness would improve the electrical functioning of the device as well as increase the reliability and durability of the device (see MPEP 2143.I(D)).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Marchant et al (US 2006/0237781) in view of Filippi et al (US 2015/0235944), and Arghavani et al (US 2011/0309447), and in further view of Park et al (US 2012/0292696).
Regarding Claim 15, the combination of Marchant et al, Filippi et al, and Arghavani et al discloses the limitations of claim 2 as explained above. The combination of Marchant et al, Filippi et al, and Arghavani does not directly disclose
further comprising the step of: depositing and etching back a source poly onto the slope morphology.
Park et al, in the related art of semiconductor devices that include FET devices, discloses
depositing (depositing [0039] Fig 4) and etching back (etch back [0039] Fig 4) a source poly (poly-1 [0039] Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Marchant et al, Filippi et al, and Arghavani et al to include depositing and etching back a source poly as taught by Park et al in order to form a functioning source with source electrodes [0039]. Further, a person of ordinary skill in the art would have recognized that depositing and etching back a source poly onto the slope morphology would be advantageous in having a fabrication process that is unperturbed [0042] and would result in a more efficient and cost-effective manufacturing process (see MPEP 2143.I(D)).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kumura et al (US 2006/0002170) which discloses a filed effect transistor (MOS transistor) [0006], and Kawazoe (US 2001/0055883) which discloses a semiconductor device with a polysilicon sidewall material that has a high etch selectivity with respect to an oxide [0005].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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