DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/02/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claims 1, 10-11 and 19 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nield (US 2018/0088989) in view of Park (US 2023/0043222).
Regarding claim 1, Nield discloses a method of operating a graphics processor, the graphics processor comprising a plurality of processing cores, the processing cores operable to execute processing tasks for processing jobs, the method comprising:
receiving one or more processing jobs for processing by the graphics processor (receiving different types of tasks; see at least Fig. 1 and paragraphs 0034-0035);
distributing one or more tasks for the processing job or jobs to processing cores of the plurality of processing cores for processing (scheduling tasks from the queue for execution by the processing unit 104 that comprises a plurality of shader cores; see at least Fig. 1 and paragraphs 0033-0034 and 0037); and
processing the tasks with the respective processing cores (task execution by processing unit 104; see at least Fig. 1 and paragraphs 0033-0034 and 0037);
wherein a first set of one or more of the processing cores of the graphics processor is configured to have a higher priority for the processing of tasks of a first type compared to a second set of one or more others of the processing cores (tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056); the method comprising:
distributing the tasks to the first and second sets of one or more processing cores for processing in accordance with the priorities of those sets of one or more processing cores for the processing of tasks of the first type (tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056).
Nield discloses the first and second sets of one or more processing cores, the fist type tasks and when distributing tasks to the first and second set of processing cores, the tasks comprising one or more tasks of the first type and one or more tasks of another type; as above, but is not clear about two different processing cores processing the first type task and the distribution of tasks of a first type for processing is prioritized to a first processing core over a second processing core.
Park discloses the above missing limitations; multiple processing cores processing one type of tasks, i.e. tasks included in a top-app group having the highest priority may be executed by multiple cores, i.e. tasks included in a top-app is prioritized to big core 81 and big core 82; see at least Fig. 8 and paragraphs 0056-0058.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Nield by the teachings of Park by having the above limitations so to more efficiently assigning task to a plurality of processing cores; see at least paragraph 0003.
Regarding claim 2, Nield in view of Park disclose the method of claim 1, wherein distributing one or more tasks for the processing job or jobs to processing cores of the plurality of processing cores for processing comprises queueing one or more tasks for respective processing cores (Nield; by task queue; see at least Fig. 1 and paragraphs 0034 and 0037-0038).
Regarding claim 3, Nield in view of Park disclose the method of claim 2, wherein queueing one or more tasks for a respective processing core comprises queueing up to a particular maximum number of tasks for the processing core (Nield; the queue has a maximum capacity; see at least paragraph 0054).
Regarding claim 4, Nield in view of Park disclose the method of claim 1, wherein when distributing tasks to the first and second set of processing cores, the tasks to be distributed comprising only one or more tasks of the first type, then tasks of the first type are distributed to both the first and the second set of processing cores (Nield; see at least paragraph 0046).
Regarding claim 5, Nield in view of Park disclose the method of claim 1, wherein when distributing tasks to the first and second set of processing cores, the tasks comprising one or more tasks of the first type and one or more processing tasks of another type, the processing tasks of the first type are distributed to the first set of processing cores, whilst the other processing tasks are distributed to the second set of processing cores (Nield; the processing block 104 has different types of ALUs with each type of ALU being optimized for a particular type of computation; see at least paragraph 0033 and the Park’s; multiple cores).
Regarding claim 6, Nield in view of Park disclose the method of claim 1, wherein distributing one or more tasks for the processing job or jobs to processing cores of the plurality of processing cores for processing comprises queueing one or more tasks for a respective processing core (Nield; see at least Fig. 1 and paragraphs 0034 and 0037-0038), the method further comprising, when distributing tasks to the first and second set of processing cores, the tasks comprising one or more tasks of the first type and one or more processing tasks of another type (Nield; tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056 and Park’s prioritization and multiple cores):
when all of the tasks of the first type have been distributed, distributing the processing tasks of another type to the first and second sets of processing cores by prioritizing distributing the tasks of another type to processing cores that have the smallest number of queued tasks (Nield; tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056 and Park’s prioritization and multiple cores).
Regarding claim 7, Nield in view of Park disclose the method of claim 1, wherein the tasks of the first type are compute tasks (Nield; see at least paragraphs 0033-0034).
Regarding claim 8, Nield in view of Park disclose the method of claim 1, wherein the second set of processing cores is configured to have a higher priority for the processing of tasks of a second type compared to the first set of one or more of the processing cores, the method comprising distributing tasks to the first and second sets of one or more processing cores for processing in accordance with the priorities of those sets of one or more processing cores for the processing of tasks of tasks of the second type (Nield; the task scheduling engine is programmed to prioritize any types of tasks, and tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056 and Park’s prioritization and multiple cores).
Regarding claim 9, Nield in view of Park disclose the method of claim 8, wherein the tasks of a second type tasks are non-compute tasks (Park; see at least paragraphs 0037 and 0056-0058).
Claim 10 is rejected on the same grounds as claim 1.
Claim 11 is rejected on the same grounds as claim 1.
Claim 12 is rejected on the same grounds as claim 2.
Claim 13 is rejected on the same grounds as claim 3.
Claim 14 is rejected on the same grounds as claim 4.
Claim 15 is rejected on the same grounds as claim 5.
Claim 16 is rejected on the same grounds as claim 6.
Claim 17 is rejected on the same grounds as claim 7.
Claim 18 is rejected on the same grounds as claim 8.
Claim 19 is rejected on the same grounds as claim 1.
Conclusion
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/YASSIN ALATA/Primary Examiner, Art Unit 2426
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