DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claims 1, 10-11 and 19 have been amended. The amendments overcome the previous drawings objection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Nield (US 2018/0088989) in view of Engh-Halstvedt (US 2023/0305963).
Regarding claim 1, Nield discloses a method of operating a graphics processor, the graphics processor comprising a plurality of processing cores, the processing cores operable to execute processing tasks for processing jobs, the method comprising:
receiving one or more processing jobs for processing by the graphics processor (receiving different types of tasks; see at least Fig. 1 and paragraphs 0034-0035);
distributing one or more tasks for the processing job or jobs to processing cores of the plurality of processing cores for processing (scheduling tasks from the queue for execution by the processing unit 104 that comprises a plurality of shader cores; see at least Fig. 1 and paragraphs 0033-0034 and 0037); and
processing the tasks with the respective processing cores (task execution by processing unit 104; see at least Fig. 1 and paragraphs 0033-0034 and 0037);
wherein a first set of one or more of the processing cores of the graphics processor is configured to have a higher priority for the processing of tasks of a first type compared to a second set of one or more others of the processing cores (tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056); the method comprising:
distributing the tasks to the first and second sets of one or more processing cores for processing in accordance with the priorities of those sets of one or more processing cores for the processing of tasks of the first type (tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056).
Nield discloses the first and second sets of one or more processing cores and the fist type tasks, but is not clear about two different sets of processing cores processing the first type task.
Engh-Halstvedt discloses the above missing limitation; compute processing tasks are distributed among multiple shader cores; see at least paragraphs 0133-0134.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify Nield by the teachings of Engh-Halstvedt by having the above limitations so to provide improvements to the provision of performance counters in data processors and data processing system; see at least paragraph 0004.
Regarding claim 2, Nield in view of Engh-Halstvedt disclose the method of claim 1, wherein distributing one or more tasks for the processing job or jobs to processing cores of the plurality of processing cores for processing comprises queueing one or more tasks for respective processing cores (Nield; by task queue; see at least Fig. 1 and paragraphs 0034 and 0037-0038).
Regarding claim 3, Nield in view of Engh-Halstvedt disclose the method of claim 2, wherein queueing one or more tasks for a respective processing core comprises queueing up to a particular maximum number of tasks for the processing core (Nield; the queue has a maximum capacity; see at least paragraph 0054).
Regarding claim 4, Nield in view of Engh-Halstvedt disclose the method of claim 1, wherein when distributing tasks to the first and second set of processing cores, the tasks to be distributed comprising only one or more tasks of the first type, then tasks of the first type are distributed to both the first and the second set of processing cores (Nield; see at least paragraph 0046).
Regarding claim 5, Nield in view of Engh-Halstvedt disclose the method of claim 1, wherein when distributing tasks to the first and second set of processing cores, the tasks comprising one or more tasks of the first type and one or more processing tasks of another type, the processing tasks of the first type are distributed to the first set of processing cores, whilst the other processing tasks are distributed to the second set of processing cores (Nield; the processing block 104 has different types of ALUs with each type of ALU being optimized for a particular type of computation; see at least paragraph 0033 and the Engh-Halstvedt; multiple cores).
Regarding claim 6, Nield in view of Engh-Halstvedt disclose the method of claim 1, wherein distributing one or more tasks for the processing job or jobs to processing cores of the plurality of processing cores for processing comprises queueing one or more tasks for a respective processing core (Nield; see at least Fig. 1 and paragraphs 0034 and 0037-0038), the method further comprising, when distributing tasks to the first and second set of processing cores, the tasks comprising one or more tasks of the first type and one or more processing tasks of another type (Nield; tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056):
when all of the tasks of the first type have been distributed, distributing the processing tasks of another type to the first and second sets of processing cores by prioritizing distributing the tasks of another type to processing cores that have the smallest number of queued tasks (Nield; tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056).
Regarding claim 7, Nield in view of Engh-Halstvedt disclose the method of claim 1, wherein the tasks of the first type are compute tasks (Nield; see at least paragraphs 0033-0034).
Regarding claim 8, Nield in view of Engh-Halstvedt disclose the method of claim 1, wherein the second set of processing cores is configured to have a higher priority for the processing of tasks of a second type compared to the first set of one or more of the processing cores, the method comprising distributing tasks to the first and second sets of one or more processing cores for processing in accordance with the priorities of those sets of one or more processing cores for the processing of tasks of tasks of the second type (Nield; the task scheduling engine is programmed to prioritize any types of tasks, and tasks have different types and execution of second phase tasks are prioritized over other tasks. Furthermore, wakeup event, i.e. bits, are used to determine which type of task is selected for execution and to identify a task of the selected type for execution; see at least paragraphs 0034-0036, 0041, 0046-0048 and 0056).
Regarding claim 9, Nield in view of Engh-Halstvedt disclose the method of claim 8, wherein the tasks of a second type tasks are non-compute tasks (Engh-Halstvedt; see at least paragraph 0050).
Claim 10 is rejected on the same grounds as claim 1.
Claim 11 is rejected on the same grounds as claim 1.
Claim 12 is rejected on the same grounds as claim 2.
Claim 13 is rejected on the same grounds as claim 3.
Claim 14 is rejected on the same grounds as claim 4.
Claim 15 is rejected on the same grounds as claim 5.
Claim 16 is rejected on the same grounds as claim 6.
Claim 17 is rejected on the same grounds as claim 7.
Claim 18 is rejected on the same grounds as claim 8.
Claim 19 is rejected on the same grounds as claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YASSIN ALATA/Primary Examiner, Art Unit 2426