DETAILED ACTION
This office action is in response to the application filed on 4/29/24.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brokaw (US20120153921).
Regarding Claim 1, Brokaw discloses a voltage regulator (fig. 4, 5) comprising: a power transistor (M0) configured to provide a load current (¶12 & 48); a voltage follower (MP2, MN0, M1, ¶39) configured to provide a gate voltage of the power transistor (gate of M0); and a circuit (M0R, 530, 540) configured to transform the gate voltage of the power transistor (gate of M0 to gate of M0R) into a mirror current of the load current and to adjust a current flow through the voltage follower based on the mirror current (¶58).
Regarding Claim 2, Brokaw discloses (fig. 4, 5) the circuit further configured to adjust the current flow through the voltage follower (via feedback of IFB) with a comparator (460) configured to generate the mirror current with a scale replica of the power transistor (M0R, ¶47).
Regarding Claim 3, Brokaw discloses (fig. 4, 5) the comparator (460) is configured with a trip point (point at which the comparator output toggles) determined by a size of the scale replica of the power transistor (size of M0R determines 590 which determines compensation ramp feed into comparator 460 which determines toggled output of the comparator, ¶40).
Regarding Claim 4, Brokaw discloses (fig. 4, 5) a gate of the scale replica (M0R) of the power transistor (M0) is configured to receive the gate voltage of the power transistor (see gates tied together in fig 5).
Regarding Claim 9, Brokaw discloses a circuit (fig. 3, 4, 5) comprising: a voltage follower (MP2, MN0, M1, ¶39, 800) configured to compare a voltage on a load (420) and a reference voltage (110); and an adaptive slew-rate booster (M0R, 530, 540) configured to transform an output voltage of the voltage follower into a replica of current drawn by the load (gate of M0 to gate of M0R) and to adjust current flows within the voltage follower based on the replica of the current (¶58).
Regarding Claim 11, Brokaw discloses (fig. 4, 5) the adaptive slew-rate booster (M0R, 530, 540) further configured to adjust the current flow through the voltage follower (via feedback of IFB) with a comparator (460) configured with a scale replica of a power transistor for the load (M0R, ¶47).
Regarding Claim 12, Brokaw discloses (fig. 4, 5) the comparator (460) is configured with a trip point (point at which the comparator output toggles) determined by a size of the scale replica of the power transistor (size of M0R determines 590 which determines compensation ramp feed into comparator 460 which determines toggled output of the comparator, ¶40).
Regarding Claim 13, Brokaw discloses (fig. 4, 5) a gate of the scale replica (M0R) of the power transistor (M0) is configured to receive the gate voltage of the power transistor (see gates tied together in fig 5).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 5-8, 10, 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art fails to disclose: “...the circuit further configured to adjust the current flow through the voltage follower with a plurality of comparators each configured to trip at a different magnitude of the load current.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 10, the prior art fails to disclose: “...the adaptive slew-rate booster configured to imbalance current flows in an error amplifier of the voltage follower to boost a slew rate of the output voltage of the voltage follower.” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 14, the prior art fails to disclose: “...the adaptive slew-rate booster further configured to adjust the current flow through the voltage follower with a plurality of comparators each configured to trip at a different level of the current drawn by the load” in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 18, the prior art fails to disclose: “...generating a gate voltage to a power transistor of a load with a voltage follower; and transforming the gate voltage into replicas of a load current in a plurality of comparators; and unbalancing current flows in the voltage follower to an extent based on the replica currents.” in combination with the additionally claimed features, as are claimed by the Applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20170371365, Kossel; Marcel A. discloses a voltage regulator.
US 20250330082, Jiang; Xi et al. discloses feed forward supply noise cancellation (FFNC) technique with load current sensor for regulator PSR improvement.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYLE J MOODY/
Primary Examiner, Art Unit 2838