Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 7-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Puranik (2023/0052808).
Claim 7: A method of sending a command from a host to a first device in a computing system, the host comprising a central processing unit (CPU) and host memory, the method comprising:
allocating a source buffer in the host memory; (Puranik ¶0010 disclosing receive, over the I/O channel, a command descriptor, the command descriptor including respective addresses for a source data buffer and a destination data buffer in the first memory device)
writing, to the source buffer, source data to be consumed by the first device in response to the command; (Puranik ¶0004 Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices; ¶0060 In one example, the producer is a host device. The producer allocates memory in an HDM for a data buffer . The HDM can be connected to a consumer , e.g., an accelerator. The producer writes to the data buffer , according to line; ¶0089 The command descriptor can be sent as one or more DMWr (deferred memory write) transactions)
generating the command having a flag and a first address, the flag being set to indicate that the first device is to access the host memory using a coherent cache on the first device, the first address referencing the source buffer in the host memory; and sending the command from the host to the first device. (Puranik Abstract Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device)
Claim 8: The method of claim 7, wherein the first device is connected to the host through a peripheral interconnect and a cache coherency manager in the host, the cache coherency manager managing the coherent cache on the first device. (Puranik ¶0037 Data produced and consumed by devices implementing the hardware interconnect as described herein can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to flags and descriptors used to facilitate data transmission as described herein; ¶0038 A host device can include a number of processing units, cache controllers, and be coupled to host-attached memory (HAM); The accelerator device can include several accelerated processing units or cores, an accelerator cache, and be coupled to host-managed device memory (HDM) for reading and writing data while performing accelerated operations)
Claim 9: The method of claim 7, further comprising: allocating a response buffer in the host memory; wherein the command includes a second address referencing the response buffer in the host memory. (Puranik ¶0088 data descriptor can be larger, e.g., 128 bytes, with an address pointing to the location of a source data buffer in the HDM , and another address pointing to the location of the destination data buffer, which can also be in the HDM . The contents of the data buffers can be read from or written into over the memory/cache channel)
Claim 10: The method of claim 9, further comprising: reading response data generated by the first device in response to the command. (Puranik ¶0010 the one or more processors can be further configured to: receive, over the I/O channel, a command descriptor, the command descriptor including respective addresses for a source data buffer and a destination data buffer in the first memory device; cache the respective addresses for the source and destination data buffers to the first cache; and non-coherently read or write the contents of the source and destination data buffer using the respective cached addresses
Claim 11: The method of claim 7, further comprising: sending the command from the host to a second device of the computing system and the first device in parallel. (Puranik ¶0121 aspects of the disclosure can be implemented according to a variety of different configurations and quantities of computing devices, including in paradigms for sequential or parallel processing, or over a distributed network of multiple devices)
Claim 12: The method of claim 11, further comprising: sending the command to a plurality of devices including the first device; and upon receiving a command completion from each of the plurality of devices, reading from response buffers in the memory. (Puranik ¶0089 data descriptor can include semaphore flags, a command, e.g., an indication of what operation to perform on the contents or the source or destination buffer, and a buffer source and destination address information; In a DMWr transaction, no write completion is sent in response to indicate that the write was successful)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 and 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brewer (2024/0070083) in view of Puranik (2023/0052808).
Claim 1: Brewer discloses: A computing system, comprising:
a host comprising a central processing unit (CPU), a host memory, and a cache coherency manager; (Brewer ¶0042 disclosing a host connected to a CXL device; host device includes a host processor 214 (e.g., comprising one or more CPUs or cores) (see ¶0043); ¶0043 host device can comprise or can be coupled to, host memory; host device can include coherence and memory circuitry; host device can be configured to manage coherency of data cached at the CXL device using, e.g., its coherence and memory circuitry )
a first device connected to the host through a peripheral interconnect and the cache coherency manager, the first device including a coherent cache that is managed by the cache coherency manager; and (Brewer ¶0014 Compute Express Link (CXL) is an open standard interconnect configured for high-bandwidth, low-latency connectivity between host devices and other devices such as accelerators, memory buffers, or smart input-output (I/O) devices; CXL provides memory semantics and mechanisms for cache coherency; ¶0004 memory devices can be coupled to a host (e.g., a host computing device) to store data, commands, or instructions for use by the host while the computer or electronic system is operating; ¶0019 CXL meta state is a data structure set by the host that informs attached devices of the current status of various elements of the CXL connection. One such aspect of the meta state includes which entity—for example the host or the memory device—has control over a cache line)
software, executing on the host, operable to allocate a source buffer in the host memory, write source data to the source buffer, generate a command having a flag and a first address, the flag being set, the first address referencing the source buffer in the host memory, and send the command to the first device; (Brewer ¶0029 controller can be configured to perform operations such as copy, write, read, error correct, etc. for the first memory device; ¶0030 controller comprises a command manager (CM) for the memory system; The CM can receive, such as from the host device , a read command for a particular logic row address in the first memory device or the second memory device; the CM can receive, from the host device , a write command for a logical row address; ¶0031 the buffer comprises a data buffer circuit that includes a region of a physical memory used to temporarily store data; ¶0038 determining a state of the dirty flag for the cache line; the dirty flag is checked first and, if marked clean, then the comparison of the original metadata and the current metadata proceeds)
Brewer in view of Puranik discloses:
where the first device is operable to receive the command, parse the command to identify that the flag is set and to obtain the first address, and read, in response to the flag being set, the source data from the source buffer by reading from the coherent cache using the first address.
Brewer discloses that the first device is operable to receive the command, parse the command to identify that the flag is set and to obtain the first address: (Brewer ¶0030 at least one of the processor or the controller comprises a command manager (CM) for the memory system. The CM can receive, such as from the host device, a read command for a particular logic row address in the first memory device; the CM can be configured to issue, to non-volatile memory and between issuing the read command and the write command, an access command associated with the first memory device; ¶0085 a dirty flag is maintained for the data in the cache line, and wherein the dirty flag is set in response to a change in data in the cache line). Brewer does not explicitly disclose read, in response to the flag being set, the source data from the source buffer by reading from the coherent cache using the first address. Puranik appears to suggest or disclose this limitation/concept: (Puranik ¶0010 one or more processors can be further configured to: receive, over the I/O channel, a command descriptor, the command descriptor including respective addresses for a source data buffer and a destination data buffer in the first memory device; cache the respective addresses for the source and destination data buffers to the first cache; ¶0015 the control information including one or more flags indicating the status of one or more data buffers in the first memory device). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include where the first device is operable to receive the command, parse the command to identify that the flag is set and to obtain the first address, and read, in response to the flag being set, the source data from the source buffer by reading from the coherent cache using the first address as taught by Puranik since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 2: The computing system of claim 1, wherein the peripheral interconnect comprises a fabric having at least one switch. (Brewer ¶0074 the machine can operate as a standalone device or can be connected (e.g., networked) to other machines; the machine can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge)
Claim 3: The computing system of claim 1,
wherein the first device is operable to send a command completion through the peripheral interconnect to the host in response to processing the command.
Brewer discloses the first a first device connected to the host through a peripheral interconnect and the cache coherency manager, but does not explicitly disclose that the first device is operable to send a command completion through the peripheral interconnect to the host in response to processing the command. Puranik appears to disclose this limitation/concept: (Puranik ¶0089 data descriptor can include semaphore flags, a command, e.g., an indication of what operation to perform on the contents or the source or destination buffer, and a buffer source and destination address information; In a DMWr transaction, no write completion is sent in response to indicate that the write was successful). ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include the first device is operable to send a command completion through the peripheral interconnect to the host in response to processing the command as taught by Puranik since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 4: The computing system of claim 1,
wherein the software is configured to allocate a response buffer in the host memory, and wherein the command includes a second address referencing the response buffer in the host memory.
Brewer discloses sending a command to first device, but does not explicitly disclose that the software is configured to allocate a response buffer in the host memory, and wherein the command includes a second address referencing the response buffer in the host memory. Puranik appears to disclose this limitation/concept: (Puranik ¶0088 data descriptor can be larger, e.g., 128 bytes, with an address pointing to the location of a source data buffer in the HDM , and another address pointing to the location of the destination data buffer, which can also be in the HDM . The contents of the data buffers can be read from or written into over the memory/cache channel). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include the software is configured to allocate a response buffer in the host memory, and wherein the command includes a second address referencing the response buffer in the host memory as taught by Puranik since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 5: The computing system of claim 4,
wherein the first device is operable to parse the command to identify the second address and write, in response to the flag being set, response data to the response buffer by writing to the coherent cache using the second address.
Brewer discloses that the first device is operable to parse the command, but does not disclose the first device is operable to parse the command to identify the second address and write, in response to the flag being set, response data to the response buffer by writing to the coherent cache using the second address. Puranik appears to suggests or disclose this limitation/concept: (Puranik ¶0087 flag and status values can correspond to the status of different data buffers whose addresses are stored in the descriptor; ¶0088 data descriptor can be larger, e.g., 128 bytes, with an address pointing to the location of a source data buffer in the HDM, and another address pointing to the location of the destination data buffer, which can also be in the HDM. The contents of the data buffers can be read from or written into over the memory/cache channel). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include the that the first device is operable to parse the command to identify the second address and write, in response to the flag being set, response data to the response buffer by writing to the coherent cache using the second address as taught by Puranik since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 14: A method of processing a command at a device sent by a host in a computing system, the host comprising a central processing unit (CPU) and host memory, the method comprising:
receiving, at the device, the command from the host; parsing, by the device, the command to identify a flag in the command that is set and to obtain a first address that references a source buffer in the host memory; and
Brewer discloses receiving, at the device, the command from the host: (Brewer ¶0030 at least one of the processor or the controller comprises a command manager (CM) for the memory system. The CM can receive, such as from the host device, a read command for a particular logic row address in the first memory device; the CM can be configured to issue, to non-volatile memory and between issuing the read command and the write command, an access command associated with the first memory device; ¶0085 a dirty flag is maintained for the data in the cache line, and wherein the dirty flag is set in response to a change in data in the cache line), but does not explicitly disclose parsing, by the device, the command to identify a flag in the command that is set and to obtain a first address that references a source buffer in the host memory. Puranik suggests or discloses this limitation/concept: (Puranik ¶0010 one or more processors can be further configured to: receive, over the I/O channel, a command descriptor, the command descriptor including respective addresses for a source data buffer and a destination data buffer in the first memory device; cache the respective addresses for the source and destination data buffers to the first cache; ¶0015 the control information including one or more flags indicating the status of one or more data buffers in the first memory device). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include receiving, at the device, the command from the host; parsing, by the device, the command to identify a flag in the command that is set and to obtain a first address that references a source buffer in the host memory as taught by Puranik since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Brewer, as modified above, discloses the following:
reading, by the device in response to the flag being set, source data from the source buffer by reading from a coherent cache on the device using the first address, wherein the coherent cache is managed by a cache coherency manager in the host. (Brewer ¶0030 at least one of the processor or the controller comprises a command manager (CM) for the memory system. The CM can receive, such as from the host device, a read command for a particular logic row address in the first memory device; the CM can be configured to issue, to non-volatile memory and between issuing the read command and the write command, an access command associated with the first memory device; ¶0085 a dirty flag is maintained for the data in the cache line, and wherein the dirty flag is set in response to a change in data in the cache line; ¶0014 Compute Express Link (CXL) is an open standard interconnect configured for high-bandwidth, low-latency connectivity between host devices and other devices such as accelerators, memory buffers, or smart input-output (I/O) devices; CXL provides memory semantics and mechanisms for cache coherency; ¶0004 memory devices can be coupled to a host (e.g., a host computing device) to store data, commands, or instructions for use by the host while the computer or electronic system is operating; ¶0019 CXL meta state is a data structure set by the host that informs attached devices of the current status of various elements of the CXL connection. One such aspect of the meta state includes which entity—for example the host or the memory device—has control over a cache line)
Claim 15: The method of claim 14, wherein the device is connected to the host through a peripheral interconnect. (Brewer ¶0014 Compute Express Link (CXL) is an open standard interconnect configured for high-bandwidth, low-latency connectivity between host devices and other devices such as accelerators, memory buffers, or smart input-output (I/O) devices; CXL provides memory semantics and mechanisms for cache coherency; ¶0004 memory devices can be coupled to a host (e.g., a host computing device) to store data, commands, or instructions for use by the host while the computer or electronic system is operating; ¶0019 CXL meta state is a data structure set by the host that informs attached devices of the current status of various elements of the CXL connection. One such aspect of the meta state includes which entity—for example the host or the memory device—has control over a cache line)
Claim 16: The method of claim 15, wherein the peripheral interconnect comprises a fabric having at least one switch. (Brewer ¶0074 the machine can operate as a standalone device or can be connected (e.g., networked) to other machines; the machine can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge)
Claim 17: The method of claim 15, further comprising:
sending, by the device to the host, a command completion through the peripheral interconnect.
Brewer discloses the device sending/receiving a command, but does not explicitly disclose sending, by the device to the host, a command completion through the peripheral interconnect. Puranik suggests or discloses this limitation/concept: (Puranik ¶0089 data descriptor can include semaphore flags, a command, e.g., an indication of what operation to perform on the contents or the source or destination buffer, and a buffer source and destination address information; In a DMWr transaction, no write completion is sent in response to indicate that the write was successful). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include sending, by the device to the host, a command completion through the peripheral interconnect as taught by Puranik since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Claim 18: The method of claim 17, further comprising:
parsing, by the device, the command to identify a second address that references a response buffer in the host memory; and writing, by the device in response to the flag being set, response data to the response buffer by writing to the coherent cache on the device using the second address.
Brewer discloses parsing the command by the device, but does not explicitly disclose parsing, by the device, the command to identify a second address that references a response buffer in the host memory; and writing, by the device in response to the flag being set, response data to the response buffer by writing to the coherent cache on the device using the second address. Puranik appears to suggest or disclose this limitation/concept: (Puranik ¶0088 data descriptor can be larger, e.g., 128 bytes, with an address pointing to the location of a source data buffer in the HDM , and another address pointing to the location of the destination data buffer, which can also be in the HDM . The contents of the data buffers can be read from or written into over the memory/cache channel; ¶0087 flag and status values can correspond to the status of different data buffers whose addresses are stored in the descriptor). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Brewer to include parsing, by the device, the command to identify a second address that references a response buffer in the host memory; and writing, by the device in response to the flag being set, response data to the response buffer by writing to the coherent cache on the device using the second address as taught by Puranik since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately; one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Allowable Subject Matter
Claims 6, 13, 19 and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 6: The computing system of claim 1, further comprising: a second device connected to the host through the peripheral interconnect and the cache coherency manager, the second device including a coherent cache that is managed by the cache coherency manager; where the software is operable to allocate another source buffer in the host memory, generate the command having a second address, the second address referencing the other source buffer in the host memory, and send the command to the second device; and where the second device is operable to receive the command, parse the command to identify that the flag is set and to obtain the second address, and read, in response to the flag being set, from the other source buffer by reading from the coherent cache using the second address.
Claim 13: The method of claim 7, wherein the source buffer comprises a first source buffer, wherein the source data comprises first source data, wherein the computing system includes a second device, and wherein the method comprises: allocating a second source buffer in the host memory; writing second source data to the second source buffer to be consumed by the second device in response to the command; generating the command to include a second address referencing the second source buffer in the host memory; and sending the command from the host to the second device.
Claim 19: The method of claim 17, wherein the command includes a second address for another source buffer in the host memory, wherein the command relates the first and second addresses with first and second device identifiers, respectively, wherein the device has the first device identifier, and wherein the method further comprises: identifying, by the device, the first address based on the first device identifier.
Claim 20: The method of claim 19, further comprising: parsing, by the device, the command to identify third and fourth addresses that reference first and second response buffers in the host memory, the command relating the third and fourth addresses with first and second device identifiers, respectively, the device having the first device identifier; and writing, by the device in response to the flag being set, response data to the first response buffer by writing to the coherent cache on the device using the third address, the device identifying the third address based on the first device identifier.
The closest patent or patent application prior art reference(s) found that is/are relevant to the applicant’s invention includes Puranik (2023/0052808) which discloses hardware interconnects and corresponding devices and systems for noncoherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and reduce the number and extent of coherent memory transactions to relatively smaller control information, including flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output (I/0) channels, and more data on memory and cache channels of a hardware interconnect that are more efficient for data transmission. Also, Brewer (2024/0070083) which discloses a system wherein A memory device receives a memory operation from a host. The memory operation establishes data and metadata in a cache line of the memory device upon receipt. The metadata is stored in a memory element that corresponds to the cache line. Later, an eviction trigger to evict the cache line is identified. Then, in response to the eviction trigger, current metadata of the cache line is compared with the metadata in the memory element to determine whether the metadata has changed. CXL provides memory semantics and mechanisms for cache coherency. The references do not appear to disclose the details of the dependent claims indicated above as allowable. The claim appear to overcome the prior art.
The closest non-patent literature prior art reference found that is relevant to the applicant’s invention includes the publication “SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link” (Lee, et, al.; 2023) which discloses a new dedicated control flow that efficiently enables data sharing among multiple computing nodes without the need to modify user applications, by leveraging message types defined in Compute Express Link (CXL). The publication further explores evaluating their proposed design based on an in-house simulation framework with detailed analytical models that mimic a cache-coherent multi-node disaggregated memory system. The reference does not appear to disclose the details of the dependent claims indicated above as allowable. The claim appear to overcome the prior art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIONE N SIMPSON whose telephone number is (571)272-5513. The examiner can normally be reached M-F; 7:30 a.m.-4:30 p.m..
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DIONE N. SIMPSON
Primary Examiner
Art Unit 3628
/DIONE N. SIMPSON/Primary Examiner, Art Unit 3629
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