DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 13, 2026 has been entered.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement filed on May 15 2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. Applicant is advised to cite the foreign reference (WO 2016/036649 A1) with a copy of the reference provided, or cite the foreign reference with a proper citation of the parent application (37 CFR 1.98(d)).
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 2-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1; Claims 2, 9, and 16 recite a method, a memory device, and a memory die, respectively. Thus, each of the claims fall under one of the four statutory categories.
Under Prong One of Step 2A of the 2019 Revised Patent Subject matter Eligibility Guidance (“2019 PEG”), claim 2 recites “receiving an indication to perform a computational operation on a first vector and a second vector”, “determining an arithmetic output bit that is based on comparing the first set of contiguous bits of the first vector and the first set of contiguous bits of the second vector with bits of a truth table that indicates results of the computational operation for various combinations of logic values”, and “performing the computational operation on the second set of contiguous bits of the first vector and on the second set of contiguous bits of the second vector based at least in part on... the arithmetic output bit”. Such limitations cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and/or mathematical calculations, relationship and/or formulas. Therefore the claim includes limitations that fall within the “mental processes” and/or “mathematical concepts” groupings of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The elements “a first vector and a second vector each stored across a first plane and a second plane of the memory device”, “reading, from the first plane of a first memory tile, data representative of a first set of contiguous bits of the first vector”, “reading, from the first plane of the first memory tile, data representative of a first set of contiguous bits of the second vector”, and “communicating the arithmetic output bit to a second plane based on the second plane storing a second set of contiguous bits, of the first vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the first vector and storing a second set of contiguous bits, of the second vector, with bit positions that are contiguous with the bit positions of the first set of contiguous bits of the second vector” are considered to be insignificant extra-solution activities (MPEP 2106.05(g). The element “a memory device” does no more than generally link the use of the judicial exception to a particular technological environment or field of use (i.e., in-memory computation environment) (MPEP 2106.05(h)). The element “the first plane and the second plane comprising content-addressable memory cells” amounts to no more than applying the exception to a computer element recited at a high-level (MPEP 2106.05(f)). Additionally, the element does no more than generally link the use of the judicial exception to a particular technological environment or field of use (i.e., in-memory computation environment) (MPEP 2106.05(h)). Thus, the elements fail to integrate the judicial exception into a practical application.
Under Step 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to Step 2A Prong Two, the elements do not amount to significantly more as data gathering has been deemed to be well-understood, conventional, and routine by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The element “a memory device” does no more than generally link the use of the judicial exception to a particular technological environment or field of use (i.e., in-memory computation environment) (MPEP 2106.05(h)). The element “the first plane and the second plane comprising content-addressable memory cells” amounts to no more than applying the exception to a computer element recited at a high level (MPEP 2106.05(f)). Additionally, the element does no more than generally link the use of the judicial exception to a particular technological environment or field of use (i.e., in-memory computation environment) (MPEP 2106.05(h)). Accordingly, this claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 recites “the second plane is included in the first memory tile”. Such elements are recited at a high level of generality, i.e., reciting generic memory structure, which amounts to no more than mere instruction to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claim additionally recites “a third set of contiguous bits of the first vector and a third set of contiguous bits of the second vector are stored in a third plane of the first memory tile”. The additional element is considered to be an insignificant step of data gathering, i.e., reading or loading from memory (MPEP 2106.05(g)), and is deemed to be considered well-understood, conventional, and routine by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 recites “determining a second arithmetic output bit, as part of performing the computational operation the second set of contiguous bits of the first vector and on the second set of contiguous bits of the second vector, based on comparing the second set of contiguous bits of the first vector and the second set of contiguous bits of the second vector with the bits of the truth table”. Such limitation further cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. The claim additionally recites “communicating the second arithmetic output bit to the third plane based on the third plane storing the third set of contiguous bits of the first vector and the third set of contiguous bits of the second vector”. Such element is considered to be an insignificant step of data gathering, i.e., reading or loading from memory (MPEP 2106.05(g)), and is deemed to be considered well-understood, conventional, and routine by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 recites “the second arithmetic output bit is determined based on the arithmetic output bit”. Such limitation further cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 recites “wherein the second plane is included in a second tile”. Such elements are recited at a high level of generality, i.e., reciting generic memory structure, which amounts to no more than mere instruction to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claim additionally recites “a third set of contiguous bits of the first vector and a third set of contiguous bits of the second vector are stored in a third plane of a third tile”. The additional element is considered to be an insignificant step of data gathering, i.e., reading or loading from memory (MPEP 2106.05(g)), and is deemed to be considered well-understood, conventional, and routine by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 recites “determining a second arithmetic output bit, as part of performing the computational operation the second set of contiguous bits of the first vector and on the second set of contiguous bits of the second vector, based on comparing the second set of contiguous bits of the first vector and the second set of contiguous bits of the second vector with the bits of the truth table”. Such limitation further cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. The claim additionally recites “communicating the second arithmetic output bit to the third plane based on the third plane storing the third set of contiguous bits of the first vector and the third set of contiguous bits of the second vector”. Such element is considered to be an insignificant step of data gathering, i.e., reading or loading from memory, (MPEP 2106.05(g)) and is deemed to be considered well-understood, conventional, and routine by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 8 recites “the second arithmetic output bit is determined based on the arithmetic output bit”. Such limitation further cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion) and mathematical calculations, relationship and/or formulas. The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 is mostly rejected for the same reasons as claim 2. The claim additionally recites “a memory die comprising a first memory tile and a second memory tile each comprising a plurality of planes” , “each plane comprises a respective array of content- addressable memory cells”, and “controller circuitry coupled with the memory die”. Such elements are recited at a high level, i.e., reciting generic memory structure and/or generic circuitry, which amounts to no more than mere instruction to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 10-15 recite a memory device similar to the method of claims 3-8, respectively. Therefore, the claims are rejected on the same premises.
Claim 16 is mostly rejected for the same reasons as claim 2. The claim additionally recites “a memory die”, “a first memory tile of content-addressable memory cells”, and “a second memory tile of content-addressable memory cells”. Such elements are recited at a high level, i.e., reciting generic memory structure, which amounts to no more than mere instruction to apply the exception using generic computer elements (see MPEP 2106.05(f)). The claim fails to provide an element that would integrate the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 17-21 recite a memory die similar to the method of claims 3-7, respectively. Therefore, the claims are rejected on the same premises.
Response to Arguments
Applicant's arguments, see Pages 9-12, filed March 13, 2026, have been fully considered but they are not persuasive.
Regarding arguments on page 9, last paragraph to page 19, third paragraph, Applicant argues that the elements indicated as “extra-solution activities” is improper because the additional elements imposes significant limits.
Examiner respectfully disagrees with this argument. See MPEP 2106.05(g) regarding insignificant extra-solution activity and MPEP 2106.05(f) regarding mere instructions to apply an exception. The additional limitations are not enough to integrate the features into the claim and it does not impose significant and meaningful limits to the claim as indicating that the planes comprise of CAM cells follows the idea of “applying” the exception into planes comprising of CAM cells (MPEP 2106.05(f)) and generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), which does not result in a meaningful limitation or integrates the elements indicated as “insignificant extra-solution activity” into the claim. Therefore, the remarks regarding that the additional elements imposes significant limits is considered not persuasive.
Regarding arguments on page 11, third paragraph to page 12, first paragraph, Applicant argues that the additional elements recite an improvement of an accelerator that includes the memory device content-addressable memory cells.
Examiner respectfully disagrees with this argument. For the sake of brevity, Examiner will focus on the new elements amended to the claim. Recall that MPEP 2106.05(a) states that "It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements" and "it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology". First, the “improvement” that Applicant is claiming is simply a result of associative processing and therefore, does not integrate the exception into a practical application or provide an inventive concept (See MPEP 2106.05(f) and MPEP 2106.05(h)) (note this is also evident as paragraph [0023] discuss how in-memory associative processing uses parallelism to increase processing bandwidth and avoids bottlenecking between the host device and APM system, thus the improvement comes solely from the associative processor, not from what the Applicant has invented). Second, the new additional elements do not provide an improvement as such additional elements analyzed under Step 2A Prong Two and Step 2B are either considered to be an insignificant step of data gathering, i.e., reading or loading from memory (MPEP 2106.05(g)) that is deemed to be considered well-understood, conventional, and routine by the courts (MPEP 2106.05(d)), amounts to no more than mere instructions to apply the exception using computer elements recited at a high level (see MPEP 2106.05(f)), or generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). As it stands, only the abstract idea provides the "improvement" of the invention as a whole. Applicant has not claimed an element that demonstrates an improvement to a well-known associative processor architecture. Therefore, the remarks regarding that the additional element provides an improvement is considered not persuasive.
The rejections of claims 2-21 under 35 U.S.C. 101 will be maintained.
Examiner’s Remarks
In assisting the Applicant to push this application in a state for allowance, Examiner recommends that either Applicant points to what causes the increased processing bandwidth within the planes or tiles rather than indicating, at a high-level, that associative processing causes the increased processing bandwidth. Alternatively, Applicant may insert an element that, when read from the specification, recites an improvement that does not come from the abstract idea. This can be done by either indicating a specific process/step, indicating an element that isn’t “generic” or recited “at a high level”, or indicating “generic” elements or elements recited “at a high level” that, in combination, provides an improvement that is not well-known (see MPEP 2106.05(a) and MPEP 2106.05(d)). Applicant is invited to set up an interview with the Examiner for further questions or propositions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.A./Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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