Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-11 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “a first dielectric layer covering the plurality of first gate structures, the second gate structure and the semiconductor substrate” and this is true in Fig. 7 of the instant Application however see Fig. 8 the top of 130 has been removed see “Referring to FIG. 8, according to embodiments of the present application, a process is carried out to expose the first gate structures 110, the second gate structure 120 and the source and drain regions on opposite sides of each of the first gate structures 110 and the second gate structure 120. Specifically, the process may be an etching process, or a combined polishing and etching process”, see Fig. 10 see paragraph 0043, that 130 is not covering the tops of the “first gate structures 110” and the source/drain regions of the substrate where “drain salicide 210” is formed, thus it is assumed that the Applicant means to say “a first dielectric layer covering a portion of the plurality of first gate structures, the second gate structure and the semiconductor substrate”.
Allowable Subject Matter
Claims 6-8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9, 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sugimae et al. (US 20030151069 A1) hereafter referred to as Sugimae. Katsumata et al. (US 20050151191 A1) hereafter referred to as Katsumata is provided as evidence for claim 11.
In regard to claim 9 [see 112 rejection] Sugimae teaches a [see Fig. 10, see paragraph 0111 “FIG. 4 is a partial sectional view along the bit line of the semiconductor device (NAND flash memory) according to a first embodiment of the present invention”] flash memory device, comprising:
a semiconductor substrate [“semiconductor substrate 1”] comprising an array region [“A part of a memory cell portion 30 and a part of a peripheral circuit portion 31 are shown” see Abstract “memory cell array portion”] and a peripheral region;
a plurality of first gate structures [“In the left direction, a selection gate 3 and three associated memory cell gates 2 are shown”] located on the semiconductor substrate in the array region, wherein adjacent first gate structures are spaced by a first gap [see above “source/drain region 12 of each memory cell”] or a second gap [see above “source/drain region 13 of the selection transistor”], and wherein the first gap has a width smaller [“As for the interval between the gate electrodes, an interval between the memory cell gates 2 is small, and an interval between the selection gates 3 between which the bit line contact 15 is held is large”] than a width of the second gap;
a second gate structure [“peripheral gate 4 of the peripheral circuit portion 31”] located on the semiconductor substrate in the peripheral region;
a first dielectric layer [see Fig. 10, “side surfaces of the memory cell gate 2, selection gate 3, and peripheral gate 4 are covered with a post oxide film 16”, see 112 rejection above] covering the plurality of first gate structures, the second gate structure and the semiconductor substrate; and
a second dielectric layer [see Fig. 8A, Fig. 8B “A first insulation film 18 is disposed on the sidewall and upper surface of the memory cell transistor, one side surface of the selection gate, and side surface of the peripheral gate” “The first insulation film 18 is disposed to fill among the memory cell gates 2 of the memory cell transistors”] covering the first dielectric layer and filling up [see Fig. 8 A, Fig. 8B] the first gap.
In regard to claim 11 Sugimae teaches wherein the first dielectric layer [see “post oxide film 16” is a type of silicon oxide, see Katsumata is provided as evidence see “The post-oxide film 6 is a silicon oxide film formed by, for example, thermal oxidation and natural oxidation” ] is silicon oxide, and the second dielectric layer [see “A film having little hydrogen content and few traps with respect to charges is suitable for the first insulation film 18. Usable examples of the film include a silicon oxide film, oxynitride film, and the like. An oxynitride film is obtained by nitriding a silicon oxide film, so that the oxynitride film does not include nitrogen as a main component”, however the Examiner notes that “nitriding a silicon oxide film” means that it comprises silicon nitride, thus under broadest reasonable interpretation the limitation is satisfied because an oxynitride is a form of nitride ] is silicon nitride.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugimae et al. (US 20030151069 A1) hereafter referred to as Sugimae in view of Hung et al. (US 20120309158 A1) hereafter referred to as Hung. Katsumata et al. (US 20050151191 A1) hereafter referred to as Katsumata is provided as evidence for claim 3.
In regard to claim 1 Sugimae teaches a method [see Fig. 7, see paragraph 0111 “FIG. 4 is a partial sectional view along the bit line of the semiconductor device (NAND flash memory) according to a first embodiment of the present invention”] for fabricating a flash memory device, comprising:
providing a semiconductor substrate [“semiconductor substrate 1”] comprising an array region [“A part of a memory cell portion 30 and a part of a peripheral circuit portion 31 are shown” see Abstract “memory cell array portion”] and a peripheral region, wherein a plurality of first gate structures [“In the left direction, a selection gate 3 and three associated memory cell gates 2 are shown”] are formed on the semiconductor substrate in the array region, wherein a second gate structure [“peripheral gate 4 of the peripheral circuit portion 31”] is formed on the semiconductor substrate in the peripheral region, wherein adjacent first gate structures are spaced by a first gap [see above “source/drain region 12 of each memory cell”] or a second gap [see above “source/drain region 13 of the selection transistor”], the first gap having a width smaller [“As for the interval between the gate electrodes, an interval between the memory cell gates 2 is small, and an interval between the selection gates 3 between which the bit line contact 15 is held is large”] than a width of the second gap;
forming a first dielectric layer [see Fig. 7, “side surfaces of the memory cell gate 2, selection gate 3, and peripheral gate 4 are covered with a post oxide film 16”] over the semiconductor substrate, wherein the first dielectric layer covers the plurality of first gate structures, the second gate structure and the semiconductor substrate;
forming a second dielectric layer [see Fig. 8A, Fig. 8B “A first insulation film 18 is disposed on the sidewall and upper surface of the memory cell transistor, one side surface of the selection gate, and side surface of the peripheral gate” “The first insulation film 18 is disposed to fill among the memory cell gates 2 of the memory cell transistors”] over the first dielectric layer, wherein the second dielectric layer fills up [see Fig. 8 A, Fig. 8B] the first gap;
forming a hard mask layer [ “as shown in FIG. 9, the memory cell portion 30 is covered with a mask material 33”] over the second dielectric layer, wherein the hard mask layer fills up [see Fig. 9] the second gap;
forming spacers [see Fig. 9 , “the first insulation film 18 formed in the upper part of the peripheral gate 4 and the first insulation film 18 formed on the upper surface of the semiconductor substrate 1 are removed by reactive ion etching (RIE) in the peripheral circuit portion 31. At this time, a tapered portion 34 is formed in the first insulation film 18 in the sidewall upper part”] on opposite sides of the second gate structure by etching the hard mask layer;
removing a remaining portion of the hard mask layer [“Thereafter, the mask material 33 is removed”]
but does not specifically teach “forming a patterned photoresist layer that covers the spacers; and removing a remaining portion of the hard mask layer and the patterned photoresist layer”.
See that Sugimae says that “Thereafter, the mask material 33 is removed” however Sugimae does not state how the “first insulation film 18 in the sidewall” is protected when removing mask material 33. See paragraphs 0142-0146, Sugimae understands etching.
However photoresist is well known in the art.
See Hung teaches “as shown in FIG. 2, a patterned photoresist (not shown) is formed on the hard mask 110, and a pattern transfer is performed by using the patterned photoresist as mask to partially remove the hard mask 110, the polysilicon layer 108, the high-k dielectric layer 106, and the interfacial layer 104 through single or multiple etching processes. After stripping the patterned photoresist, a dummy gate 112 is formed on the substrate 100”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sugimae to include “forming a patterned photoresist layer that covers the spacers; and removing a remaining portion of the hard mask layer and the patterned photoresist layer”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to protect “first insulation film 18 in the sidewall” from damage when removing mask material 33.
In regard to claim 2 Sugimae and Hung as combined does not specifically teach wherein forming the second dielectric layer filling up the first gap over the first dielectric layer comprises: forming the second dielectric layer over the first dielectric layer to a thickness of 300 Å to 450Å; and etching the second dielectric layer to thin the second dielectric layer by a thickness of 100Å to 220Å.
However see Sugimae Fig. 8A, Fig. 8B see “an interval between the gate electrodes is about 0.2 .mu.m” “The first insulation film 18 has a thickness, for example, of about 0.05 .mu.m or more”, see “It is to be noted that as shown in FIG. 8B, there is another method comprising: after depositing the interlayer insulator 20, etching and removing the first insulation film 18 and post oxide film 16 by a chemical mechanical polishing (CMP) method until the memory cell gate 2, the selection gate 3, and the upper surface of the gate mask material 11 including the silicon nitride film on the peripheral gate 4 are exposed”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein forming the second dielectric layer filling up the first gap over the first dielectric layer comprises: forming the second dielectric layer over the first dielectric layer to a thickness of 300 Å to 450Å; and etching the second dielectric layer to thin the second dielectric layer by a thickness of 100Å to 220Å ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 3 Sugimae and Hung as combined teaches wherein the first dielectric layer [see “post oxide film 16” is a type of silicon oxide, see Katsumata is provided as evidence see “The post-oxide film 6 is a silicon oxide film formed by, for example, thermal oxidation and natural oxidation” ] is silicon oxide, and the second dielectric layer [see “A film having little hydrogen content and few traps with respect to charges is suitable for the first insulation film 18. Usable examples of the film include a silicon oxide film, oxynitride film, and the like. An oxynitride film is obtained by nitriding a silicon oxide film, so that the oxynitride film does not include nitrogen as a main component”, however the Examiner notes that “nitriding a silicon oxide film” means that it comprises silicon nitride, thus under broadest reasonable interpretation the limitation is satisfied because an oxynitride is a form of nitride ] is silicon nitride.
In addition to the above broadest reasonable interpretation rejection, the Examiner is also giving a case law rejection.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use " silicon nitride ", since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 4 Sugimae and Hung as combined does not specifically teach wherein the hard mask layer that is formed over the second dielectric layer and fills up the second gap has a thickness of 1000Å to 2000Å.
However see Sugimae Fig. 8A, Fig. 8B see “an interval between the gate electrodes is about 0.2 .mu.m” “The first insulation film 18 has a thickness, for example, of about 0.05 .mu.m or more”, see “As for the interval between the gate electrodes, an interval between the memory cell gates 2 is small, and an interval between the selection gates 3 between which the bit line contact 15 is held is large”.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the hard mask layer that is formed over the second dielectric layer and fills up the second gap has a thickness of 1000Å to 2000Å ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 5 Sugimae and Hung as combined teaches wherein removing the remaining portion of the hard mask layer and the patterned photoresist layer comprises: etching away [see combination Hung, both Sugimae and Hung know etching to remove mask material] the remaining portion of the hard mask layer; and stripping off [see combination Hung] the patterned photoresist layer.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugimae et al. (US 20030151069 A1) hereafter referred to as Sugimae in view of Inoue (KR 20020062576 A)
In regard to claim 10 Sugimae teaches wherein a source region [“source/drain region 12 of each memory cell is disposed in the semiconductor substrate 1 on the both sides of the memory cell gate 2” “A lightly-doped source/drain diffusion layer 23 is disposed in the semiconductor substrate 1 under the sidewall of the peripheral gate 4, and a heavily-doped source/drain diffusion layer 24 is disposed in the semiconductor substrate 1 outside the lightly-doped source/drain diffusion layer”] and a drain region are formed in the semiconductor substrate on opposite sides of each of the first gate structure and the second gate structure, and
but does not specifically teach wherein a first gate salicide is formed on a surface of the first gate structure, a second gate salicide formed on a surface of the second gate structure and a source salicide and a drain salicide formed on surfaces of the source and drain regions.
However this is common in the art, see Inoue teaches etching and siliciding of the gates and source/drains of both peripheral and memory cell transistors, see “In FIG. 2H, the second nitride film 27 can be formed by, for example, the CVD method. The second nitride film 27 may, for example, have a thickness of about 200 nm. The second nitride film 27 may be etched back to be left as a sidewall at the side of the gate electrode of the memory cell region 10a and the peripheral transistor region 10b. Next, an alloy containing CoSi (cobalt silicide) can be formed, for example, by sputtering. The alloy may be about 11 nm thick. The alloy is then subjected to several annealing treatments. Excess CoSi can then be removed. In this manner, the metal silicide layer 28 is formed on the drain region 23 and the source region 24 of the memory cell region 10a and the source / drain region 26 and the gate electrode of the peripheral transistor region 10b. It may be formed by a silicide process.”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sugimae to include wherein a first gate salicide is formed on a surface of the first gate structure, a second gate salicide formed on a surface of the second gate structure and a source salicide and a drain salicide formed on surfaces of the source and drain regions.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that the presence of silicide helps reduce resistance.
[see that claim 11 was rejected as 102 above]
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sugimae et al. (US 20030151069 A1) hereafter referred to as Sugimae
In regard to claim 11 Sugimae teaches wherein the first dielectric layer [see “post oxide film 16” is a type of silicon oxide, see Katsumata is provided as evidence see “The post-oxide film 6 is a silicon oxide film formed by, for example, thermal oxidation and natural oxidation” ] is silicon oxide, and the second dielectric layer [see “A film having little hydrogen content and few traps with respect to charges is suitable for the first insulation film 18. Usable examples of the film include a silicon oxide film, oxynitride film, and the like. An oxynitride film is obtained by nitriding a silicon oxide film, so that the oxynitride film does not include nitrogen as a main component”, however the Examiner notes that “nitriding a silicon oxide film” means that it comprises silicon nitride, thus under broadest reasonable interpretation the limitation is satisfied because an oxynitride is a form of nitride ] is silicon nitride,
however since Sugimae does not state silicon nitride, the Examiner is also giving a case law rejection.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use " silicon nitride ", since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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