DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Amendment
The Response, filed on June 24, 2026, has been received and made of record. In response to the Non-Final Office Action dated January 26, 2026, claims 1 and 10 have been amended.
Response to Arguments
Regarding the 35 U.S.C. 112(a) rejection of claims 1-4 and 6-20, Applicant first argues that because figure 4 does not illustrate an insulating layer interposed between the first electrode and the photoelectric conversion layer, support for the negative limitation is provided (Remarks, pp. 6-7). The Examiner respectfully disagrees.
To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention. See, e.g., Moba, B.V. v. Diamond Automation, Inc., 325 F.3d 1306, 1319, 66 USPQ2d 1429, 1438 (Fed. Cir. 2003); Vas-Cath, Inc. v. Mahurkar, 935 F.2d at 1563, 19 USPQ2d at 1116. The limitation of “without an insulating layer between…” was not found to be described in the specification, as required by the written description requirement.
In view of the above, the Office stands behind the 35 U.S.C. 112(a) rejection of claims 1-4 and 6-20.
Applicant then argues that “a skilled artisan would understand a negative limitation to necessarily be present in a disclosure” citing Novartis Pharms. Corp. V. Accord Healthcare, Inc., 38 F.4th 1013, 1021 (Fed. Cri. 2022). (Remarks, p. 7). Again, the Examiner respectfully disagrees.
Although Novartis provides that it is possible that the written description requirement may be satisfied when a skilled artisan would understand the specification as inherently disclosing the negative limitation, the record has not been established, in this particular field, that “the absence of mention of a limitation necessarily excluded that limitation, written description could be satisfied despite the specification's silence.” See Tronzo v. Biomet, Inc. , 156 F.3d 1154, 1159 (Fed. Cir. 1998). Per Novartis, “[if] however a patent owner could establish that a particular limitation would always be understood by skilled artisans as being necessarily excluded from a particular claimed method or apparatus if that limitation is not mentioned, the written description would be satisfied despite the specification’s silence.” Applicant has not been found to meet this burden. Therefore, at least in view of the above, the Office stands behind the 35 U.S.C. 112(a) written description rejection of claims 1-4 and 6-20.
Regarding the 35 U.S.C. 112(b) rejection of claims 4 and 13, Applicant's arguments have been fully considered and are found to be persuasive. Therefore, the outstanding 35 U.S.C. 112(b) rejection of claims 4 and 13 is withdrawn.
Regarding the 35 U.S.C. 102 rejection of claims 4 and 13, Applicant argues that Tashiro does not teach the newly amended claim material (Remarks, pp. 8-10). The Examiner respectfully disagrees.
As what constitutes the “exposure period” and the “non-exposure period” is only currently defined in the claims by switching the voltage supplies, and not defined by the hole accumulation, etc. of Tashiro, Tashiro still is still found to teach the limitations of the claim, as currently recited. Specifically, the voltage supply circuitry starts the exposure period by switching the voltage supplied to the respective second electrodes from the second voltage to the first voltage (e.g., the transition from fig. 6B to fig. 6C, illustrating Voltage Vs2 switching to Vs1 at the second electrode 201), and ends the exposure period by switching the voltage supplied to the respective second electrodes from the first voltage to the second voltage (e.g., upon repeat of the cycle, fig. 6A to fig. 6B, illustrating Voltage Vs1 switching to Vs2 at the second electrode 201), and the exposure period starts and ends in common for the pixels (e.g., [0216]). In view of at least the above, and the claims as currently recited, the Office stands behind the 35 U.S.C. 102 rejection of claims 4 and 13,
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Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4 and 6-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1-4 and 6-20, independent claims 1 and 10, from which claims 2-4 and 6-20 depend and inherit all limitations therefrom, recite "wherein the first electrode faces the photoelectric conversion layer without an insulating layer between the first electrode and the photoelectric conversion layer", which were not found to be described in the specification, as required by the written description requirement.
The written description has not been found to support this negative limitation. In other words, the written description has not been found to disclose, discuss or describe avoiding, preventing or intentionally/purposefully not including an insulating layer between the first electrode and the photoelectric conversion layer. In fact, the written description is devoid of any discussion on this subject. Not describing an element in the written description does not expressly mean that the element is not intended to be included or that the element cannot be included. A negative limitation must have basis in the original disclosure, with the specification being a written description of the invention and of the manner and process of making and using the same. In this case, no support for the amended language has been found in Applicant’s written description. The Office notes that although Applicant attempts to attach support through the drawings, the determination of the subject matter in the inventor(s) possession is though being described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s) had possession of the claimed invention. The fact that the drawings lack to illustrate an element, does not provide convincing support that the element was not intended or could not be included. In this instance, the intentional exclusion of an element, i.e., “wherein the first electrode faces the photoelectric conversion layer without an insulating layer between the first electrode and the photoelectric conversion layer”, has not been found to be described in the specification, as required by the written description requirement. In view of at least the above, the claims, as currently presented, are rejected as failing to comply with the written description requirement.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2016/0014364 to Tashiro et al. (hereinafter “Tashiro”) in view of U.S. Patent No. 9,754,980 to Yamazaki et al. (hereinafter “Yamazaki”).
Regarding claim 1, Tashiro teaches an imaging device (e.g., fig. 2; fig. 14) comprising pixels (e.g., fig. 2, element 100; fig. 14; [0211]) each including a photoelectric converter (e.g., fig. 1A, element 101; [0043]; fig. 14; [0211]) including a first electrode (e.g., fig. 1A, element 209; [0043]; fig. 14; [0211]), a second electrode (e.g., fig. 1A, element 201; [0043]; fig. 14; [0211]), and a photoelectric conversion layer (e.g., fig. 1A, element 205; [0043]; fig. 14; [0211]) between the first electrode and the second electrode (e.g., fig. 1A; [0211]), and a charge accumulation region (e.g., fig. 1A and 13, Node B; [0088]) electrically connected to the first electrode (e.g., fig. 1, connected to element 209; [0088]), wherein the first electrode is configured to collect a signal charge generated in the photoelectric conversion layer (e.g., fig. 6B and 6C; [0088-91]), wherein the charge accumulation region is configured to accumulate the signal charge generated in the photoelectric conversion layer (e.g., figs. 6B and 6C; [0090-91]), and wherein the first electrode faces the photoelectric conversion layer (e.g., fig. 1A), and voltage supply circuitry (e.g., fig. 1A, element 110; [0043-44]; fig. 14; [0211]) configured to supply a first voltage to respective second electrodes in an exposure period (e.g., fig. 1A; [0044], Vs1; [0048], [0082]) and a second voltage different from the first voltage to the respective second electrodes in a non-exposure period (e.g., fig. 1A; [0044], Vs2; [0048], [0087-88]), wherein the voltage supply circuitry starts the exposure period by switching the voltage supplied to the respective second electrodes from the second voltage to the first voltage (e.g., the transition from fig. 6B to fig. 6C, illustrating Voltage Vs2 switching to Vs1 at the second electrode 201), and ends the exposure period by switching the voltage supplied to the respective second electrodes from the first voltage to the second voltage (e.g., upon repeat of the cycle, fig. 6A to fig. 6B, illustrating Voltage Vs1 switching to Vs2 at the second electrode 201), and the exposure period starts and ends in common for the pixels.
Tashiro, however, has not been found by the Examiner to expressly disclose wherein the first electrode faces the photoelectric conversion layer without an insulating layer between the first electrode and the photoelectric conversion layer.
Nevertheless, Yamazaki teaches a well-known photoelectric conversion element that includes a first electrode (e.g., fig. 1A, element 101; col. 6, lines 15-23), a second electrode (e.g., fig. 1A, element 104; col. 6, lines 15-23), a photoelectric conversion layer between the first electrode and the second electrode (e.g., fig. 1A, element 102; col. 6, lines 15-23), wherein the first electrode faces the photoelectric conversion layer without an insulating layer between the first electrode and the photoelectric conversion layer (e.g., fig. 1A). It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to have substituted the elements as taught by Yamazaki, in place of the elements included in the teachings of Tashiro, in order to achieve the predictable results of further simplifying manufacturing and/or reducing material costs through eliminating of the inclusion of the insulating layer of the photoelectric conversion element.
Regarding claim 2, Tashiro and Yamazaki teach all the limitations of claim 2 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein the exposure period is a period for accumulating a respective signal charge in the charge accumulation region (e.g., ‘364 – [0046], [0082]).
Regarding claim 3, Tashiro and Yamazaki teach all the limitations of claim 3 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein each of the pixels includes a detection circuit that detects a respective signal charge (e.g., ‘364 – figs. 1A and 14, element 104).
Regarding claim 4, Tashiro and Yamazaki teach all the limitations of claim 4 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein each of the pixels includes a carrier blocking layer between the photoelectric conversion layer and the first electrode (e.g., ‘364 – figs. 1A and 5B, element 207), the carrier blocking layer being configured to block a carrier, a polarity of the carrier being different from that of the signal charge generated by photoelectric conversion (e.g., ‘364 – [0077], [0088-97]).
Regarding claim 6, Tashiro and Yamazaki teach all the limitations of claim 6 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein the imaging device is configured to allow light to be incident to respective photoelectric converters of the pixels even in the non-exposure period (e.g., ‘364 – figs. 2 and 14, no blocking structure associated with the recited imaging device).
Regarding claim 7, Tashiro and Yamazaki teach all the limitations of claim 7 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein a first potential difference between the first electrode and the second electrode in the exposure period is greater than a second potential difference between the first electrode and the second electrode in the non-exposure period (e.g., ‘364 – figs. 6A-6F).
Regarding claim 8, Tashiro and Yamazaki teach all of the limitations of claim 8 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein respective second electrodes of the pixels are electrically connected to one another (e.g., ‘364 – fig. 5A and 5B; and fig. 1A, at least all connected to ground).
Regarding claim 9, Tashiro and Yamazaki teach all the limitations of claim 9 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein each of the pixels includes a transistor having a gate that is electrically connected to a respective first electrode without interposing another transistor (e.g., ‘364 – fig. 1A, element 104; fig. 1A, element 102, form/limits of electrical connectivity is not defined by the claim; fig. 14, element 501; [0211], form/limits of electrical connectivity is not defined by the claim).
Regarding claim 10, Tashiro teaches an imaging device (e.g. fig. 2; fig. 14) comprising pixels (e.g., fig. 2, element 100; fig. 14; [0211]) each including a photoelectric converter (e.g., fig. 1A, element 101; [0043]; fig. 14; [0211]) including a first electrode (e.g., fig. 1A, element 209; [0043]; fig. 14; [0211]), a second electrode (e.g., fig. 1A, element 201; [0043]; fig. 14; [0211]), a photoelectric conversion layer (e.g., fig. 1A, element 205; [0043]; fig. 14; [0211]) between the first electrode and the second electrode (e.g., fig. 1A; [0211]), and a charge accumulation region (e.g., fig. 1A and 13, Node B; [0088]) electrically connected to the first electrode (e.g., fig. 1, connected to element 209; [0088]), wherein the first electrode is configured to collect a signal charge generated in the photoelectric conversion layer (e.g., fig. 6B and 6C; [0088-91]), wherein the charge accumulation region is configured to accumulate the signal charge generated in the photoelectric conversion layer (e.g., figs. 6B and 6C; [0090-91]), and wherein the first electrode faces the photoelectric conversion layer (e.g., fig. 1A), and voltage supply circuitry (e.g., fig. 1A, element 110; [0043]; fig. 14; [0211]) configured to supply a first voltage to respective second electrodes in an exposure period (e.g., fig. 1A; [0048], [0082]) and a second voltage different from the first voltage to the respective second electrodes in a non-exposure period (e.g., fig. 1A; [0048], [0087-88]), wherein the voltage supply circuitry starts the exposure period by switching the voltage supplied to the respective second electrodes from the second voltage to the first voltage (e.g., the transition from fig. 6B to fig. 6C, illustrating Voltage Vs2 switching to Vs1 at the second electrode 201), and ends the exposure period by switching the voltage supplied to the respective second electrodes from the first voltage to the second voltage (e.g., upon repeat of the cycle, fig. 6A to fig. 6B, illustrating Voltage Vs1 switching to Vs2 at the second electrode 201), the exposure period starts and ends in common for the pixels, each of the pixels includes a transistor having a gate that is electrically connected to a respective first electrode without interposing another transistor (e.g., fig. 1A, element 104; fig. 1A, element 102, form/limits of electrical connectivity is not defined by the claim; fig. 14, element 501; [0211], form/limits of electrical connectivity is not defined by the claim).
Tashiro, however, has not been found by the Examiner to expressly disclose wherein the first electrode faces the photoelectric conversion layer without an insulating layer between the first electrode and the photoelectric conversion layer.
Nevertheless, Yamazaki teaches a well-known photoelectric conversion element that includes a first electrode (e.g., fig. 1A, element 101; col. 6, lines 15-23), a second electrode (e.g., fig. 1A, element 104; col. 6, lines 15-23), a photoelectric conversion layer between the first electrode and the second electrode (e.g., fig. 1A, element 102; col. 6, lines 15-23), wherein the first electrode faces the photoelectric conversion layer without an insulating layer between the first electrode and the photoelectric conversion layer (e.g., fig. 1A). It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to have substituted the elements as taught by Yamazaki, in place of the elements included in the teachings of Tashiro, in order to achieve the predictable results of further simplifying manufacturing and/or reducing material costs through eliminating of the inclusion of the insulating layer of the photoelectric conversion element.
Regarding claim 11, Tashiro and Yamazaki teach all the limitations of claim 11 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein the exposure period is a period for accumulating a respective signal charge in the charge accumulation region (e.g., ‘364 – [0046], [0082]).
Regarding claim 12, Tashiro and Yamazaki teach all the limitations of claim 12 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein the transistor is configured to output a signal corresponding to a potential of the gate (e.g., ‘364 – fig. 1A, element 104).
Regarding claim 13, Tashiro and Yamazaki teach all the limitations of claim 13 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein each of the pixels includes a carrier blocking layer between the photoelectric conversion layer and the first electrode (e.g., ‘364 – figs. 1A and 5B, element 207), the carrier blocking layer being configured to block a carrier, a polarity of the carrier being different from that of the signal charge (e.g., [0077], [0088-97]).
Regarding claim 14, Tashiro and Yamazaki teach all the limitations of claim 14 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein the imaging device is configured to allow light to be incident to respective photoelectric converters of the pixels even in the non-exposure period (e.g., ‘364 – figs. 2 and 14, no blocking structure associated with the recited imaging device).
Regarding claim 15, Tashiro and Yamazaki teach all the limitations of claim 15 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein a first potential difference between the first electrode and the second electrode in the exposure period is greater than a second potential difference between the first electrode and the second electrode in the non-exposure period (e.g., ‘364 – figs. 6A-6F).
Regarding claim 16, Tashiro and Yamazaki teach all the limitations of claim 16 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein respective second electrodes of the pixels are electrically connected to one another (e.g., ‘364 – fig. 5A and 5B; and fig. 1A, at least all connected to ground).
Regarding claim 17, Tashiro and Yamazaki teach all the limitations of claim 17 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein respective second electrodes of the pixels constitute a single electrode (e.g., ‘364 – [0064], common electrodes).
Regarding claim 18, Tashiro and Yamazaki teach all the limitations of claim 18 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein respective second electrodes of the pixels constitute a single electrode (e.g., ‘364 – [0064], common electrodes).
Regarding claim 19, Tashiro and Yamazaki teach all the limitations of claim 19 (see the 35 U.S.C.103 rejection of claim 1, supra) including teaching wherein the first electrode is electrically connected to the photoelectric conversion layer (e.g., ‘364 – figs. 1A and 6; [0088-91]).
Regarding claim 20, Tashiro and Yamazaki teach all the limitations of claim 20 (see the 35 U.S.C.103 rejection of claim 10, supra) including teaching wherein the first electrode is electrically connected to the photoelectric conversion layer (e.g., ‘364 – figs. 1A and 6; [0088-91]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GARY C VIEAUX whose telephone number is (571)272-7318. The examiner can normally be reached Increased Flex.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GARY C VIEAUX/Primary Examiner, Art Unit 2638
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