Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 04/06/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of patent number 11,994,951 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6,9-14,16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210072924 A1 (Li) in view of US 20190013079 A1 (Blodgett).
Regarding claim 2, Li teaches
A memory system, comprising:
one or more non-volatile memory devices; (fig 1:100; par 12 “A user or an operator at the factory side manually uses the host device 101, e.g. a computer device, to execute a testing procedure (or an automatic testing procedure/program) to test multiple storage devices 100 which are individually coupled to the host device 101 for the mass production testing.” ) and
one or more controllers coupled with the one or more non-volatile memory devices and configured to cause the memory system to: (fig 1:105; par 13 “The storage device 100 comprises a flash memory controller 105, a DRAM 110 externally coupled to the flash memory controller 105, and a flash memory 115 (e.g. a NAND-type flash memory) externally coupled to the flash memory controller 105.” )
allocate memory associated with event alerts of the memory system, and sending a signal to perform a reset operation of the memory system;( fig 2:225; par 32 “In Step 225, the processor 1052 receives the reset trigger signal from the watchdog timer 1051, and then is arranged to control the memory controller 1053 by sending a first control signal to the memory controller 1053 via the internal bus. In this situation, the processor 1052 determines that a fault/failure occurs, then retries the corresponding fault/failure information used for debugging, and then copies and stores the corresponding fault/failure information into the DRAM 110 by controlling the memory controller 1053 to write the corresponding fault/failure information into the DRAM 1053.”, par 33 “The corresponding fault/failure information for example comprises at least one of registry information of the processor 1052, registry information of the flash memory interface controller 1054, and registry information of the protocol controller 1055.”)
save, to DRAM, a message comprising fault/failure information in response to determining that a fault has occurred;( fig 2:225; par 32 “ In this situation, the processor 1052 determines that a fault/failure occurs, then retries the corresponding fault/failure information used for debugging, and then copies and stores the corresponding fault/failure information into the DRAM 110 by controlling the memory controller 1053 to write the corresponding fault/failure information into the DRAM 1053.”, par 33 “The corresponding fault/failure information for example comprises at least one of registry information of the processor 1052, registry information of the flash memory interface controller 1054, and registry information of the protocol controller 1055.”; par 45; the contents of the register is fault/failure information, which Li teaches sending to DRAM.) and
perform the reset operation of the memory system(fig 2:240; par 37 “… in Step 240 the processor 1052 is arranged to reset the current registry information of the flash memory interface controller 1054…”) in response to saving the fault/failure information. (fig 2:225; par 23 “Step 225: Copy the corresponding fault/failure information used for debugging into the DRAM 110;”; fig 2:240; par 37 “Instead, when it is determined that the flash memory interface controller is abnormal in Step 230, then in Step 240 the processor 1052 is arranged to reset the current registry information of the flash memory interface controller 1054 and then in Step 245 is arranged to send the second control signal to the flash memory interface controller 1054 to control the flash memory interface controller 1054 to write at least one portion of the corresponding fault/failure information which has been recorded in the DRAM 110 previously into the flash memory 115.”; par 18 “Provided that substantially the same result is achieved, the steps of the flowchart shown in FIG. 2 need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate.” Step 240(the reset operation step) comes after step 225(the transmit failure information step))
However, although Li teaches allocating memory for fault information(interpreted as event alerts), and saving the fault information in memory, Li does not specifically teach allocate one or more bits of a register associated with event alerts of the memory system, the one or more bits indicating to perform a reset operation of the memory system; or transmit, to a host system, a message comprising contents of the register in response to allocating the one or more bits;
On the other hand, Blodgett teaches,
A memory system, comprising:
one or more non-volatile memory devices;(fig 1:170; par 34 “Storage 170 may be one or more NAND storage cells or storage devices segmented into a plurality of Logical Unit (LU)s 0-N (155, 160, 165) which handle read/write and other storage related commands.”) and
one or more controllers coupled with the one or more non-volatile memory devices and configured to cause the memory system to:(fig 2:150; par 34 “UFS device 140 features a device level manager 150 that provides for device level features such as power management, and the like (which may be executed by memory controller 1001 of FIG. 10).”; fig 10:1001 par 87 “FIG. 10 illustrates an example block diagram of a memory device 1000 (e.g., a storage device, such as a UFS device 140 from FIG.1) including a memory controller 1001 and a memory array 1002 having a plurality of memory cells 1004, and a host 1005 external to the memory device 1000.”)
allocate one or more bits of a register associated with event alerts of the memory system, the one or more bits indicating event alerts of the memory system;(par 43 “For example, circuitry and/or firmware within the controller of the memory device may respond to a temperature sensor output indicating the crossing of a temperature threshold ( either internal or external ambient sensors), by setting a temperature too high exception event register, and throttling performance. In other examples, the circuitry and/or firmware may set a performance throttling exception event register and throttle performance.”; par 47 “The exception event mechanism may have three components: a status attribute, a control attribute, and an alert flag. The control attribute … . The alert flag … . The status attribute may indicate which exception events are currently active at the NAND memory device. For example, a bit may be set in the status attribute indicating that performance throttling is ongoing. Other bits may correspond to other exception events.”)
transmit, to a host system, a message comprising contents of the register in response to allocating the one or more bits; (par 47 “The exception event mechanism may have three components: a status attribute, a control attribute, and an alert flag. The control attribute may be set by the host to the exception events the host is interested in receiving an alert for. The alert flag may be set when one of the exception events the host is interested in is active. The status attribute may indicate which exception events are currently active at the NAND memory device. For example, a bit may be set in the status attribute indicating that performance throttling is ongoing. Other bits may correspond to other exception events. If at least one of the status attributes are set and the corresponding control attribute is set, the alert flag may be set to indicate that the exception event is present. The alert flag may be passed to the host in a response UPIU message or in other ways such as a notification.”)and
perform the error handling operation of the memory system in response to transmitting the message.(par 62 “In some examples, an initiator identifier (e.g., an IID) information field may be added to the register. … . If the initiator that reads the result register detects that its IID differs from the IID in the result, the host may be alerted to an error and perform proper error handling.”; par 56 “At operation 1630, the host may determine that the response indicates that an event alert bit is set, and if so, the host may then read the wExceptionEventStatus attribute to determine that the performance throttling event is set.”; par 43 “For example, circuitry and/or firmware within the controller of the memory device may respond to a temperature sensor output indicating the crossing of a temperature threshold ( either internal or external ambient sensors), by setting a temperature too high exception event register, and throttling performance. In other examples, the circuitry and/or firmware may set a performance throttling exception event register and throttle performance.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Li to incorporate the register, the register bits, and transmit, to a host system, a message comprising contents of the register in response to allocating the one or more bits of Blodgett. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Li -- a need for how to store and notify hosts of exception events in memory devices -- with Blodgett providing a known method to solve a similar problem. Blodgett provides “FIG. 15 illustrates a flowchart of a method 1500 of performance throttling according to some examples of the present disclosure. At operation 1510, the memory device may determine that a condition has occurred that indicates a need for a performance throttling operation. … At operation 1530, the memory device may set a performance throttling status indicator in an exception event status attribute. For example, setting a bit in a wExceptionEventStatus attribute of the memory device. … At operation 1560, the memory device may provide a response to the command with a response (e.g., UPIU response). The UPIU response may set a flag (EVENT_STATUS) in the response indicating whether any exception events (e.g., a performance throttling event) are indicated in the attributes (e.g., in a wExceptionEventStatus attribute). In some examples, the UPIU response may set a flag (EVENT_ STATUS) in the response indicating whether any exception events are indicated in the attributes (e.g., in a wExceptionEventStatus attribute) only if at least one exception event is indicated that also has a corresponding flag set in a control attribute such as a wExceptionEventControl attribute.”(Blodgett par 15)
Regarding claim 3, Li and Blodgett teaches,
The memory system of claim 2,
Li further teaches,
wherein the one or more controllers are further configured to cause the memory system to:
receive a second message from the host system, the second message requesting the contents of the register,(par 12 “In this situation, the user or operator can use a parse software tool of the testing procedure/program to retrieve or read the corresponding fault/failure information from the storage device 100 and then to parse/analyze the corresponding fault/failure information to display information on a screen of the host device 101 for the user/operator.”)
wherein transmitting the message is in response to receiving the second message.(par 45 “… the host device 101 loads the corresponding fault/failure information from the flash memory 115.”; par 46 “In Step 320, after receiving a portion or all of the corresponding fault/failure information, the host device 101 is arranged to …”)
Regarding claim 4, Li and Blodgett teaches,
The memory system of claim 2,
Li further teaches,
wherein the one or more controllers are further configured to cause the memory system to:
receive a command to perform the reset operation in response to transmitting the message,(fig 2:225; par 32 “In Step 225, the processor 1052 receives the reset trigger signal from the watchdog timer 1051, and then is arranged to control the memory controller 1053 by sending a first control signal to the memory controller 1053 via the internal bus. In this situation, the processor 1052 determines that a fault/failure occurs, then retries the corresponding fault/failure information used for debugging, and then copies and stores the corresponding fault/failure information into the DRAM 110 by controlling the memory controller 1053 to write the corresponding fault/failure information into the DRAM 1053.”)
wherein performing the reset operation is in response to receiving the command. (fig 2:240; par 37 “Instead, when it is determined that the flash memory interface controller is abnormal in Step 230, then in Step 240 the processor 1052 is arranged to reset the current registry information of the flash memory interface controller 1054 and then in Step 245 is arranged to send the second control signal to the flash memory interface controller 1054 to control the flash memory interface controller 1054 to write at least one portion of the corresponding fault/failure information which has been recorded in the DRAM 110 previously into the flash memory 115.”)
Regarding claim 5, Li and Blodgett teaches,
The memory system of claim 2,
Li further teaches,
wherein the one or more controllers are further configured to cause the memory system to:
identify one or more fault conditions of the one or more non-volatile memory devices, the one or more fault conditions being associated with resetting the memory system,(par 15 “Each storage device 100 is arranged to initiate the watchdog timer 1051 when the storage device 100 is powered on to be tested. The watchdog timer 1051 is used to detect whether a fault/failure of a corresponding storage device 100 occurs.”, fig 2:225; par 32 “In Step 225, the processor 1052 receives the reset trigger signal from the watchdog timer 1051, and then is arranged to control the memory controller 1053 by sending a first control signal to the memory controller 1053 via the internal bus. In this situation, the processor 1052 determines that a fault/failure occurs, then retries the corresponding fault/failure information used for debugging, and then copies and stores the corresponding fault/failure information into the DRAM 110 by controlling the memory controller 1053 to write the corresponding fault/failure information into the DRAM 1053.”)
wherein allocating the one or more bits is in response to identifying the one or more fault conditions. (fig 2:225; par 32 “In Step 225, the processor 1052 receives the reset trigger signal from the watchdog timer 1051, and then is arranged to control the memory controller 1053 by sending a first control signal to the memory controller 1053 via the internal bus. In this situation, the processor 1052 determines that a fault/failure occurs, then retries the corresponding fault/failure information used for debugging, and then copies and stores the corresponding fault/failure information into the DRAM 110 by controlling the memory controller 1053 to write the corresponding fault/failure information into the DRAM 1053.”, par 33 “The corresponding fault/failure information for example comprises at least one of registry information of the processor 1052, registry information of the flash memory interface controller 1054, and registry information of the protocol controller 1055.”)
Regarding claim 6, Li and Blodgett teaches,
The memory system of claim 5,
Li further teaches,
wherein the one or more controllers are further configured to cause the memory system to:
store parameter information about an operation of the memory system in response to identifying the one or more fault conditions,( fig 2:225; par 32 “In Step 225, the processor 1052 receives the reset trigger signal from the watchdog timer 1051, and then is arranged to control the memory controller 1053 by sending a first control signal to the memory controller 1053 via the internal bus. In this situation, the processor 1052 determines that a fault/failure occurs, then retries the corresponding fault/failure information used for debugging, and then copies and stores the corresponding fault/failure information into the DRAM 110 by controlling the memory controller 1053 to write the corresponding fault/failure information into the DRAM 1053.”)
wherein transmitting the message is in response to storing the parameter information. (fig 2:225; par 23 “Step 225: Copy the corresponding fault/failure information used for debugging into the DRAM 110;”; fig 2:240; par 37 “… in Step 240 the processor 1052 is arranged to reset the current registry information of the flash memory interface controller 1054 and then in Step 245 is arranged to send the second control signal to the flash memory interface controller 1054 to control the flash memory interface controller 1054 to write at least one portion of the corresponding fault/failure information which has been recorded in the DRAM 110 previously into the flash memory 115.”; par 18 “Provided that substantially the same result is achieved, the steps of the flowchart shown in FIG. 2 need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate.”)
Regarding claim 9, Li and Blodgett teaches,
The memory system of claim 2,
Li further teaches,
wherein the message comprises a query response to the host system. (par 12 “In this situation, the user or operator can use a parse software tool of the testing procedure/program to retrieve or read the corresponding fault/failure information from the storage device 100 and then to parse/analyze the corresponding fault/failure information to display information on a screen of the host device 101 for the user/operator.”)
Regarding claims 10-14, they are the non-transitory computer-readable medium containing instructions that the apparatus of claims 2-6 implement and are rejected for the same reasons.
Regarding claims 16-20, they are the method that the apparatus of claims 2-6 implement and are rejected for the same reasons.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210072924 A1 (Li) in view of US 20190013079 A1 (Blodgett) as applied to claim 2 above, and further in view of US 11094393 B1 (Alavoine).
Regarding claim 8, Li and Blodgett teaches,
The memory system of claim 2,
Li further teaches,
wherein, to perform the reset operation, the one or more controllers are further configured to cause the memory system to reset the one or more non-volatile memory controller(fig 2:240; par 37 “… in Step 240 the processor 1052 is arranged to reset the current registry information of the flash memory interface controller 1054…”)
However, Li and Blodgett does not specifically teach reset the one or more non-volatile memory devices.
On the other hand, Alavoine teaches,
A memory system with a memory controller(fig 1:114; col 5 ln 20-26 “The memory controller 114 may also manage maintenance of the memory 124, such as scheduling and/or initiating refresh cycles, and as described herein, clear content ( e.g., data and/or code) commands. In some examples, the memory controller 114 may include one or more processors configured to perform the operations disclosed herein.”) and a mode register that contains bits for a clear content command that clears a corresponding memory cell; (col 9 ln 42-45 “In some examples, the clear content command may be written to a mode register. The memory controller 114 may then read the mode register according to a periodic interval and execute the clear content command.” col 10 ln 29-34 “Thus, to execute the clear content command, the memory controller 114 may activate one of the switches at the gate of the switch using a clear command signal (e.g., shown in FIG. 7 as "CB" or "C"), thereby grounding the BL 702 or BLB 704, and clearing a corresponding memory cell.”)
wherein, to perform the reset operation, the one or more controllers are further configured to cause the memory system to reset the one or more non-volatile memory devices.(fig 6:610,620; col 9 ln 61-64 “If a clear content command has been written to the mode register, then, at block 610, the memory controller 114 may determine whether the clear content command has been executed.” Col 9-10 ln 66-2 “If the clear content command has not been executed, the process 600 may advance to block 615 where the memory controller 114 executes the clear content command.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Li to incorporate the reset of non-volatile memory devices of Alavoine. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Li -- a need for a solution for the issue of how to respond to RAM errors(Alavoine col 1 ln 15-46 “One of the disadvantages is that a RAM may occasionally experience errors … As RAM devices are utilized more, there exists a need for further improvements to such devices.”)-- with Alavoine providing a known method to solve a similar problem. Alavoine provides “Certain embodiments provide a method of clearing content stored on a memory of an electronic device, the memory comprising a plurality of memory banks on each of which a plurality of memory cells are arranged, each of the plurality of memory cells coupled to an associated sense amplifier.”(Alavoine col 1 ln 58-62 )
Claim(s) 7,15,21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210072924 A1 (Li) in view of US 20190013079 A1 (Blodgett) as applied to claim 2 above, and further in view of US 20220382611 A1 (Kapish) and US 20220148674 A1 (Qiao).
Regarding claim 7, Li and Blodgett teaches,
The memory system of claim 2,
Li further teaches,
wherein, to allocate the one or more bits,( par 33 “The corresponding fault/failure information for example comprises at least one of registry information of the processor 1052, registry information of the flash memory interface controller 1054, and registry information of the protocol controller 1055.”;)
However, Li and Blodgett do not specifically go into detail about what other parameters are monitored.
On the other hand, Kapish teaches,
An anomaly detection and resolution system(par 4 “In one embodiment, a method comprises collecting operational data for one or more devices and identifying one or more anomalies associated with the one or more devices based at least in part on the collected operational data. At least a portion of the collected operational data corresponding to the identified one or more anomalies is analyzed, and a probability of automatic resolution for respective ones of the identified one or more anomalies is determined based at least in part on the analysis.”),
the one or more controllers are further configured to cause the memory system to:
allocate a second bit of the register to indicate that a first threshold capacity of a storage area associated with system data is satisfied; (par 26 “As used herein, "telemetry data" is to be broadly construed to include, for example, performance metrics such as, but not necessarily limited to, throughput, latency, memory capacity and usage, response and completion time, communication failures, temperature, channel capacity and bandwidth or other types of data which may be collected via, for example, sensors or other equipment or software associated with a client device 102.”)
allocate a third bit of the register to indicate that a level of need associated with background operations of the memory system is above a first threshold; (par 26 “As used herein, "telemetry data" is to be broadly construed to include, for example, performance metrics such as, but not necessarily limited to, throughput, latency, memory capacity and usage, response and completion time, communication failures, temperature, channel capacity and bandwidth or other types of data which may be collected via, for example, sensors or other equipment or software associated with a client device 102.”);
allocate a fourth bit of the register to indicate that a temperature of the memory system is above a second threshold; (par 26 “As used herein, "telemetry data" is to be broadly construed to include, for example, performance metrics such as, but not necessarily limited to, throughput, latency, memory capacity and usage, response and completion time, communication failures, temperature, channel capacity and bandwidth or other types of data which may be collected via, for example, sensors or other equipment or software associated with a client device 102.”);
allocate a fifth bit of the register to indicate that the temperature of the memory system is below a third threshold; (par 26 “As used herein, "telemetry data" is to be broadly construed to include, for example, performance metrics such as, but not necessarily limited to, throughput, latency, memory capacity and usage, response and completion time, communication failures, temperature, channel capacity and bandwidth or other types of data which may be collected via, for example, sensors or other equipment or software associated with a client device 102.”);
allocate a sixth bit of the register to indicate that a second threshold capacity of a write booster is satisfied; (par 26 “As used herein, "telemetry data" is to be broadly construed to include, for example, performance metrics such as, but not necessarily limited to, throughput, latency, memory capacity and usage, response and completion time, communication failures, temperature, channel capacity and bandwidth or other types of data which may be collected via, for example, sensors or other equipment or software associated with a client device 102.”) and
allocate a seventh bit of the register to indicate that the memory system is operating at a reduced performance. (par 26 “As used herein, "telemetry data" is to be broadly construed to include, for example, performance metrics such as, but not necessarily limited to, throughput, latency, memory capacity and usage, response and completion time, communication failures, temperature, channel capacity and bandwidth or other types of data which may be collected via, for example, sensors or other equipment or software associated with a client device 102.”)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Li and Blodgett to incorporate the telemetry monitoring parameters of Kapish. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Li and Blodgett -- a need for a solution for the issue of how to identify anomalies -- with Kapish providing a known method to solve a similar problem. Kapish provides “a method comprises collecting operational data for one or more devices and identifying one or more anomalies associated with the one or more devices based at least in part on the collected operational data. At least a portion of the collected operational data corresponding to the identified one or more anomalies is analyzed, and a probability of automatic resolution for respective ones of the identified one or more anomalies is determined based at least in part on the analysis.”(Kapish par 4)
However, Li, Blodgett, and Kapish do not specifically teach allocate a first bit of the register for requesting that a host system remove resources from a physical memory resources pool;
On the other hand, Qiao teaches,
A memory fault handling method and apparatus(par 6 “a memory fault handling method and apparatus, a device, and a storage medium, to perform memory fault recovery in time, prevent system breakdown, and reduce adverse impact on services.” )
the one or more controllers are further configured to cause the memory system to:
allocate a first bit of the register for requesting that a host system remove resources from a physical memory resources pool;(fig 2:first bank, Other banks; par 39 “In other words, if the fault analysis result includes a fault mode, the starting fault recovery for the memory by the computer device based on the current fault analysis result of the memory includes: when the fault mode is a memory bank fault, starting fault recovery for the memory, where the fault recovery includes: replacing a faulty bank with a redundant bank, and recovering data in the redundant bank.” Par 42.)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify Li, Blodgett, and Kapish to incorporate the fault handling of Qiao. One of ordinary skill in the art would have been motivated to remedy the shortcomings of Li, Blodgett, and Kapish -- a need for a solution for the issue of how to analyze historical fault information to improve memory fault handling -- with Qiao providing a known method to solve a similar problem. Qiao provides “a memory fault handling method and apparatus, a device, and a storage medium, to perform memory fault recovery in time, prevent system breakdown, and reduce adverse impact on services.”(Qiao par 6) “In this embodiment of this application, a fault analysis result is obtained by analyzing the historical fault information, and then memory fault recovery is performed based on the fault analysis result.” (Qiao par 9)
Regarding claim 15, it is the non-transitory computer-readable medium containing instructions that the apparatus of claim 7 implements and is rejected for the same reasons.
Regarding claims 21, It is the method that the apparatus of claim 7 implements and is rejected for the same reasons.
Response to Arguments
Applicant’s arguments, see remarks pg. 8, filed 04/06/2026, with respect to the double patenting rejections have been fully considered and are persuasive. The double patenting rejections of 01/07/2026 has been withdrawn.
Applicant’s arguments, see remarks pg. 9-12, filed 04/06/2026, with respect to the rejection(s) of claim(s) independent claims 2, 10, and 16 under 35 U.S.C. 103 as being unpatentable over US 20210072924 A1 (Li) in view of US 11094393 B1 (Alavoine) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 U.S.C. 103 as being unpatentable over US 20210072924 A1 (Li) in view of US 20190013079 A1 (Blodgett).
With respect to the independent claims, the applicant has argued that Li and Alavoine does not teach limitations “allocate one or more bits of a register associated with event alerts of the memory system, the one or more bits indicating to perform a reset operation of the memory system;” explaining that Li instead stores fault/failure information in a flash memory or in DRAM and does not teach allocating bits of a register. The examiner respectfully disagrees. although Li does not mention a register, Li teaches storing event alerts in the cited (fig 2:225; par 32 “In Step 225, the processor 1052 receives the reset trigger signal from the watchdog timer 1051… and then copies and stores the corresponding fault/failure information into the DRAM 110 by controlling the memory controller 1053 to write the corresponding fault/failure information into the DRAM 1053.”). Although Li does not teach allocating bits of a register, Li does teach storing event alerts of the memory system in the form of fault/failure information. The examiner interprets this as limitations “allocate memory associated with event alerts of the memory system, and sending a signal to perform a reset operation of the memory system;”.
The rejection of the independent claims is based on Li and Blodgett. Blodgett teaches the missing register and bits limitations not covered by Li in the cited (par 43 “For example, circuitry and/or firmware within the controller of the memory device may respond to a temperature sensor output indicating the crossing of a temperature threshold ( either internal or external ambient sensors), by setting a temperature too high exception event register, and throttling performance. In other examples, the circuitry and/or firmware may set a performance throttling exception event register and throttle performance.”; par 47 “The exception event mechanism may have three components: a status attribute, a control attribute, and an alert flag. The control attribute … . The alert flag … . The status attribute may indicate which exception events are currently active at the NAND memory device. For example, a bit may be set in the status attribute indicating that performance throttling is ongoing. Other bits may correspond to other exception events.”). The par 43 citation explains that there is an event register that stores event alerts. The par 47 citation explains that the exception event may contain flags and bits that show status. Together this shows that Blodgett teaches limitation “allocate one or more bits of a register associated with event alerts of the memory system, the one or more bits indicating event alerts of the memory system”. Blodgett does not specifically talk about resetting, but Li does, and together they cover all the limitations.
With respect to the independent claims, the applicant has also argued that Li and Alavoine does not teach limitations “transmit, to a host system, a message comprising contents of the register in response to allocating the one or more bits; and perform the reset operation of the memory system in response to transmitting the message.”. The examiner respectfully disagrees.
Regarding the newly amended limitation “transmit, to a host system, a message comprising contents of the register in response to allocating the one or more bits;”, the newly cited Blodgett teaches in the cited (par 47 “The exception event mechanism may have three components: a status attribute, a control attribute, and an alert flag. … If at least one of the status attributes are set and the corresponding control attribute is set, the alert flag may be set to indicate that the exception event is present. The alert flag may be passed to the host in a response UPIU message or in other ways such as a notification.”). The examiner interprets this as limitations “transmit, to a host system, a message comprising contents of the register in response to allocating the one or more bits;”.
Regarding limitation “and perform the reset operation of the memory system in response to transmitting the message.”, Li teaches in the cited (fig 2:240; par 37 “… in Step 240 the processor 1052 is arranged to reset the current registry information of the flash memory interface controller 1054…”; and fig 2:225; par 23 “Step 225: Copy the corresponding fault/failure information used for debugging into the DRAM 110;”; fig 2:240; par 37 “Instead, when it is determined that the flash memory interface controller is abnormal in Step 230, then in Step 240 the processor 1052 is arranged to reset the current registry information of the flash memory interface controller 1054 and then in Step 245 is arranged to send the second control signal to the flash memory interface controller 1054 to control the flash memory interface controller 1054 to write at least one portion of the corresponding fault/failure information which has been recorded in the DRAM 110 previously into the flash memory 115.”; par 18 “Provided that substantially the same result is achieved, the steps of the flowchart shown in FIG. 2 need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate.” Step 240(the reset operation step) comes after step 225(the transmit failure information step), and so is done in response to the transmit failure information step, with a normal status check done right before the reset is done(step 230).) examiner interprets this as limitation “and perform the reset operation of the memory system in response to transmitting the message.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210406143 A1 - Chaiken - finds memory faults by testing during runtime. Handles failed tests accordingly. Does not specifically mention reset.
US 20220334920 A1 - Ho - detects system fault and copies over memory, initializes and runs the copied over commands.
US 20210326209 A1 - Hasegawa - anomaly detector that resets components when a failure is detected. Uses registers to mark what needs resetting. Detects failures in components, not necessarily memory.
US 20210191795 A1 - Misra - error condition detected, stores memory contents, then resets memory. Also has temperature threshold.
US 20230106369 A1 - Flynn - Dynamic policy based on resource consumption
US 20230026064 A1 - Kulkarni - par 24 " For example, the parameters may be, but not limited to, temperature at the node, storage space available, and load on nodes. Appropriate types of sensors, in required quantities, are deployed based on their sensing capability to measure/sense the plurality of parameters."
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/M.X./Examiner, Art Unit 2113
/MARC DUNCAN/Primary Examiner, Art Unit 2113
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